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__init__.py
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__init__.py
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"""
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from __future__ import print_function
import struct
import traceback
import os
from binaryninja.architecture import Architecture
from binaryninja.lowlevelil import LowLevelILLabel, LLIL_TEMP
from binaryninja.function import RegisterInfo, InstructionInfo, InstructionTextToken
from binaryninja.binaryview import BinaryView
from binaryninja.plugin import PluginCommand
from binaryninja.interaction import AddressField, ChoiceField, get_form_input
from binaryninja.types import Symbol
from binaryninja.log import log_error
from binaryninja.enums import (Endianness, BranchType, InstructionTextTokenType,
LowLevelILOperation, LowLevelILFlagCondition, FlagRole, SegmentFlag,
ImplicitRegisterExtend, SymbolType)
# Shift syles
SHIFT_SYLE_ARITHMETIC = 0,
SHIFT_SYLE_LOGICAL = 1,
SHIFT_SYLE_ROTATE_WITH_EXTEND = 2,
SHIFT_SYLE_ROTATE = 3,
ShiftStyle = [
'as', # SHIFT_SYLE_ARITHMETIC
'ls', # SHIFT_SYLE_LOGICAL
'rox', # SHIFT_SYLE_ROTATE_WITH_EXTEND
'ro' # SHIFT_SYLE_ROTATE
]
BITFIELD_STYLE_TST = 0,
BITFIELD_STYLE_EXTU = 1,
BITFIELD_STYLE_CHG = 2,
BITFIELD_STYLE_EXTS = 3,
BITFIELD_STYLE_CLR = 4,
BITFIELD_STYLE_FFO = 5,
BITFIELD_STYLE_SET = 6,
BITFIELD_STYLE_INS = 7,
BitfieldStyle = [
"tst", # BITFIELD_STYLE_TST
"extu", # BITFIELD_STYLE_EXTU
"chg", # BITFIELD_STYLE_CHG
"exts", # BITFIELD_STYLE_EXTS
"clr", # BITFIELD_STYLE_CLR
"ffo", # BITFIELD_STYLE_FFO
"set", # BITFIELD_STYLE_SET
"ins", # BITFIELD_STYLE_INS
]
# Condition codes
CONDITION_TRUE = 0
CONDITION_FALSE = 1
CONDITION_HIGH = 2
CONDITION_LESS_OR_SAME = 3
CONDITION_CARRY_CLEAR = 4
CONDITION_CARRY_SET = 5
CONDITION_NOT_EQUAL = 6
CONDITION_EQUAL = 7
CONDITION_OVERFLOW_CLEAR = 8
CONDITION_OVERFLOW_SET = 9
CONDITION_PLUS = 10
CONDITION_MINUS = 11
CONDITION_GREATER_OR_EQUAL = 12
CONDITION_LESS_THAN = 13
CONDITION_GREATER_THAN = 14
CONDITION_LESS_OR_EQUAL = 15
Condition = [
't', # CONDITION_TRUE
'f', # CONDITION_FALSE
'hi', # CONDITION_HIGH
'ls', # CONDITION_LESS_OR_SAME
'cc', # CONDITION_CARRY_CLEAR
'cs', # CONDITION_CARRY_SET
'ne', # CONDITION_NOT_EQUAL
'eq', # CONDITION_EQUAL
'vc', # CONDITION_OVERFLOW_CLEAR
'vs', # CONDITION_OVERFLOW_SET
'pl', # CONDITION_PLUS
'mi', # CONDITION_MINUS
'ge', # CONDITION_GREATER_OR_EQUAL
'lt', # CONDITION_LESS_THAN
'gt', # CONDITION_GREATER_THAN
'le' # CONDITION_LESS_OR_EQUAL
]
# Registers
REGISTER_D0 = 0
REGISTER_D1 = 1
REGISTER_D2 = 2
REGISTER_D3 = 3
REGISTER_D4 = 4
REGISTER_D5 = 5
REGISTER_D6 = 6
REGISTER_D7 = 7
REGISTER_A0 = 8
REGISTER_A1 = 9
REGISTER_A2 = 10
REGISTER_A3 = 11
REGISTER_A4 = 12
REGISTER_A5 = 13
REGISTER_A6 = 14
REGISTER_A7 = 15
Registers = [
'd0', # REGISTER_D0
'd1', # REGISTER_D1
'd2', # REGISTER_D2
'd3', # REGISTER_D3
'd4', # REGISTER_D4
'd5', # REGISTER_D5
'd6', # REGISTER_D6
'd7', # REGISTER_D7
'a0', # REGISTER_A0
'a1', # REGISTER_A1
'a2', # REGISTER_A2
'a3', # REGISTER_A3
'a4', # REGISTER_A4
'a5', # REGISTER_A5
'a6', # REGISTER_A6
'sp' # REGISTER_A7
]
# Sizes
SIZE_BYTE = 0
SIZE_WORD = 1
SIZE_LONG = 2
SizeSuffix = [
'.b', # SIZE_BYTE
'.w', # SIZE_WORD
'.l', # SIZE_LONG
]
# Operands
class OpRegisterDirect:
def __init__(self, size, reg):
self.size = size
self.reg = reg
def __repr__(self):
return "OpRegisterDirect(%d, %s)" % (self.size, self.reg)
def format(self, addr):
# a0, d0
return [
InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg)
]
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
return None
def get_source_il(self, il):
if self.reg == 'ccr':
c = il.flag_bit(1, 'c', 0)
v = il.flag_bit(1, 'v', 1)
z = il.flag_bit(1, 'z', 2)
n = il.flag_bit(1, 'n', 3)
x = il.flag_bit(1, 'x', 4)
return il.or_expr(1, il.or_expr(1, il.or_expr(1, il.or_expr(1, c, v), z), n), x)
else:
return il.reg(1 << self.size, self.reg)
def get_dest_il(self, il, value, flags=0):
if self.reg == 'ccr':
return None
else:
# return il.set_reg(1 << self.size, self.reg, value)
# if self.size == SIZE_BYTE:
# if self.reg[0] == 'a' or self.reg == 'sp':
# return None
# else:
# return il.set_reg(1, self.reg+'.b', value, flags)
# elif self.size == SIZE_WORD:
# return il.set_reg(2, self.reg+'.w', value, flags)
# else:
# return il.set_reg(4, self.reg, value, flags)
if self.size == SIZE_BYTE:
if self.reg[0] == 'a' or self.reg == 'sp':
return None
else:
return il.set_reg(4, self.reg, il.or_expr(4, il.and_expr(4, il.const(4, 0xffffff00), il.reg(4, self.reg)), il.and_expr(4, il.const(4, 0xff), value)), flags)
elif self.size == SIZE_WORD:
if self.reg[0] == 'a' or self.reg == 'sp':
return il.set_reg(4, self.reg, il.sign_extend(4, value), flags)
else:
return il.set_reg(4, self.reg, il.or_expr(4, il.and_expr(4, il.const(4, 0xffff0000), il.reg(4, self.reg)), il.and_expr(4, il.const(4, 0xffff), value)), flags)
else:
return il.set_reg(4, self.reg, value, flags)
class OpRegisterDirectPair:
def __init__(self, size, reg1, reg2):
self.size = size
self.reg1 = reg1
self.reg2 = reg2
def __repr__(self):
return "OpRegisterDirectPair(%d, %s, %s)" % (self.size, self.reg1, self.reg2)
def format(self, addr):
# d0:d1
return [
InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg1),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ":"),
InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg2)
]
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
return None
def get_source_il(self, il):
return (il.reg(1 << self.size, self.reg1), il.reg(1 << self.size, self.reg2))
def get_dest_il(self, il, values, flags=0):
return (il.set_reg(1 << self.size, self.reg1, values[0], flags), il.set_reg(1 << self.size, self.reg2, values[1], flags))
class OpRegisterMovemList:
def __init__(self, size, regs):
self.size = size
self.regs = regs
def __repr__(self):
return "OpRegisterMovemList(%d, %s)" % (self.size, repr(self.regs))
def format(self, addr):
# d0-d7/a0/a2/a4-a7
if len(self.regs) == 0:
return []
tokens = [InstructionTextToken(InstructionTextTokenType.RegisterToken, self.regs[0])]
last = self.regs[0]
first = None
for reg in self.regs[1:]:
if Registers[Registers.index(last)+1] == reg and reg != 'a0':
if first is None:
first = last
last = reg
else:
if first is not None:
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, "-"))
tokens.append(InstructionTextToken(InstructionTextTokenType.RegisterToken, last))
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, "/"))
tokens.append(InstructionTextToken(InstructionTextTokenType.RegisterToken, reg))
first = None
last = reg
if first is not None:
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, "-"))
tokens.append(InstructionTextToken(InstructionTextTokenType.RegisterToken, last))
return tokens
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
return None
def get_source_il(self, il):
return [il.reg(1 << self.size, reg) for reg in self.regs]
def get_dest_il(self, il, values, flags=0):
return [il.set_reg(1 << self.size, reg, val, flags) for reg, val in zip(self.regs, values)]
class OpRegisterIndirect:
def __init__(self, size, reg):
self.size = size
self.reg = reg
def __repr__(self):
return "OpRegisterIndirect(%d, %s)" % (self.size, self.reg)
def format(self, addr):
# (a0)
return [
InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("),
InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg),
InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")")
]
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
return il.reg(4, self.reg)
def get_source_il(self, il):
return il.load(1 << self.size, self.get_address_il(il))
def get_dest_il(self, il, value, flags=0):
#return il.store(1 << self.size, self.get_address_il(il), value, flags)
return il.expr(LowLevelILOperation.LLIL_STORE, self.get_address_il(il).index, value.index, size=1 << self.size, flags=flags)
class OpRegisterIndirectPair:
def __init__(self, size, reg1, reg2):
self.size = size
self.reg1 = reg1
self.reg2 = reg2
def __repr__(self):
return "OpRegisterIndirectPair(%d, %s, %s)" % (self.size, self.reg1, self.reg2)
def format(self, addr):
# d0:d1
return [
InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("),
InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg1),
InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")"),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ":"),
InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("),
InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg2),
InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")")
]
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
return (il.reg(4, self.reg1), il.reg(4, self.reg2))
def get_source_il(self, il):
return (il.load(1 << self.size, il.reg(4, self.reg1)), il.load(1 << self.size, il.reg(4, self.reg2)))
def get_dest_il(self, il, values, flags=0):
#return (il.store(1 << self.size, il.reg(4, self.reg1), values[0], flags), il.store(1 << self.size, il.reg(4, self.reg2), values[1], flags))
return (il.store(1 << self.size, il.reg(4, self.reg1), values[0]), il.store(1 << self.size, il.reg(4, self.reg2), values[1]))
class OpRegisterIndirectPostincrement:
def __init__(self, size, reg):
self.size = size
self.reg = reg
def __repr__(self):
return "OpRegisterIndirectPostincrement(%d, %s)" % (self.size, self.reg)
def format(self, addr):
# (a0)+
return [
InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("),
InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg),
InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")"),
InstructionTextToken(InstructionTextTokenType.TextToken, "+")
]
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return il.set_reg(4,
self.reg,
il.add(4,
il.reg(4, self.reg),
il.const(4, 1 << self.size)
)
)
def get_address_il(self, il):
return il.reg(4, self.reg)
def get_source_il(self, il):
return il.load(1 << self.size, self.get_address_il(il))
def get_dest_il(self, il, value, flags=0):
#return il.store(1 << self.size, self.get_address_il(il), value, flags)
return il.expr(LowLevelILOperation.LLIL_STORE, self.get_address_il(il).index, value.index, size=1 << self.size, flags=flags)
class OpRegisterIndirectPredecrement:
def __init__(self, size, reg):
self.size = size
self.reg = reg
def __repr__(self):
return "OpRegisterIndirectPredecrement(%d, %s)" % (self.size, self.reg)
def format(self, addr):
# -(a0)
return [
InstructionTextToken(InstructionTextTokenType.TextToken, "-"),
InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("),
InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg),
InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")")
]
def get_pre_il(self, il):
return il.set_reg(4,
self.reg,
il.sub(4,
il.reg(4, self.reg),
il.const(4, 1 << self.size)
)
)
def get_post_il(self, il):
return None
def get_address_il(self, il):
return il.reg(4, self.reg)
def get_source_il(self, il):
return il.load(1 << self.size, self.get_address_il(il))
def get_dest_il(self, il, value, flags=0):
#return il.store(1 << self.size, self.get_address_il(il), value, flags)
return il.expr(LowLevelILOperation.LLIL_STORE, self.get_address_il(il).index, value.index, size=1 << self.size, flags=flags)
class OpRegisterIndirectDisplacement:
def __init__(self, size, reg, offset):
self.size = size
self.reg = reg
self.offset = offset
def __repr__(self):
return "OpRegisterIndirectDisplacement(%d, %s, 0x%x)" % (self.size, self.reg, self.offset)
def format(self, addr):
if self.reg == 'pc':
return [
InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("),
InstructionTextToken(InstructionTextTokenType.PossibleAddressToken, "${:08x}".format(addr+2+self.offset), addr+2+self.offset, 4),
InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")")
]
else:
# $1234(a0)
return [
InstructionTextToken(InstructionTextTokenType.IntegerToken, "${:04x}".format(self.offset), self.offset, 2),
InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("),
InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg),
InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")")
]
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
if self.reg == 'pc':
return il.const(4, il.current_address+2+self.offset)
else:
return il.add(4,
il.reg(4, self.reg),
il.const(2, self.offset)
)
def get_source_il(self, il):
return il.load(1 << self.size, self.get_address_il(il))
def get_dest_il(self, il, value, flags=0):
if self.reg == 'pc':
return None
else:
#return il.store(1 << self.size, self.get_address_il(il), value, flags)
return il.expr(LowLevelILOperation.LLIL_STORE, self.get_address_il(il).index, value.index, size=1 << self.size, flags=flags)
class OpRegisterIndirectIndex:
def __init__(self, size, reg, offset, ireg, ireg_long, scale):
self.size = size
self.reg = reg
self.offset = offset
self.ireg = ireg
self.ireg_long = ireg_long
self.scale = scale
def __repr__(self):
return "OpRegisterIndirectIndex(%d, %s, 0x%x, %s, %d, %d)" % (self.size, self.reg, self.offset, self.ireg, self.ireg_long, self.scale)
def format(self, addr):
# $1234(a0,a1.l*4)
tokens = []
if self.offset != 0:
tokens.append(InstructionTextToken(InstructionTextTokenType.IntegerToken, "${:x}".format(self.offset), self.offset))
tokens.append(InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("))
tokens.append(InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg))
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ","))
tokens.append(InstructionTextToken(InstructionTextTokenType.RegisterToken, self.ireg))
tokens.append(InstructionTextToken(InstructionTextTokenType.TextToken, "."))
tokens.append(InstructionTextToken(InstructionTextTokenType.TextToken, "l" if self.ireg_long else 'w'))
if self.scale != 1:
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, "*"))
tokens.append(InstructionTextToken(InstructionTextTokenType.IntegerToken, "{}".format(self.scale), self.scale))
tokens.append(InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")"))
return tokens
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
return il.add(4,
il.add(4,
il.const(4, il.current_address+2) if self.reg == 'pc' else il.reg(4, self.reg),
il.const(4, self.offset)
),
il.mult(4,
il.reg(4 if self.ireg_long else 2, self.ireg),
il.const(1, self.scale)
)
)
def get_source_il(self, il):
return il.load(1 << self.size, self.get_address_il(il))
def get_dest_il(self, il, value, flags=0):
if self.reg == 'pc':
return None
else:
#return il.store(1 << self.size, self.get_address_il(il), value, flags)
return il.expr(LowLevelILOperation.LLIL_STORE, self.get_address_il(il).index, value.index, size=1 << self.size, flags=flags)
class OpMemoryIndirect:
def __init__(self, size, reg, offset, outer_displacement):
self.size = size
self.reg = reg
self.offset = offset
self.outer_displacement = outer_displacement
def __repr__(self):
return "OpRegisterIndirectIndex(%d, %s, %d, %d)" % (self.size, self.reg, self.offset, self.outer_displacement)
def format(self, addr):
# ([$1234,a0],$1234)
tokens = []
tokens.append(InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("))
tokens.append(InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "["))
if self.offset != 0:
tokens.append(InstructionTextToken(InstructionTextTokenType.IntegerToken, "${:x}".format(self.offset), self.offset))
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ","))
tokens.append(InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg))
tokens.append(InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, "]"))
if self.outer_displacement != 0:
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ","))
tokens.append(InstructionTextToken(InstructionTextTokenType.IntegerToken, "${:x}".format(self.outer_displacement), self.outer_displacement))
tokens.append(InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")"))
return tokens
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
return il.add(4,
il.load(4,
il.add(4,
il.const(4, il.current_address+2) if self.reg == 'pc' else il.reg(4, self.reg),
il.const(4, self.offset)
),
),
il.const(4, self.outer_displacement)
)
def get_source_il(self, il):
return il.load(1 << self.size, self.get_address_il(il))
def get_dest_il(self, il, value, flags=0):
if self.reg == 'pc':
return None
else:
#return il.store(1 << self.size, self.get_address_il(il), value, flags)
return il.expr(LowLevelILOperation.LLIL_STORE, self.get_address_il(il).index, value.index, size=1 << self.size, flags=flags)
class OpMemoryIndirectPostindex:
def __init__(self, size, reg, offset, ireg, ireg_long, scale, outer_displacement):
self.size = size
self.reg = reg
self.offset = offset
self.ireg = ireg
self.ireg_long = ireg_long
self.scale = scale
self.outer_displacement = outer_displacement
def __repr__(self):
return "OpRegisterIndirectIndex(%d, %s, 0x%x, %s, %d, %d, 0x%x)" % (self.size, self.reg, self.offset, self.ireg, self.ireg_long, self.scale, self.outer_displacement)
def format(self, addr):
# ([$1234,a0],a1.l*4,$1234)
tokens = []
tokens.append(InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("))
tokens.append(InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "["))
if self.offset != 0:
tokens.append(InstructionTextToken(InstructionTextTokenType.IntegerToken, "${:x}".format(self.offset), self.offset))
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ","))
tokens.append(InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg))
tokens.append(InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, "]"))
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ","))
tokens.append(InstructionTextToken(InstructionTextTokenType.RegisterToken, self.ireg))
tokens.append(InstructionTextToken(InstructionTextTokenType.TextToken, "."))
tokens.append(InstructionTextToken(InstructionTextTokenType.TextToken, "l" if self.ireg_long else 'w'))
if self.scale != 1:
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, "*"))
tokens.append(InstructionTextToken(InstructionTextTokenType.IntegerToken, "{}".format(self.scale), self.scale))
if self.outer_displacement != 0:
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ","))
tokens.append(InstructionTextToken(InstructionTextTokenType.IntegerToken, "${:x}".format(self.outer_displacement), self.outer_displacement))
tokens.append(InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")"))
return tokens
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
return il.add(4,
il.load(4,
il.add(4,
il.const(4, il.current_address+2) if self.reg == 'pc' else il.reg(4, self.reg),
il.const(4, self.offset)
)
),
il.add(4,
il.mult(4,
il.reg(4 if self.ireg_long else 2, self.ireg),
il.const(1, self.scale)
),
il.const(4, self.outer_displacement)
)
)
def get_source_il(self, il):
return il.load(1 << self.size, self.get_address_il(il))
def get_dest_il(self, il, value, flags=0):
if self.reg == 'pc':
return None
else:
#return il.store(1 << self.size, self.get_address_il(il), value, flags)
return il.expr(LowLevelILOperation.LLIL_STORE, self.get_address_il(il).index, value.index, size=1 << self.size, flags=flags)
class OpMemoryIndirectPreindex:
def __init__(self, size, reg, offset, ireg, ireg_long, scale, outer_displacement):
self.size = size
self.reg = reg
self.offset = offset
self.ireg = ireg
self.ireg_long = ireg_long
self.scale = scale
self.outer_displacement = outer_displacement
def __repr__(self):
return "OpRegisterIndirectIndex(%d, %s, 0x%x, %s, %d, %d, 0x%x)" % (self.size, self.reg, self.offset, self.ireg, self.ireg_long, self.scale, self.outer_displacement)
def format(self, addr):
# ([$1234,a0,a1.l*4],$1234)
tokens = []
tokens.append(InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("))
tokens.append(InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "["))
if self.offset != 0:
tokens.append(InstructionTextToken(InstructionTextTokenType.IntegerToken, "${:x}".format(self.offset), self.offset))
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ","))
tokens.append(InstructionTextToken(InstructionTextTokenType.RegisterToken, self.reg))
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ","))
tokens.append(InstructionTextToken(InstructionTextTokenType.RegisterToken, self.ireg))
tokens.append(InstructionTextToken(InstructionTextTokenType.TextToken, "."))
tokens.append(InstructionTextToken(InstructionTextTokenType.TextToken, "l" if self.ireg_long else 'w'))
if self.scale != 1:
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, "*"))
tokens.append(InstructionTextToken(InstructionTextTokenType.IntegerToken, "{}".format(self.scale), self.scale))
tokens.append(InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, "]"))
if self.outer_displacement != 0:
tokens.append(InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ","))
tokens.append(InstructionTextToken(InstructionTextTokenType.IntegerToken, "${:x}".format(self.outer_displacement), self.outer_displacement))
tokens.append(InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")"))
return tokens
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
return il.add(4,
il.load(4,
il.add(4,
il.add(4,
il.const(4, il.current_address+2) if self.reg == 'pc' else il.reg(4, self.reg),
il.const(4, self.offset)
),
il.mult(4,
il.reg(4 if self.ireg_long else 2, self.ireg),
il.const(1, self.scale)
)
)
),
il.const(4, self.outer_displacement)
)
def get_source_il(self, il):
return il.load(1 << self.size, self.get_address_il(il))
def get_dest_il(self, il, value, flags=0):
if self.reg == 'pc':
return None
else:
#return il.store(1 << self.size, self.get_address_il(il), value, flags)
return il.expr(LowLevelILOperation.LLIL_STORE, self.get_address_il(il).index, value.index, size=1 << self.size, flags=flags)
class OpAbsolute:
def __init__(self, size, address, address_size):
self.size = size
self.address = address
self.address_size = address_size
def __repr__(self):
return "OpAbsolute(%d, 0x%x, %d)" % (self.size, self.address, self.address_size)
def format(self, addr):
# ($1234).w
return [
InstructionTextToken(InstructionTextTokenType.BeginMemoryOperandToken, "("),
InstructionTextToken(InstructionTextTokenType.PossibleAddressToken, "${:0{}x}".format(self.address, 1 << self.address_size), self.address, 1 << self.address_size),
InstructionTextToken(InstructionTextTokenType.EndMemoryOperandToken, ")"+SizeSuffix[self.address_size])
]
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
return il.sign_extend(4,
il.const(1 << self.address_size, self.address)
)
def get_source_il(self, il):
return il.load(1 << self.size, self.get_address_il(il))
def get_dest_il(self, il, value, flags=0):
#return il.store(1 << self.size, self.get_address_il(il), value, flags)
return il.expr(LowLevelILOperation.LLIL_STORE, self.get_address_il(il).index, value.index, size=1 << self.size, flags=flags)
class OpImmediate:
def __init__(self, size, value):
self.size = size
self.value = value
def __repr__(self):
return "OpImmediate(%d, 0x%x)" % (self.size, self.value)
def format(self, addr):
# #$1234
return [
InstructionTextToken(InstructionTextTokenType.TextToken, "#"),
#InstructionTextToken(InstructionTextTokenType.PossibleAddressToken, "${:0{}x}".format(self.value, 1 << self.size), self.value, 1 << self.size)
InstructionTextToken(InstructionTextTokenType.IntegerToken, "${:0{}x}".format(self.value, 1 << self.size), self.value, 1 << self.size)
]
def get_pre_il(self, il):
return None
def get_post_il(self, il):
return None
def get_address_il(self, il):
return None
def get_source_il(self, il):
return il.const(1 << self.size, self.value)
def get_dest_il(self, il, value, flags=0):
return None
# condition mapping to LLIL flag conditions
ConditionMapping = {
# 'hi': LowLevelILFlagCondition.
# 'ls': LowLevelILFlagCondition.
# 'cc': LowLevelILFlagCondition.
# 'cs': LowLevelILFlagCondition.
'ne': LowLevelILFlagCondition.LLFC_NE,
'eq': LowLevelILFlagCondition.LLFC_E,
'vc': LowLevelILFlagCondition.LLFC_NO,
'vs': LowLevelILFlagCondition.LLFC_O,
'pl': LowLevelILFlagCondition.LLFC_POS,
'mi': LowLevelILFlagCondition.LLFC_NEG,
'ge': LowLevelILFlagCondition.LLFC_UGE,
'lt': LowLevelILFlagCondition.LLFC_ULT,
'gt': LowLevelILFlagCondition.LLFC_UGT,
'le': LowLevelILFlagCondition.LLFC_ULE,
}
class M68000(Architecture):
name = "M68000"
address_size = 4
default_int_size = 4
max_instr_length = 22
endianness = Endianness.BigEndian
regs = {
'd0': RegisterInfo('d0', 4),
'd1': RegisterInfo('d1', 4),
'd2': RegisterInfo('d2', 4),
'd3': RegisterInfo('d3', 4),
'd4': RegisterInfo('d4', 4),
'd5': RegisterInfo('d5', 4),
'd6': RegisterInfo('d6', 4),
'd7': RegisterInfo('d7', 4),
'a0': RegisterInfo('a0', 4, extend=ImplicitRegisterExtend.SignExtendToFullWidth),
'a1': RegisterInfo('a1', 4, extend=ImplicitRegisterExtend.SignExtendToFullWidth),
'a2': RegisterInfo('a2', 4, extend=ImplicitRegisterExtend.SignExtendToFullWidth),
'a3': RegisterInfo('a3', 4, extend=ImplicitRegisterExtend.SignExtendToFullWidth),
'a4': RegisterInfo('a4', 4, extend=ImplicitRegisterExtend.SignExtendToFullWidth),
'a5': RegisterInfo('a5', 4, extend=ImplicitRegisterExtend.SignExtendToFullWidth),
'a6': RegisterInfo('a6', 4, extend=ImplicitRegisterExtend.SignExtendToFullWidth),
'sp': RegisterInfo('sp', 4, extend=ImplicitRegisterExtend.SignExtendToFullWidth),
'sr': RegisterInfo('sr', 2),
'ccr': RegisterInfo('sr', 1),
# control registers
# MC68010/MC68020/MC68030/MC68040/CPU32
'sfc': RegisterInfo('sfc', 4),
'dfc': RegisterInfo('dfc', 4),
'usp': RegisterInfo('usp', 4),
'vbr': RegisterInfo('vbr', 4),
# MC68020/MC68030/MC68040
'cacr': RegisterInfo('cacr', 4),
'caar': RegisterInfo('caar', 4),
'msp': RegisterInfo('msp', 4),
'isp': RegisterInfo('isp', 4),
# MC68040/MC68LC040
'tc': RegisterInfo('tc', 4),
'itt0': RegisterInfo('itt0', 4),
'itt1': RegisterInfo('itt1', 4),
'dtt0': RegisterInfo('dtt0', 4),
'dtt1': RegisterInfo('dtt1', 4),
'mmusr': RegisterInfo('mmusr', 4),
'urp': RegisterInfo('urp', 4),
'srp': RegisterInfo('srp', 4),
# MC68EC040
'iacr0': RegisterInfo('iacr0', 4),
'iacr1': RegisterInfo('iacr1', 4),
'dacr0': RegisterInfo('dacr0', 4),
'dacr1': RegisterInfo('dacr1', 4),
}
stack_pointer = 'sp'
flags = ['x', 'n', 'z', 'v', 'c']
flag_write_types = ['', '*', 'nzvc']
flags_written_by_flag_write_types = {
'*': ['x', 'n', 'z', 'v', 'c'],
'nzvc': ['n', 'z', 'v', 'c'],
}
flag_roles = {
'x': FlagRole.SpecialFlagRole,
'n': FlagRole.NegativeSignFlagRole,
'z': FlagRole.ZeroFlagRole,
'v': FlagRole.OverflowFlagRole,
'c': FlagRole.CarryFlagRole,
}
flags_required_for_flag_condition = {
# LowLevelILFlagCondition. ['c', 'z'], # hi
# LowLevelILFlagCondition. ['c', 'z'], # ls
# LowLevelILFlagCondition. ['c'], # cc
# LowLevelILFlagCondition. ['c'], # cs
LowLevelILFlagCondition.LLFC_NE: ['z'], # ne
LowLevelILFlagCondition.LLFC_E: ['z'], # eq
LowLevelILFlagCondition.LLFC_NO: ['v'], # vc
LowLevelILFlagCondition.LLFC_O: ['v'], # vs
LowLevelILFlagCondition.LLFC_POS: ['n'], # pl
LowLevelILFlagCondition.LLFC_NEG: ['n'], # mi
LowLevelILFlagCondition.LLFC_UGE: ['n', 'v'], # ge
LowLevelILFlagCondition.LLFC_ULT: ['n', 'v'], # lt
LowLevelILFlagCondition.LLFC_UGT: ['n', 'v', 'z'], # gt
LowLevelILFlagCondition.LLFC_ULE: ['n', 'v', 'z'], # le
}
control_registers = {
}
memory_indirect = False
movem_store_decremented = False
def decode_effective_address(self, mode, register, data, size=None):
mode &= 0x07
register &= 0x07
reg = None
if mode == 0:
# data register direct
return (OpRegisterDirect(size, Registers[register]), 0)
elif mode == 1:
# address register direct
return (OpRegisterDirect(size, Registers[register+8]), 0)
elif mode == 2:
# address register indirect
return (OpRegisterIndirect(size, Registers[register+8]), 0)
elif mode == 3:
# address register indirect with postincrement
return (OpRegisterIndirectPostincrement(size, Registers[register+8]), 0)
elif mode == 4:
# address register indirect with predecrement
return (OpRegisterIndirectPredecrement(size, Registers[register+8]), 0)
elif mode == 5:
# address register indirect with displacement
return (OpRegisterIndirectDisplacement(size, Registers[register+8], struct.unpack_from('>h', data, 0)[0]), 2)
elif mode == 6:
# extended addressing mode
reg = Registers[register+8]
elif mode == 7:
if register == 0:
# absolute short
val = struct.unpack_from('>H', data, 0)[0]
if val & 0x8000:
val |= 0xffff0000
return (OpAbsolute(size, val, 1), 2)
if register == 1:
# absolute long
return (OpAbsolute(size, struct.unpack_from('>L', data, 0)[0], 2), 4)
elif register == 2:
# program counter indirect with displacement
return (OpRegisterIndirectDisplacement(size, 'pc', struct.unpack_from('>h', data, 0)[0]), 2)
elif register == 3:
# extended addressing mode
reg = 'pc'
elif register == 4:
# immediate
if size == None:
# unspecified length
return (OpImmediate(size, None), None)
elif size == SIZE_BYTE:
# byte
return (OpImmediate(size, struct.unpack_from('>b', data, 1)[0]), 2)
elif size == 1:
# word
return (OpImmediate(size, struct.unpack_from('>h', data, 0)[0]), 2)
elif size == 2:
# long
return (OpImmediate(size, struct.unpack_from('>l', data, 0)[0]), 4)
if reg is not None:
extra = struct.unpack_from('>H', data, 0)[0]
# index register
xn = Registers[extra >> 12]
# index register size
index_size = (extra >> 11) & 1