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c++0x_warning.h #51
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Hi Sarah, when you run synthesis, both the I'm glad the tutorial was useful to you! If you are comfortable working with a CMake-based workflow, I recommend using the |
Thank you very much, I've added the -DHLSLIB_SYNTHESIS flag as well as std=c++11 and that solved this issue. I'm getting now another error which after some research it seems that the HLS bind_storage pragma is not supported in 2019.2? Is my understanding correct or am I missing something? I'm new to Vivado HLS. The error message is shown below. If I'm going to move to a newer version, which version do you recommend that would fully support hlslib? Thanks again for your help, much appreciated. Starting C synthesis ... |
I tried compiling the examples with 2019.2, but I cannot reproduce this error. Did you modify the code in any way? Are you using the newest version of the examples repository? I'm currently using Vitis 2021.1, but I would just recommend using the newest version available (currently 2021.2). |
No I didn't modify anything, and I got the code from https://github.com/spcl/hls_tutorial_examples just a few days ago so I think I have the latest version. I have tried synthesizing Example2 instead and still got the same errors. All I have done is place the hlslib files and Example2.cpp, Entry.cpp,Test.cpp (Example2 and Entry as source, Test as test bench) files in the project folder and defined the top function to be Example2. Starting C synthesis ... |
I'm not sure why it compiles this part when you don't specify the resource, but the error is because the |
Hi, Sorry for the late reply, I have moved to Vitis HLS 2021.1 and thankfully this error doesn't show anymore when I run C synthesis. Now, when I run the C simulation for example 2 it works fine as well, but for example 6 it generates the below message when running the code for only Example6 function call and commenting the Example6_Vectorized function call and relevant comparison loop. However, when calling Example6_vectorized instead, and also in case of example 7, it seems like the simulation gets stuck until I forcibly end the simulation. Is there a cflag I'm supposed to set for C simulation as well? The following flags are set be default " -cflags -Wno-unknown-pragmas -csimflags -Wno-unknown-pragmas ". Thanks a lot for your help. Example6: In file included from C:/Xilinx/Vitis_HLS/2021.1/include/hls_fpo.h:189:0, Test ran successfully. |
To give a complete picture, the output of C synthesis of Example 7 which runs successfully, however, there are many warnings like the shown below among other warnings: "WARNING: [HLS 200-805] An internal stream 'a_pipes.stream_.V.0' with default size can result in deadlock. Please consider resizing the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma." |
As a fair warning, Vitis' own C-simulation does not always work particularly well, I favor compiling my programs with a regular C++ compiler when running simulation. This is all set up in the makefiles of the tutorial repository, but I realize that you are using the Xilinx GUI instead, which might not easily allow this. Could it be that it's simply taking a very long time? These examples are more meant for showing the output of synthesis, rather than running them on large input sizes (which will be fast in hardware, but not in simulation). Could you try setting the domain size to something relatively small (for example 64x64x64) in Example6.h or Example7.h? |
Thank you, changing the domain size didn't occur to me, I changed it to a smaller size and the C simulation ran successfully! (although the mentioned warning is still showing but I guess that's not a big issue). Thanks a lot for your help. |
The warning is only relevant in hardware, and indeed it might benefit from making the FIFOs a bit deeper, but it should be safe for you to ignore :-) |
Hi,
I have watched the "Productive Parallel Programming for FPGA with High Level Synthesis" on youtube and I found it be very useful, thank you for posting it! I'm trying to run the examples on my machine but I have encountered the warning and error shown below when synthesizing any example that includes the use of hlslib (this is from Example 4). I'm using vivado hls 2019.2 on Windows. I have tried setting the CFLAG to -std=c++0x or -std=c++11, when doing so too many errors arise as shown in the second picture below. When I open the c++0x_warning.h file the warning is mentioning c++11. I've spent quite some time trying to solve this issue to no avail.
The C simulation runs successfully though.
Thank you for your help.
Best Regards,
Sarah
"
Starting C synthesis ...
C:/Xilinx/Vivado/2019.2/bin/vivado_hls.bat C:/Users/Sara/AppData/Roaming/Xilinx/Vivado/Example4/Example4/csynth.tcl
INFO: [HLS 200-10] Running 'C:/Xilinx/Vivado/2019.2/bin/unwrapped/win64.o/vivado_hls.exe'
INFO: [HLS 200-10] For user 'Sara' on host 'lenovo-sara' (Windows NT_amd64 version 6.2) on Fri Nov 05 14:09:18 +1100 2021
INFO: [HLS 200-10] In directory 'C:/Users/Sara/AppData/Roaming/Xilinx/Vivado'
Sourcing Tcl script 'C:/Users/Sara/AppData/Roaming/Xilinx/Vivado/Example4/Example4/csynth.tcl'
INFO: [HLS 200-10] Opening project 'C:/Users/Sara/AppData/Roaming/Xilinx/Vivado/Example4'.
INFO: [HLS 200-10] Adding design file 'Example4/Example4/Example4.cpp' to the project
INFO: [HLS 200-10] Adding test bench file 'Example4/Example4/Test.cpp' to the project
INFO: [HLS 200-10] Opening solution 'C:/Users/Sara/AppData/Roaming/Xilinx/Vivado/Example4/Example4'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
WARNING: [HLS 200-40] Cannot find library 'C:/Xilinx/Vivado/2019.2/common/technology/xilinx/Virtex-7/Virtex-7.lib'.
WARNING: [HLS 200-40] Cannot find library 'xilinx/Virtex-7/Virtex-7'.
INFO: [HLS 200-10] Setting target device to 'xc7vx485t-ffg1157-1'
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [HLS 200-10] Analyzing design file 'Example4/Example4/Example4.cpp' ...
WARNING: [HLS 200-40] In file included from Example4/Example4/Example4.cpp:1:
In file included from Example4/Example4/Example4.h:3:
In file included from Example4/Example4/hlslib/xilinx/Stream.h:11:
In file included from C:/Xilinx/Vivado/2019.2/win64/tools/clang/bin..\lib\clang\3.1/../../../include/c++/4.5.2\condition_variable:34:
C:/Xilinx/Vivado/2019.2/win64/tools/clang/bin..\lib\clang\3.1/../../../include/c++/4.5.2\bits/c++0x_warning.h:31:2: error: This file requires compiler and library support for the upcoming ISO C++ standard, C++0x. This support is currently experimental, and must be enabled with the -std=c++0x or -std=gnu++0x compiler options.
#error This file requires compiler and library support for the upcoming
^
1 error generated.
C preprocessor failed.
while executing
"source C:/Users/Sara/AppData/Roaming/Xilinx/Vivado/Example4/Example4/csynth.tcl"
invoked from within
"hls::main C:/Users/Sara/AppData/Roaming/Xilinx/Vivado/Example4/Example4/csynth.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"
Finished C synthesis.
"
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