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vivado.jou
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#-----------------------------------------------------------
# Vivado v2015.2 (64-bit)
# SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
# Start of session at: Thu Dec 17 15:09:48 2015
# Process ID: 8939
# Log file: /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/vivado.log
# Journal file: /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.xpr
launch_sdk -workspace /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk -hwspec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/design_1_wrapper.hdf
mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre
ls
ls
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy
set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
write_bitstream -force /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
reset_run impl_1 -prev_step
launch_runs impl_1 -to_step write_bitstream -jobs 8
wait_on_run impl_1
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre
"/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre"
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy ' -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre'
write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit "up 0x00000000 design_1_test.bit up 0x00A00000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre" AC701.mcs
write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit "up 0x00000000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit up 0x00A00000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre" AC701.mcs
write_bitstream -force /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
open_run impl_1
set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
write_bitstream -force /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit "up 0x00000000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit up 0x00A00000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre" AC701.mcs
write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit "up 0x00000000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit" -loaddata "up 0x00A00000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre" AC701.mcs
pwd
open_hw
connect_hw_server -url localhost:3121
current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
set_property PARAM.FREQUENCY 30000000 [get_hw_targets */xilinx_tcf/Digilent/*]
open_hw_target
current_hw_device [lindex [get_hw_devices] 0]
refresh_hw_device [lindex [get_hw_devices] 0]
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {n25q256-3.3v-spi-x1_x2_x4}] 0]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
refresh_hw_device [lindex [get_hw_devices] 0]
set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.FILE {AC701.mcs} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]]
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]]]] } { create_hw_bitstream -hw_device [lindex [get_hw_devices] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices] 0]]; program_hw_devices [lindex [get_hw_devices] 0]; };
program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
disconnect_hw_server localhost:3121
close_hw
close_project
open_project /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.xpr
reset_run synth_1
launch_runs synth_1 -jobs 8
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 8
wait_on_run synth_1
launch_runs impl_1 -jobs 8
wait_on_run impl_1
ipx::open_ipxact_file /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/component.xml
set_property core_revision 32 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
update_ip_catalog -rebuild -repo_path /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs
ipx::check_integrity -quiet [ipx::current_core]
ipx::archive_core /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/user.org_user_trigger_logic_AXI_1.1.zip [ipx::current_core]
close_project
open_project /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.xpr
open_bd_design {/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd}
report_ip_status -name ip_status
upgrade_ip -vlnv user.org:user:trigger_logic_AXI:1.1 [get_ips design_1_trigger_logic_AXI_0_0]
report_ip_status -name ip_status
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
wait_on_run impl_1
open_hw
open_run impl_1
set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
write_bitstream -force /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit "up 0x00000000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit" -loaddata "up 0x00A00000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre" AC701.mcs
open_hw
connect_hw_server -url localhost:3121
current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
set_property PARAM.FREQUENCY 30000000 [get_hw_targets */xilinx_tcf/Digilent/*]
open_hw_target
current_hw_device [lindex [get_hw_devices] 0]
refresh_hw_device [lindex [get_hw_devices] 0]
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {n25q256-3.3v-spi-x1_x2_x4}] 0]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
refresh_hw_device [lindex [get_hw_devices] 0]
set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.FILE {AC701.mcs} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]]
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]]]] } { create_hw_bitstream -hw_device [lindex [get_hw_devices] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices] 0]]; program_hw_devices [lindex [get_hw_devices] 0]; };
program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
disconnect_hw_server localhost:3121
close_hw
open_bd_design {/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd}
close_project
create_project phase_shift_40MHz_clk_gen_axi /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi -part xc7a200tfbg676-2
set_property board_part xilinx.com:ac701:part0:1.2 [current_project]
set_property target_language VHDL [current_project]
add_files -norecurse /n/15/moore.1424/xilinx/axi_template.vhd
import_files -force -norecurse
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
file mkdir /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.srcs/sources_1/new
close [ open /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.srcs/sources_1/new/clk_gen.vhd w ]
add_files /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.srcs/sources_1/new/clk_gen.vhd
update_compile_order -fileset sources_1
file mkdir /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.srcs/sim_1/new
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.srcs/sim_1/new/clk_gen_tb.vhd w ]
add_files -fileset sim_1 /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.srcs/sim_1/new/clk_gen_tb.vhd
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
launch_simulation
source clk_gen_tb.tcl
restart
run 100 ns
update_compile_order -fileset sources_1
close_sim
launch_simulation
launch_simulation
launch_simulation
launch_simulation
launch_simulation
source clk_gen_tb.tcl
add_wave {{/clk_gen_tb/cg0/clk_0_r_int}} {{/clk_gen_tb/cg0/clk_0_f_int}} {{/clk_gen_tb/cg0/last_clk_0_f_int}}
restart
run 100 ns
save_wave_config {/n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/clk_gen_tb_behav.wcfg}
close_sim
launch_simulation
source clk_gen_tb.tcl
add_wave {{/clk_gen_tb/cg0/clk_0_r_int}} {{/clk_gen_tb/cg0/clk_0_f_int}} {{/clk_gen_tb/cg0/last_clk_0_f_int}}
restart
run 100 ns
save_wave_config {/n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/clk_gen_tb_behav.wcfg}
launch_simulation
source clk_gen_tb.tcl
add_wave {{/clk_gen_tb/cg0/clk_0_r_int}} {{/clk_gen_tb/cg0/clk_0_f_int}} {{/clk_gen_tb/cg0/last_clk_0_f_int}}
restart
run 100 ns
close_sim
launch_simulation
source clk_gen_tb.tcl
restart
run 100 ns
close_sim
launch_simulation
source clk_gen_tb.tcl
add_wave {{/clk_gen_tb/cg0/clk_0_r_int}} {{/clk_gen_tb/cg0/clk_0_f_int}} {{/clk_gen_tb/cg0/last_clk_0_f_int}}
restart
run 100 ns
save_wave_config {/n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/clk_gen_tb_behav.wcfg}
add_files -fileset sim_1 -norecurse /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/clk_gen_tb_behav.wcfg
set_property xsim.view /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/clk_gen_tb_behav.wcfg [get_filesets sim_1]
launch_simulation
open_wave_config /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/clk_gen_tb_behav.wcfg
source clk_gen_tb.tcl
restart
launch_simulation
launch_simulation
launch_simulation
launch_simulation
launch_simulation
open_wave_config /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/clk_gen_tb_behav.wcfg
source clk_gen_tb.tcl
restart
run 100 ns
restart
run 100 ns
close_sim
add_files -norecurse /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.srcs/sources_1/new/clk_0_gen.vhd
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
launch_simulation
launch_simulation
open_wave_config /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/clk_gen_tb_behav.wcfg
source clk_gen_tb.tcl
add_wave {{/clk_gen_tb/cg0/cg0/clk_0_r_int}} {{/clk_gen_tb/cg0/cg0/clk_0_f_int}} {{/clk_gen_tb/cg0/cg0/last_clk_0_f_int}}
restart
run 100 ns
close_sim
launch_simulation
open_wave_config /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/clk_gen_tb_behav.wcfg
source clk_gen_tb.tcl
launch_simulation
open_wave_config /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/clk_gen_tb_behav.wcfg
source clk_gen_tb.tcl
close_sim
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
synth_design -rtl -name rtl_1
synth_design -rtl -name rtl_1
close_design
ipx::package_project -root_dir /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi -vendor user.org -library user -taxonomy /UserIP
set_property core_revision 2 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
set_property ip_repo_paths /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi [current_project]
update_ip_catalog
ipx::check_integrity -quiet [ipx::current_core]
ipx::archive_core /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/user.org_user_phase_shift_40MHz_clk_gen_axi_1.0.zip [ipx::current_core]
set_property core_revision 3 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
update_ip_catalog -rebuild -repo_path /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi
ipx::check_integrity -quiet [ipx::current_core]
ipx::archive_core /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/user.org_user_phase_shift_40MHz_clk_gen_axi_1.0.zip [ipx::current_core]
close_project
open_project /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.xpr
set_property ip_repo_paths {/n/15/moore.1424/xillinx/trigger_logic_axi_io /n/15/moore.1424/xillinx/ip_repo /n/15/moore.1424/xillinx/pulse_gen_axi /n/15/moore.1424/xillinx/axi_real_time_clock} [current_project]
update_ip_catalog
update_ip_catalog -rebuild -repo_path /n/15/moore.1424/xillinx/ip_repo
close_project
open_project /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.xpr
ipx::open_ipxact_file /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/component.xml
set_property ip_repo_paths {/n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi /n/15/moore.1424/xillinx/ip_repo} [current_project]
update_ip_catalog
set_property ip_repo_paths {/n/15/moore.1424/xillinx/ip_repo /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi} [current_project]
set_property core_revision 4 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
update_ip_catalog -rebuild -repo_path /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi
ipx::check_integrity -quiet [ipx::current_core]
ipx::archive_core /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/user.org_user_phase_shift_40MHz_clk_gen_axi_1.0.zip [ipx::current_core]
close_project
open_project /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.xpr
set_property ip_repo_paths {/n/15/moore.1424/xillinx/trigger_logic_axi_io /n/15/moore.1424/xillinx/pulse_gen_axi /n/15/moore.1424/xillinx/axi_real_time_clock} [current_project]
update_ip_catalog
set_property ip_repo_paths {/n/15/moore.1424/xillinx/trigger_logic_axi_io /n/15/moore.1424/xillinx/pulse_gen_axi /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi /n/15/moore.1424/xillinx/axi_real_time_clock} [current_project]
update_ip_catalog
open_bd_design {/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd}
startgroup
create_bd_cell -type ip -vlnv user.org:user:phase_shift_40MHz_clk_gen_axi:1.0 phase_shift_40MHz_clk_gen_axi_0
endgroup
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/microblaze_0 (Periph)" Clk "Auto" } [get_bd_intf_pins phase_shift_40MHz_clk_gen_axi_0/S_AXI]
disconnect_bd_net /microblaze_0_Clk [get_bd_pins phase_shift_40MHz_clk_gen_axi_0/S_AXI_ACLK]
delete_bd_objs [get_bd_intf_nets microblaze_0_axi_periph_M09_AXI]
disconnect_bd_net /proc_sys_reset_1_peripheral_aresetn [get_bd_pins phase_shift_40MHz_clk_gen_axi_0/S_AXI_ARESETN]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/microblaze_0 (Periph)" Clk "/clk_wiz_0/clk_out2 (400 MHz)" } [get_bd_intf_pins phase_shift_40MHz_clk_gen_axi_0/S_AXI]
delete_bd_objs [get_bd_intf_nets microblaze_0_axi_periph_M09_AXI] [get_bd_cells phase_shift_40MHz_clk_gen_axi_0]
disconnect_bd_net /proc_sys_reset_1_peripheral_aresetn [get_bd_pins microblaze_0_axi_periph/M09_ARESETN]
disconnect_bd_net /microblaze_0_Clk [get_bd_pins microblaze_0_axi_periph/M09_ACLK]
validate_bd_design
startgroup
set_property -dict [list CONFIG.NUM_MI {9}] [get_bd_cells microblaze_0_axi_periph]
endgroup
validate_bd_design
startgroup
create_bd_cell -type ip -vlnv user.org:user:phase_shift_40MHz_clk_gen_axi:1.0 phase_shift_40MHz_clk_gen_axi_0
endgroup
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/microblaze_0 (Periph)" Clk "/clk_wiz_0/clk_out2 (400 MHz)" } [get_bd_intf_pins phase_shift_40MHz_clk_gen_axi_0/S_AXI]
startgroup
create_bd_port -dir O clk_0
connect_bd_net [get_bd_pins /phase_shift_40MHz_clk_gen_axi_0/clk_0] [get_bd_ports clk_0]
endgroup
startgroup
create_bd_port -dir O clk_1
connect_bd_net [get_bd_pins /phase_shift_40MHz_clk_gen_axi_0/clk_1] [get_bd_ports clk_1]
endgroup
startgroup
create_bd_port -dir O clk_2
connect_bd_net [get_bd_pins /phase_shift_40MHz_clk_gen_axi_0/clk_2] [get_bd_ports clk_2]
endgroup
save_bd_design
close_project
open_project /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.xpr
synth_design -rtl -name rtl_1
synth_design -rtl -name rtl_1
ipx::open_ipxact_file /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/component.xml
ipx::merge_project_changes hdl_parameters [ipx::current_core]
set_property core_revision 5 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
update_ip_catalog -rebuild -repo_path /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi
ipx::check_integrity -quiet [ipx::current_core]
ipx::archive_core /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/user.org_user_phase_shift_40MHz_clk_gen_axi_1.0.zip [ipx::current_core]
close_project
open_project /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.xpr
open_bd_design {/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd}
report_ip_status -name ip_status
upgrade_ip -vlnv user.org:user:phase_shift_40MHz_clk_gen_axi:1.0 [get_ips design_1_phase_shift_40MHz_clk_gen_axi_0_1]
report_ip_status -name ip_status
close_project
open_project /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.xpr
file mkdir /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.srcs/constrs_1
file mkdir /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.srcs/constrs_1/new
close [ open /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.srcs/constrs_1/new/phase_shift_40MHz_clk_constraints.xdc w ]
add_files -fileset constrs_1 /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/phase_shift_40MHz_clk_gen_axi.srcs/constrs_1/new/phase_shift_40MHz_clk_constraints.xdc
open_project /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.xpr
current_project phase_shift_40MHz_clk_gen_axi
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
synth_design -rtl -name rtl_1
synth_design -rtl -name rtl_1
refresh_design
ipx::open_ipxact_file /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/component.xml
ipx::merge_project_changes hdl_parameters [ipx::current_core]
set_property core_revision 6 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
update_ip_catalog -rebuild -repo_path /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi
ipx::check_integrity -quiet [ipx::current_core]
ipx::archive_core /n/15/moore.1424/xillinx/phase_shift_40MHz_clk_gen_axi/user.org_user_phase_shift_40MHz_clk_gen_axi_1.0.zip [ipx::current_core]
close_project
close_project
open_project /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.xpr
open_bd_design {/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd}
report_ip_status -name ip_status
upgrade_ip -vlnv user.org:user:phase_shift_40MHz_clk_gen_axi:1.0 [get_ips design_1_phase_shift_40MHz_clk_gen_axi_0_1]
delete_bd_objs [get_bd_nets phase_shift_40MHz_clk_gen_axi_0_clk_2] [get_bd_ports clk_2]
delete_bd_objs [get_bd_nets phase_shift_40MHz_clk_gen_axi_0_clk_1] [get_bd_ports clk_1]
delete_bd_objs [get_bd_nets phase_shift_40MHz_clk_gen_axi_0_clk_0] [get_bd_ports clk_0]
startgroup
create_bd_port -dir O -from 1 -to 0 clk_0
connect_bd_net [get_bd_pins /phase_shift_40MHz_clk_gen_axi_0/clk_0] [get_bd_ports clk_0]
endgroup
startgroup
create_bd_port -dir O -from 1 -to 0 clk_1
connect_bd_net [get_bd_pins /phase_shift_40MHz_clk_gen_axi_0/clk_1] [get_bd_ports clk_1]
endgroup
startgroup
create_bd_port -dir O -from 1 -to 0 clk_2
connect_bd_net [get_bd_pins /phase_shift_40MHz_clk_gen_axi_0/clk_2] [get_bd_ports clk_2]
endgroup
save_bd_design
report_ip_status -name ip_status
reset_run synth_1
launch_runs impl_1 -jobs 8
wait_on_run impl_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
wait_on_run impl_1
open_run impl_1