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vivado.log
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vivado.log
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#-----------------------------------------------------------
# Vivado v2015.2 (64-bit)
# SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
# Start of session at: Thu Dec 17 15:09:48 2015
# Process ID: 8939
# Log file: /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/vivado.log
# Journal file: /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/n/15/moore.1424/xillinx/trigger_logic_axi_io'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/n/15/moore.1424/xillinx/pulse_gen_axi'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/n/15/moore.1424/xillinx/axi_real_time_clock'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/xilinx/Vivado/2015.2/data/ip'.
open_project: Time (s): cpu = 00:00:41 ; elapsed = 00:00:23 . Memory (MB): peak = 6034.574 ; gain = 220.945 ; free physical = 1390 ; free virtual = 22837
launch_sdk -workspace /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk -hwspec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk -hwspec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre
WARNING: [Common 17-259] Unknown Tcl command 'mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre' sending command to the OS shell for execution.
ls
WARNING: [Common 17-259] Unknown Tcl command 'ls' sending command to the OS shell for execution.
ac701_mig.ucf
hs_err_pid22817.log
image.mfs
memfs
project_1.cache
project_1.hw
project_1.runs
project_1.sdk
project_1.sdk.bac
project_1.sdk.bac.10_5_2016
project_1.sdk.broken
project_1.sim
project_1.srcs
project_1.xpr
updatemem_7663.backup.jou
updatemem_7663.backup.log
updatemem.jou
updatemem.log
vivado_186684.backup.jou
vivado_186684.backup.log
vivado_22817.backup.jou
vivado_22817.backup.log
vivado_3400.backup.jou
vivado_3400.backup.log
vivado_7294.backup.jou
vivado_7294.backup.log
vivado_8939.backup.jou
vivado_8939.backup.log
vivado.jou
vivado.log
vivado_pid22817.str
vivado_pid7294.str
vivado_pid7950.zip
vivado_pid86952.zip
vivado_pid8939.str
webtalk.jou
webtalk.log
ls
WARNING: [Common 17-259] Unknown Tcl command 'ls' sending command to the OS shell for execution.
ac701_mig.ucf
hs_err_pid22817.log
image.mfs
memfs
project_1.cache
project_1.hw
project_1.runs
project_1.sdk
project_1.sdk.bac
project_1.sdk.bac.10_5_2016
project_1.sdk.broken
project_1.sim
project_1.srcs
project_1.xpr
updatemem_7663.backup.jou
updatemem_7663.backup.log
updatemem.jou
updatemem.log
vivado_186684.backup.jou
vivado_186684.backup.log
vivado_22817.backup.jou
vivado_22817.backup.log
vivado_3400.backup.jou
vivado_3400.backup.log
vivado_7294.backup.jou
vivado_7294.backup.log
vivado_8939.backup.jou
vivado_8939.backup.log
vivado.jou
vivado.log
vivado_pid22817.str
vivado_pid7294.str
vivado_pid7950.zip
vivado_pid86952.zip
vivado_pid8939.str
webtalk.jou
webtalk.log
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy
WARNING: [Common 17-259] Unknown Tcl command '/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy' sending command to the OS shell for execution.
Usage: /opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy [option(s)] in-file [out-file]
Copies a binary file, possibly transforming it in the process
The options are:
-I --input-target <bfdname> Assume input file is in format <bfdname>
-O --output-target <bfdname> Create an output file in format <bfdname>
-B --binary-architecture <arch> Set output arch, when input is arch-less
-F --target <bfdname> Set both input and output format to <bfdname>
--debugging Convert debugging information, if possible
-p --preserve-dates Copy modified/access timestamps to the output
-D --enable-deterministic-archives
Produce deterministic output when stripping archives
-U --disable-deterministic-archives
Disable -D behavior (default)
-j --only-section <name> Only copy section <name> into the output
--add-gnu-debuglink=<file> Add section .gnu_debuglink linking to <file>
-R --remove-section <name> Remove section <name> from the output
-S --strip-all Remove all symbol and relocation information
-g --strip-debug Remove all debugging symbols & sections
--strip-dwo Remove all DWO sections
--strip-unneeded Remove all symbols not needed by relocations
-N --strip-symbol <name> Do not copy symbol <name>
--strip-unneeded-symbol <name>
Do not copy symbol <name> unless needed by
relocations
--only-keep-debug Strip everything but the debug information
--extract-dwo Copy only DWO sections
--extract-symbol Remove section contents but keep symbols
-K --keep-symbol <name> Do not strip symbol <name>
--keep-file-symbols Do not strip file symbol(s)
--localize-hidden Turn all ELF hidden symbols into locals
-L --localize-symbol <name> Force symbol <name> to be marked as a local
--globalize-symbol <name> Force symbol <name> to be marked as a global
-G --keep-global-symbol <name> Localize all symbols except <name>
-W --weaken-symbol <name> Force symbol <name> to be marked as a weak
--weaken Force all global symbols to be marked as weak
-w --wildcard Permit wildcard in symbol comparison
-x --discard-all Remove all non-global symbols
-X --discard-locals Remove any compiler-generated symbols
-i --interleave [<number>] Only copy N out of every <number> bytes
--interleave-width <number> Set N for --interleave
-b --byte <num> Select byte <num> in every interleaved block
--gap-fill <val> Fill gaps between sections with <val>
--pad-to <addr> Pad the last section up to address <addr>
--set-start <addr> Set the start address to <addr>
{--change-start|--adjust-start} <incr>
Add <incr> to the start address
{--change-addresses|--adjust-vma} <incr>
Add <incr> to LMA, VMA and start addresses
{--change-section-address|--adjust-section-vma} <name>{=|+|-}<val>
Change LMA and VMA of section <name> by <val>
--change-section-lma <name>{=|+|-}<val>
Change the LMA of section <name> by <val>
--change-section-vma <name>{=|+|-}<val>
Change the VMA of section <name> by <val>
{--[no-]change-warnings|--[no-]adjust-warnings}
Warn if a named section does not exist
--set-section-flags <name>=<flags>
Set section <name>'s properties to <flags>
--add-section <name>=<file> Add section <name> found in <file> to output
--rename-section <old>=<new>[,<flags>] Rename section <old> to <new>
--long-section-names {enable|disable|keep}
Handle long section names in Coff objects.
--change-leading-char Force output format's leading character style
--remove-leading-char Remove leading character from global symbols
--reverse-bytes=<num> Reverse <num> bytes at a time, in output sections with content
--redefine-sym <old>=<new> Redefine symbol name <old> to <new>
--redefine-syms <file> --redefine-sym for all symbol pairs
listed in <file>
--srec-len <number> Restrict the length of generated Srecords
--srec-forceS3 Restrict the type of generated Srecords to S3
--strip-symbols <file> -N for all symbols listed in <file>
--strip-unneeded-symbols <file>
--strip-unneeded-symbol for all symbols listed
in <file>
--keep-symbols <file> -K for all symbols listed in <file>
--localize-symbols <file> -L for all symbols listed in <file>
--globalize-symbols <file> --globalize-symbol for all in <file>
--keep-global-symbols <file> -G for all symbols listed in <file>
--weaken-symbols <file> -W for all symbols listed in <file>
--alt-machine-code <index> Use the target's <index>'th alternative machine
--writable-text Mark the output text as writable
--readonly-text Make the output text write protected
--pure Mark the output file as demand paged
--impure Mark the output file as impure
--prefix-symbols <prefix> Add <prefix> to start of every symbol name
--prefix-sections <prefix> Add <prefix> to start of every section name
--prefix-alloc-sections <prefix>
Add <prefix> to start of every allocatable
section name
--file-alignment <num> Set PE file alignment to <num>
--heap <reserve>[,<commit>] Set PE reserve/commit heap to <reserve>/
<commit>
--image-base <address> Set PE image base to <address>
--section-alignment <num> Set PE section alignment to <num>
--stack <reserve>[,<commit>] Set PE reserve/commit stack to <reserve>/
<commit>
--subsystem <name>[:<version>]
Set PE subsystem to <name> [& <version>]
--compress-debug-sections Compress DWARF debug sections using zlib
--decompress-debug-sections Decompress DWARF debug sections using zlib
-v --verbose List all object files modified
@<file> Read options from <file>
-V --version Display this program's version number
-h --help Display this output
--info List object formats & architectures supported
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy: supported targets: elf32-microblaze elf32-microblazeel elf32-little elf32-big srec symbolsrec verilog tekhex binary ihex
set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
WARNING: [Vivado 12-628] No current design set.
ERROR: [Common 17-161] Invalid option value '' specified for 'objects'.
set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
WARNING: [Vivado 12-628] No current design set.
ERROR: [Common 17-161] Invalid option value '' specified for 'objects'.
write_bitstream -force /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
reset_run impl_1 -prev_step
launch_runs impl_1 -to_step write_bitstream -jobs 8
[Thu Dec 17 16:00:21 2015] Launched impl_1...
Run output will be captured here: /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/runme.log
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre
WARNING: [Common 17-259] Unknown Tcl command '/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre' sending command to the OS shell for execution.
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy
WARNING: [Common 17-259] Unknown Tcl command '/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy' sending command to the OS shell for execution.
Usage: /opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy [option(s)] in-file [out-file]
Copies a binary file, possibly transforming it in the process
The options are:
-I --input-target <bfdname> Assume input file is in format <bfdname>
-O --output-target <bfdname> Create an output file in format <bfdname>
-B --binary-architecture <arch> Set output arch, when input is arch-less
-F --target <bfdname> Set both input and output format to <bfdname>
--debugging Convert debugging information, if possible
-p --preserve-dates Copy modified/access timestamps to the output
-D --enable-deterministic-archives
Produce deterministic output when stripping archives
-U --disable-deterministic-archives
Disable -D behavior (default)
-j --only-section <name> Only copy section <name> into the output
--add-gnu-debuglink=<file> Add section .gnu_debuglink linking to <file>
-R --remove-section <name> Remove section <name> from the output
-S --strip-all Remove all symbol and relocation information
-g --strip-debug Remove all debugging symbols & sections
--strip-dwo Remove all DWO sections
--strip-unneeded Remove all symbols not needed by relocations
-N --strip-symbol <name> Do not copy symbol <name>
--strip-unneeded-symbol <name>
Do not copy symbol <name> unless needed by
relocations
--only-keep-debug Strip everything but the debug information
--extract-dwo Copy only DWO sections
--extract-symbol Remove section contents but keep symbols
-K --keep-symbol <name> Do not strip symbol <name>
--keep-file-symbols Do not strip file symbol(s)
--localize-hidden Turn all ELF hidden symbols into locals
-L --localize-symbol <name> Force symbol <name> to be marked as a local
--globalize-symbol <name> Force symbol <name> to be marked as a global
-G --keep-global-symbol <name> Localize all symbols except <name>
-W --weaken-symbol <name> Force symbol <name> to be marked as a weak
--weaken Force all global symbols to be marked as weak
-w --wildcard Permit wildcard in symbol comparison
-x --discard-all Remove all non-global symbols
-X --discard-locals Remove any compiler-generated symbols
-i --interleave [<number>] Only copy N out of every <number> bytes
--interleave-width <number> Set N for --interleave
-b --byte <num> Select byte <num> in every interleaved block
--gap-fill <val> Fill gaps between sections with <val>
--pad-to <addr> Pad the last section up to address <addr>
--set-start <addr> Set the start address to <addr>
{--change-start|--adjust-start} <incr>
Add <incr> to the start address
{--change-addresses|--adjust-vma} <incr>
Add <incr> to LMA, VMA and start addresses
{--change-section-address|--adjust-section-vma} <name>{=|+|-}<val>
Change LMA and VMA of section <name> by <val>
--change-section-lma <name>{=|+|-}<val>
Change the LMA of section <name> by <val>
--change-section-vma <name>{=|+|-}<val>
Change the VMA of section <name> by <val>
{--[no-]change-warnings|--[no-]adjust-warnings}
Warn if a named section does not exist
--set-section-flags <name>=<flags>
Set section <name>'s properties to <flags>
--add-section <name>=<file> Add section <name> found in <file> to output
--rename-section <old>=<new>[,<flags>] Rename section <old> to <new>
--long-section-names {enable|disable|keep}
Handle long section names in Coff objects.
--change-leading-char Force output format's leading character style
--remove-leading-char Remove leading character from global symbols
--reverse-bytes=<num> Reverse <num> bytes at a time, in output sections with content
--redefine-sym <old>=<new> Redefine symbol name <old> to <new>
--redefine-syms <file> --redefine-sym for all symbol pairs
listed in <file>
--srec-len <number> Restrict the length of generated Srecords
--srec-forceS3 Restrict the type of generated Srecords to S3
--strip-symbols <file> -N for all symbols listed in <file>
--strip-unneeded-symbols <file>
--strip-unneeded-symbol for all symbols listed
in <file>
--keep-symbols <file> -K for all symbols listed in <file>
--localize-symbols <file> -L for all symbols listed in <file>
--globalize-symbols <file> --globalize-symbol for all in <file>
--keep-global-symbols <file> -G for all symbols listed in <file>
--weaken-symbols <file> -W for all symbols listed in <file>
--alt-machine-code <index> Use the target's <index>'th alternative machine
--writable-text Mark the output text as writable
--readonly-text Make the output text write protected
--pure Mark the output file as demand paged
--impure Mark the output file as impure
--prefix-symbols <prefix> Add <prefix> to start of every symbol name
--prefix-sections <prefix> Add <prefix> to start of every section name
--prefix-alloc-sections <prefix>
Add <prefix> to start of every allocatable
section name
--file-alignment <num> Set PE file alignment to <num>
--heap <reserve>[,<commit>] Set PE reserve/commit heap to <reserve>/
<commit>
--image-base <address> Set PE image base to <address>
--section-alignment <num> Set PE section alignment to <num>
--stack <reserve>[,<commit>] Set PE reserve/commit stack to <reserve>/
<commit>
--subsystem <name>[:<version>]
Set PE subsystem to <name> [& <version>]
--compress-debug-sections Compress DWARF debug sections using zlib
--decompress-debug-sections Decompress DWARF debug sections using zlib
-v --verbose List all object files modified
@<file> Read options from <file>
-V --version Display this program's version number
-h --help Display this output
--info List object formats & architectures supported
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy: supported targets: elf32-microblaze elf32-microblazeel elf32-little elf32-big srec symbolsrec verilog tekhex binary ihex
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre
WARNING: [Common 17-259] Unknown Tcl command '/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre' sending command to the OS shell for execution.
"/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre"
invalid command name "/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre"
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy ' -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre'
WARNING: [Common 17-259] Unknown Tcl command '/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy ' -O srec /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.elf /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre'' sending command to the OS shell for execution.
Usage: /opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy [option(s)] in-file [out-file]
Copies a binary file, possibly transforming it in the process
The options are:
-I --input-target <bfdname> Assume input file is in format <bfdname>
-O --output-target <bfdname> Create an output file in format <bfdname>
-B --binary-architecture <arch> Set output arch, when input is arch-less
-F --target <bfdname> Set both input and output format to <bfdname>
--debugging Convert debugging information, if possible
-p --preserve-dates Copy modified/access timestamps to the output
-D --enable-deterministic-archives
Produce deterministic output when stripping archives
-U --disable-deterministic-archives
Disable -D behavior (default)
-j --only-section <name> Only copy section <name> into the output
--add-gnu-debuglink=<file> Add section .gnu_debuglink linking to <file>
-R --remove-section <name> Remove section <name> from the output
-S --strip-all Remove all symbol and relocation information
-g --strip-debug Remove all debugging symbols & sections
--strip-dwo Remove all DWO sections
--strip-unneeded Remove all symbols not needed by relocations
-N --strip-symbol <name> Do not copy symbol <name>
--strip-unneeded-symbol <name>
Do not copy symbol <name> unless needed by
relocations
--only-keep-debug Strip everything but the debug information
--extract-dwo Copy only DWO sections
--extract-symbol Remove section contents but keep symbols
-K --keep-symbol <name> Do not strip symbol <name>
--keep-file-symbols Do not strip file symbol(s)
--localize-hidden Turn all ELF hidden symbols into locals
-L --localize-symbol <name> Force symbol <name> to be marked as a local
--globalize-symbol <name> Force symbol <name> to be marked as a global
-G --keep-global-symbol <name> Localize all symbols except <name>
-W --weaken-symbol <name> Force symbol <name> to be marked as a weak
--weaken Force all global symbols to be marked as weak
-w --wildcard Permit wildcard in symbol comparison
-x --discard-all Remove all non-global symbols
-X --discard-locals Remove any compiler-generated symbols
-i --interleave [<number>] Only copy N out of every <number> bytes
--interleave-width <number> Set N for --interleave
-b --byte <num> Select byte <num> in every interleaved block
--gap-fill <val> Fill gaps between sections with <val>
--pad-to <addr> Pad the last section up to address <addr>
--set-start <addr> Set the start address to <addr>
{--change-start|--adjust-start} <incr>
Add <incr> to the start address
{--change-addresses|--adjust-vma} <incr>
Add <incr> to LMA, VMA and start addresses
{--change-section-address|--adjust-section-vma} <name>{=|+|-}<val>
Change LMA and VMA of section <name> by <val>
--change-section-lma <name>{=|+|-}<val>
Change the LMA of section <name> by <val>
--change-section-vma <name>{=|+|-}<val>
Change the VMA of section <name> by <val>
{--[no-]change-warnings|--[no-]adjust-warnings}
Warn if a named section does not exist
--set-section-flags <name>=<flags>
Set section <name>'s properties to <flags>
--add-section <name>=<file> Add section <name> found in <file> to output
--rename-section <old>=<new>[,<flags>] Rename section <old> to <new>
--long-section-names {enable|disable|keep}
Handle long section names in Coff objects.
--change-leading-char Force output format's leading character style
--remove-leading-char Remove leading character from global symbols
--reverse-bytes=<num> Reverse <num> bytes at a time, in output sections with content
--redefine-sym <old>=<new> Redefine symbol name <old> to <new>
--redefine-syms <file> --redefine-sym for all symbol pairs
listed in <file>
--srec-len <number> Restrict the length of generated Srecords
--srec-forceS3 Restrict the type of generated Srecords to S3
--strip-symbols <file> -N for all symbols listed in <file>
--strip-unneeded-symbols <file>
--strip-unneeded-symbol for all symbols listed
in <file>
--keep-symbols <file> -K for all symbols listed in <file>
--localize-symbols <file> -L for all symbols listed in <file>
--globalize-symbols <file> --globalize-symbol for all in <file>
--keep-global-symbols <file> -G for all symbols listed in <file>
--weaken-symbols <file> -W for all symbols listed in <file>
--alt-machine-code <index> Use the target's <index>'th alternative machine
--writable-text Mark the output text as writable
--readonly-text Make the output text write protected
--pure Mark the output file as demand paged
--impure Mark the output file as impure
--prefix-symbols <prefix> Add <prefix> to start of every symbol name
--prefix-sections <prefix> Add <prefix> to start of every section name
--prefix-alloc-sections <prefix>
Add <prefix> to start of every allocatable
section name
--file-alignment <num> Set PE file alignment to <num>
--heap <reserve>[,<commit>] Set PE reserve/commit heap to <reserve>/
<commit>
--image-base <address> Set PE image base to <address>
--section-alignment <num> Set PE section alignment to <num>
--stack <reserve>[,<commit>] Set PE reserve/commit stack to <reserve>/
<commit>
--subsystem <name>[:<version>]
Set PE subsystem to <name> [& <version>]
--compress-debug-sections Compress DWARF debug sections using zlib
--decompress-debug-sections Decompress DWARF debug sections using zlib
-v --verbose List all object files modified
@<file> Read options from <file>
-V --version Display this program's version number
-h --help Display this output
--info List object formats & architectures supported
/opt/xilinx/SDK/2015.2/gnu/microblaze/lin/bin/mb-objcopy: supported targets: elf32-microblaze elf32-microblazeel elf32-little elf32-big srec symbolsrec verilog tekhex binary ihex
write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit "up 0x00000000 design_1_test.bit up 0x00A00000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre" AC701.mcs
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile design_1_test.bit
ERROR: [Bitstream 40-47] File design_1_test.bit does not exist.
ERROR: [Bitstream 40-46] File design_1_test.bit cannot be opened for input.
ERROR: [Vivado 12-3540] Could not load bitfile design_1_test.bit.
ERROR: [Common 17-39] 'write_cfgmem' failed due to earlier errors.
write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit "up 0x00000000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit up 0x00A00000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre" AC701.mcs
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
ERROR: [Vivado 12-3735] SPI_BUSWIDTH property is set to "1" on bitfile /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit. This property has to be set to "4" to generate a configuration memory file for the SPIX4 interface. Please ensure that a valid value has been set for the property BITSTREAM.Config.SPI_buswidth and rerun this command.
ERROR: [Common 17-39] 'write_cfgmem' failed due to earlier errors.
write_bitstream -force /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
open_run impl_1
INFO: [Netlist 29-17] Analyzing 2445 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2015.2
INFO: [Device 21-403] Loading part xc7a200tfbg676-2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/.Xil/Vivado-8939-cadence11/dcp/design_1_wrapper_early.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xdc:50]
INFO: [Timing 38-2] Deriving generated clocks [/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xdc:50]
get_clocks: Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 7228.160 ; gain = 591.668 ; free physical = 748 ; free virtual = 20505
INFO: [Timing 38-2] Deriving generated clocks [/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc:56]
get_clocks: Time (s): cpu = 00:00:15 ; elapsed = 00:00:06 . Memory (MB): peak = 7256.160 ; gain = 21.000 ; free physical = 720 ; free virtual = 20476
Finished Parsing XDC File [/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/.Xil/Vivado-8939-cadence11/dcp/design_1_wrapper_early.xdc]
Parsing XDC File [/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/.Xil/Vivado-8939-cadence11/dcp/design_1_wrapper.xdc]
Finished Parsing XDC File [/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/.Xil/Vivado-8939-cadence11/dcp/design_1_wrapper.xdc]
Parsing XDC File [/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/.Xil/Vivado-8939-cadence11/dcp/design_1_wrapper_late.xdc]
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'design_1_i/axi_ethernet_0/U0/eth_mac/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/ip/ip_1/synth/bd_0_eth_mac_0_clocks.xdc:29]
Finished Parsing XDC File [/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/.Xil/Vivado-8939-cadence11/dcp/design_1_wrapper_late.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 7341.512 ; gain = 67.352 ; free physical = 628 ; free virtual = 20384
Restored from archive | CPU: 7.580000 secs | Memory: 75.004967 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 7341.512 ; gain = 67.352 ; free physical = 628 ; free virtual = 20384
Generating merged BMM file for the design top 'design_1_wrapper'...
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/imports/Debug/spi_bootloader.elf
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 928 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 6 instances
IOBUFDS_DIFF_OUT_INTERMDISABLE => IOBUFDS_DIFF_OUT_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT, IBUFDS_INTERMDISABLE_INT, OBUFTDS, OBUFTDS, INV): 8 instances
IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 64 instances
LUT6_2 => LUT6_2 (LUT5, LUT6): 82 instances
OBUFDS => OBUFDS: 9 instances
OBUFDS => OBUFDS_DUAL_BUF (OBUFDS, OBUFDS, INV): 1 instances
RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 560 instances
RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 6 instances
RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 160 instances
open_run: Time (s): cpu = 00:03:01 ; elapsed = 00:01:54 . Memory (MB): peak = 7514.871 ; gain = 1377.297 ; free physical = 583 ; free virtual = 20226
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
write_bitstream -force /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-1223] The version limit for your license is '2015.10' and will expire in -47 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC 23-20] Rule violation (BUFC-1) Input Buffer Connections - Input buffer spi_flash_ss_iobuf_0/IBUF (in spi_flash_ss_iobuf_0 macro) has no loads. An input buffer must drive an internal load.
WARNING: [DRC 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_MUL_I/Use_DSP48E1.dsp_module_lower/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_MUL_I/Use_DSP48E1.dsp_module_upper/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.Doing_mul64.Virtex_MUL64.dsp_module_I2/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.Doing_mul64.Virtex_MUL64.dsp_module_I3/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.Doing_mul64.Virtex_MUL64.dsp_module_I4/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel1 input B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel1__0 input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel2 input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r1 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_mux/wl_po_fine_shifted0 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_po_cntlr/simp_stg3_final_shft0 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_po_cntlr/stg2_target_r_reg input A B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/offset0_return3 input A B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/offset_return3 input A B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/offset_return4 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/rise_lead_center_offset_r_reg input B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_data_offset_01 input A is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row_cnt0 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row_cnt0__0 input A B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_prbs_gen/sel1 input A B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/real_time_clock_v1_0_S00_AXI_0/U0/rc1/msrtc/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/real_time_clock_v1_0_S00_AXI_0/U0/rc1/rtc1/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/real_time_clock_v1_0_S00_AXI_0/U0/rc1/rtc2/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/handshake_counter/beam_c/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/handshake_unit1/c0/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B C is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/per1/prescaler_counter/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/prescaler_xor_pulser_AND_prescaler_delayed_counter/beam_c/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/prescaler_xor_pulser_counter/beam_c/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/pulser_0p1_to_10Hz/c1/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/pulser_0p1_to_10Hz/c2/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/pulser_delayed_AND_prescaler_xor_pulser_counter/beam_c/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/beam_current_counter/beam_c/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[0].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[1].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[2].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[3].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[4].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[5].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[6].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[7].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[8].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[9].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/u1_coincidence_unit/q_count/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/u2_coincidence_unit/q_count/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive input B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_MUL_I/Use_DSP48E1.dsp_module_lower/Using_DSP48E1.DSP48E1_I1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.Doing_mul64.Virtex_MUL64.dsp_module_I2/Using_DSP48E1.DSP48E1_I1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.Doing_mul64.Virtex_MUL64.dsp_module_I3/Using_DSP48E1.DSP48E1_I1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel1__0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel2 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_mux/wl_po_fine_shifted0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_po_cntlr/simp_stg3_final_shft0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_po_cntlr/stg2_target_r_reg output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/offset0_return3 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/offset_return3 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/offset_return4 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/rise_lead_center_offset_r_reg output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_data_offset_01 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row_cnt0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row_cnt0__0 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_prbs_gen/sel1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/real_time_clock_v1_0_S00_AXI_0/U0/rc1/msrtc/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/real_time_clock_v1_0_S00_AXI_0/U0/rc1/rtc1/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/real_time_clock_v1_0_S00_AXI_0/U0/rc1/rtc2/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/handshake_counter/beam_c/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/handshake_unit1/c0/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/per1/prescaler_counter/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/prescaler_xor_pulser_AND_prescaler_delayed_counter/beam_c/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/prescaler_xor_pulser_counter/beam_c/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/pulser_0p1_to_10Hz/c1/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/pulser_0p1_to_10Hz/c2/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/backend_logic/pulser_delayed_AND_prescaler_xor_pulser_counter/beam_c/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/beam_current_counter/beam_c/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[0].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[1].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[2].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[3].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[4].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[5].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[6].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[7].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[8].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/gen_trig_counters[9].trig_countn/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/u1_coincidence_unit/q_count/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (DPOP-1) Output pipelining - DSP design_1_i/trigger_logic_AXI_0/U0/frontend_logic/u2_coincidence_unit/q_count/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx7.i_dsp48e_wrap/i_primitive output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [DRC 23-20] Rule violation (REQP-1709) Clock output buffering - PLLE2_ADV connectivity violation. The signal design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out on the design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned.
WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR[10] (net: design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/ADDRB[4]) which is driven by a register (design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR[11] (net: design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/ADDRB[5]) which is driven by a register (design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR[12] (net: design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/ADDRB[6]) which is driven by a register (design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR[13] (net: design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/ADDRB[7]) which is driven by a register (design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR[14] (net: design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/ADDRB[8]) which is driven by a register (design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR[6] (net: design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/ADDRB[0]) which is driven by a register (design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR[7] (net: design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/ADDRB[1]) which is driven by a register (design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR[8] (net: design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/ADDRB[2]) which is driven by a register (design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR[9] (net: design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/ADDRB[3]) which is driven by a register (design_1_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Common 17-14] Message 'DRC 23-20' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 218 Warnings, 24 Advisories
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Generating merged BMM file for the design top 'design_1_wrapper'...
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/imports/Debug/spi_bootloader.elf
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:03:00 ; elapsed = 00:02:38 . Memory (MB): peak = 7932.512 ; gain = 386.359 ; free physical = 227 ; free virtual = 18989
/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit "up 0x00000000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit up 0x00A00000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre" AC701.mcs
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
Creating bitstream load up from address 0x00A00000
Loading bitfile /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre
ERROR: [Bitstream 40-48] File /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre has unknown file format.
ERROR: [Vivado 12-3540] Could not load bitfile /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre.
ERROR: [Common 17-39] 'write_cfgmem' failed due to earlier errors.
write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit "up 0x00000000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit" -loaddata "up 0x00A00000 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre" AC701.mcs
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
Creating bitstream load up from address 0x00A00000
Loading datafile /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre
Writing file ./AC701.mcs
Writing log file ./AC701.prm
===================================
Configuration Memory information
===================================
File Format MCS
Interface SPIX4
Size 32M
Start Address 0x00000000
End Address 0x01FFFFFF
Addr1 Addr2 Date File(s)
0x00000000 0x00947A5B Dec 17 16:27:19 2015 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.runs/impl_1/design_1_wrapper.bit
0x00A00000 0x00A9358B Dec 17 16:28:49 2015 /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.sdk/helo_world/Debug/helo_world.sre
pwd
/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW
open_hw
connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
localhost:3121
current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
localhost:3121/xilinx_tcf/Digilent/210203343119A
set_property PARAM.FREQUENCY 30000000 [get_hw_targets */xilinx_tcf/Digilent/*]
15000000
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210203343119A
current_hw_device [lindex [get_hw_devices] 0]
xc7a200t_0
refresh_hw_device [lindex [get_hw_devices] 0]
INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {n25q256-3.3v-spi-x1_x2_x4}] 0]
n25q256-3.3v-spi-x1_x2_x4_0
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
refresh_hw_device [lindex [get_hw_devices] 0]
INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.FILE {AC701.mcs} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]]
WARNING: [Common 17-599] Property 'PROGRAM.FILE' is deprecated for object type 'hw_cfgmem'. Use PROGRAM.FILES property.
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]]]] } { create_hw_bitstream -hw_device [lindex [get_hw_devices] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices] 0]]; program_hw_devices [lindex [get_hw_devices] 0]; };
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
Mfg ID : 20 Memory Type : ba Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
Performing Erase Operation...
Erase Operation successful.
Performing Program and Verify Operations...
Program/Verify Operation successful.
INFO: [Labtoolstcl 44-377] Flash programming completed successfully
program_hw_cfgmem: Time (s): cpu = 00:00:09 ; elapsed = 00:05:27 . Memory (MB): peak = 7958.324 ; gain = 0.000 ; free physical = 269 ; free virtual = 18518
disconnect_hw_server localhost:3121
close_hw
close_project
open_project /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/n/15/moore.1424/xillinx/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/xilinx/Vivado/2015.2/data/ip'.
open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 7961.340 ; gain = 0.000 ; free physical = 3316 ; free virtual = 21130
reset_run synth_1
launch_runs synth_1 -jobs 8
INFO: [HDL 9-2216] Analyzing Verilog file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/all_input_delays.v" into library work [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/all_input_delays.v:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/add_module.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/add_module.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/beam_current_monitor.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/beam_current_monitor.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/dsp_edge_c_16bit.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/dsp_edge_c_16bit.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/edge_detector.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/edge_detector.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/fixed_1Hz_pulse_gen.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/fixed_1Hz_pulse_gen.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/handshake_unit.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/handshake_unit.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/mux_10_to_2.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/mux_10_to_2.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/one_ch_delay.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/one_ch_delay.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/prescaler.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/prescaler.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/pulse_gen.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/pulse_gen.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/tmp/pulse_gen_ripple.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/tmp/pulse_gen_ripple.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/rate_counter.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/rate_counter.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/rate_counters.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/rate_counters.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/test_mux.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/test_mux.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_backend.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_backend.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_frontend.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_frontend.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/trigger_logic_axi.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/trigger_logic_axi.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/varable_delays.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/varable_delays.vhd:1]
[Fri Dec 18 17:23:45 2015] Launched synth_1...
Run output will be captured here: /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.runs/synth_1/runme.log
reset_run synth_1
launch_runs synth_1 -jobs 8
INFO: [HDL 9-2216] Analyzing Verilog file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/all_input_delays.v" into library work [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/all_input_delays.v:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/add_module.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/add_module.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/beam_current_monitor.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/beam_current_monitor.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/dsp_edge_c_16bit.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/dsp_edge_c_16bit.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/edge_detector.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/edge_detector.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/fixed_1Hz_pulse_gen.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/fixed_1Hz_pulse_gen.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/handshake_unit.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/handshake_unit.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/mux_10_to_2.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/mux_10_to_2.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/one_ch_delay.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/one_ch_delay.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/prescaler.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/prescaler.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/pulse_gen.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/pulse_gen.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/tmp/pulse_gen_ripple.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/tmp/pulse_gen_ripple.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/rate_counter.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/rate_counter.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/rate_counters.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/rate_counters.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/test_mux.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/test_mux.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_backend.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_backend.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_frontend.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_frontend.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/trigger_logic_axi.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/trigger_logic_axi.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/varable_delays.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/varable_delays.vhd:1]
[Fri Dec 18 17:25:09 2015] Launched synth_1...
Run output will be captured here: /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.runs/synth_1/runme.log
launch_runs impl_1 -jobs 8
[Fri Dec 18 17:28:48 2015] Launched impl_1...
Run output will be captured here: /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.runs/impl_1/runme.log
ipx::open_ipxact_file /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/component.xml
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/edge_detector.vhd'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/dsp_edge_c_16bit.vhd'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/rate_counter.vhd'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/fixed_1Hz_pulse_gen.vhd'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/rate_counters.vhd'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/test_mux.vhd'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/all_input_delays.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/varable_delays.vhd'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/mux_10_to_2.vhd'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/tmp/pulse_gen_ripple.vhd'.
set_property core_revision 32 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
update_ip_catalog -rebuild -repo_path /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs
INFO: [IP_Flow 19-725] Reloaded user IP repository '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs'
ipx::check_integrity -quiet [ipx::current_core]
ipx::archive_core /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/user.org_user_trigger_logic_AXI_1.1.zip [ipx::current_core]
close_project
open_project /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/n/15/moore.1424/xillinx/trigger_logic_axi_io'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/n/15/moore.1424/xillinx/pulse_gen_axi'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/n/15/moore.1424/xillinx/axi_real_time_clock'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/xilinx/Vivado/2015.2/data/ip'.
WARNING: [BD 41-1661] One or more IPs have been locked in the design 'design_1.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
design_1_trigger_logic_AXI_0_0
open_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 7961.340 ; gain = 0.000 ; free physical = 3280 ; free virtual = 21096
open_bd_design {/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd}
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.0 - axi_bram_ctrl_0
Adding component instance block -- xilinx.com:ip:axi_ethernet:7.0 - axi_ethernet_0
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_ethernet_0_dma
Adding component instance block -- xilinx.com:ip:axi_timer:2.0 - axi_timer_0
Adding component instance block -- xilinx.com:ip:axi_uartlite:2.0 - axi_uartlite_0
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.2 - blk_mem_gen_0
Adding component instance block -- xilinx.com:ip:clk_wiz:5.1 - clk_wiz_0
Adding component instance block -- xilinx.com:ip:mdm:3.2 - mdm_1
Adding component instance block -- xilinx.com:ip:microblaze:9.5 - microblaze_0
Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - microblaze_0_axi_intc
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - microblaze_0_xlconcat
Adding component instance block -- xilinx.com:ip:mig_7series:2.3 - mig_7series_0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_1
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_clk_wiz_0_401M
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_clk_wiz_0_125M
Adding component instance block -- user.org:user:real_time_clock_v1_0_S00_AXI:1.0 - real_time_clock_v1_0_S00_AXI_0
Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - axi_quad_spi_0
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0
Adding component instance block -- user.org:user:trigger_logic_AXI:1.1 - trigger_logic_AXI_0
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_data_fifo:2.1 - s04_data_fifo
Adding component instance block -- xilinx.com:ip:axi_data_fifo:2.1 - s03_data_fifo
Adding component instance block -- xilinx.com:ip:axi_data_fifo:2.1 - s02_data_fifo
Adding component instance block -- xilinx.com:ip:axi_data_fifo:2.1 - s01_data_fifo
Adding component instance block -- xilinx.com:ip:axi_data_fifo:2.1 - s00_data_fifo
Adding component instance block -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - dlmb_bram_if_cntlr
Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - dlmb_v10
Adding component instance block -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - ilmb_bram_if_cntlr
Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - ilmb_v10
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.2 - lmb_bram
Successfully read diagram <design_1> from BD file </data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd>
open_bd_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 7961.340 ; gain = 0.000 ; free physical = 3278 ; free virtual = 21093
report_ip_status -name ip_status
upgrade_ip -vlnv user.org:user:trigger_logic_AXI:1.1 [get_ips design_1_trigger_logic_AXI_0_0]
Upgrading '/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd'
INFO: [IP_Flow 19-3422] Upgraded design_1_trigger_logic_AXI_0_0 (trigger_logic_AXI_v1_1 1.1) from revision 31 to revision 32
INFO: [IP_Flow 19-3471] Wrote upgrade log to '/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_trigger_logic_AXI_0_0/design_1_trigger_logic_AXI_0_0.upgrade_log'.
Wrote : </data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd>
upgrade_ip: Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 7961.340 ; gain = 0.000 ; free physical = 3344 ; free virtual = 21095
report_ip_status -name ip_status
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
Adding component instance block -- xilinx.com:ip:axi_ethernet_buffer:2.0 - eth_buf
Adding component instance block -- xilinx.com:ip:tri_mode_ethernet_mac:9.0 - eth_mac
Successfully read diagram <bd_0> from BD file </data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/bd_0.bd>
INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /axi_quad_spi_0
#######################################################################################
INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
########################################################################################
WARNING: [xilinx.com:ip:microblaze:9.5-14] /microblaze_0: The D-cache cacheable segment 0x80000000 - 0xBFFFFFFF does not include the M_AXI_DC segment 0xC0000000-0xC0000FFF, which prevents this M_AXI_DC segment from being accessed by the cache. To resolve this issue change user assigned parameters C_DCACHE_BASEADDR and C_DCACHE_HIGHADDR, or modify the address map.
WARNING: [xilinx.com:ip:microblaze:9.5-14] /microblaze_0: The I-cache cacheable segment 0x80000000 - 0xBFFFFFFF does not include the M_AXI_IC segment 0xC0000000-0xC0000FFF, which prevents this M_AXI_IC segment from being accessed by the cache. To resolve this issue change user assigned parameters C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR, or modify the address map.
INFO: [xilinx.com:ip:axi_intc:4.1-1] /microblaze_0_axi_intc: The AXI INTC core has been configured to operate with synchronous clocks.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_bram_porta_ADDR'(12) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addrb'(32) to net 'axi_bram_ctrl_0_bram_portb_ADDR'(12) - Only lower order bits will be connected.
VHDL Output written to : /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hdl/design_1.vhd
VHDL Output written to : /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
Wrote : </data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd>
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_microblaze_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_mig_7series_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_mig_7series_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block mig_7series_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_dlmb_v10_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/dlmb_v10 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_ilmb_v10_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/ilmb_v10 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_dlmb_bram_if_cntlr_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/dlmb_bram_if_cntlr .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_ilmb_bram_if_cntlr_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/ilmb_bram_if_cntlr .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_lmb_bram_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/lmb_bram .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_microblaze_0_axi_intc_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_axi_intc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_microblaze_0_xlconcat_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_xlconcat .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_mdm_1_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block mdm_1 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_proc_sys_reset_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_proc_sys_reset_1_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_1 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_timer_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_timer_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_uartlite_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_axi_uartlite_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_uartlite_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_bram_ctrl_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_bram_ctrl_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_blk_mem_gen_0_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_ethernet_0_0'...
VHDL Output written to : /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/hdl/bd_0.vhd
VHDL Output written to : /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/hdl/bd_0_wrapper.vhd
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_ethernet_0_0/bd_0/bd_0_eth_buf_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_axi_ethernet_0_0/bd_0/bd_0_eth_buf_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block eth_buf .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_ethernet_0_0/bd_0/bd_0_eth_mac_0'...
WARNING: [IP_Flow 19-650] IP license key 'eth_avb_endpoint@2015.04' is enabled with a Design_Linking license.
WARNING: [IP_Flow 19-650] IP license key 'eth_avb_endpoint@2015.04' is enabled with a Design_Linking license.
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_axi_ethernet_0_0/bd_0/bd_0_eth_mac_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block eth_mac .
INFO: [BD 41-1379] This design does not contain any processor.
Exporting to file /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/hw_handoff/design_1_axi_ethernet_0_0.hwh
Generated Block Design Tcl file /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/hw_handoff/design_1_axi_ethernet_0_0_bd.tcl
Generated Hardware Definition File /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/hdl/design_1_axi_ethernet_0_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ethernet_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_ethernet_0_dma_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ethernet_0_dma .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_clk_wiz_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_clk_wiz_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_xbar_1'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'design_1_xbar_1' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/xbar .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_xbar_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'design_1_xbar_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_axi_periph/xbar .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_trigger_logic_AXI_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_trigger_logic_AXI_0_0/c_counter_binary_3'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_trigger_logic_AXI_0_0/prescaler_counter_binary_3'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_trigger_logic_AXI_0_0/c_counter_binary_2'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_trigger_logic_AXI_0_0/c_counter_binary_1'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_trigger_logic_AXI_0_0/c_counter_binary_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_trigger_logic_AXI_0_0/blk_mem_gen_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block trigger_logic_AXI_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_rst_clk_wiz_0_401M_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_rst_clk_wiz_0_401M_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_clk_wiz_0_401M .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_rst_clk_wiz_0_125M_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_rst_clk_wiz_0_125M_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_clk_wiz_0_125M .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_real_time_clock_v1_0_S00_AXI_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_real_time_clock_v1_0_S00_AXI_0_0/real_time_1ms_from_125MHz_counter_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_real_time_clock_v1_0_S00_AXI_0_0/real_time_32b_counter_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block real_time_clock_v1_0_S00_AXI_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_quad_spi_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_axi_quad_spi_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_quad_spi_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_gpio_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_axi_gpio_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_s00_data_fifo_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'design_1_s00_data_fifo_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s00_couplers/s00_data_fifo .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_s01_data_fifo_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'design_1_s01_data_fifo_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s01_couplers/s01_data_fifo .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_s02_data_fifo_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'design_1_s02_data_fifo_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s02_couplers/s02_data_fifo .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_s03_data_fifo_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'design_1_s03_data_fifo_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s03_couplers/s03_data_fifo .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_s04_data_fifo_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'design_1_s04_data_fifo_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s04_couplers/s04_data_fifo .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_auto_cc_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'design_1_auto_cc_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_axi_periph/m05_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_auto_cc_1'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'design_1_auto_cc_1' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_axi_periph/m06_couplers/auto_cc .
Exporting to file /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Block Design Tcl file /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
Generated Hardware Definition File /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hdl/design_1.hwdef
Adding component instance block -- xilinx.com:ip:axi_ethernet_buffer:2.0 - eth_buf
Adding component instance block -- xilinx.com:ip:tri_mode_ethernet_mac:9.0 - eth_mac
Successfully read diagram <bd_0> from BD file </data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/bd_0.bd>
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_bram_porta_ADDR'(12) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addrb'(32) to net 'axi_bram_ctrl_0_bram_portb_ADDR'(12) - Only lower order bits will be connected.
VHDL Output written to : /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hdl/design_1.vhd
VHDL Output written to : /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
Wrote : </data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd>
INFO: [IP_Flow 19-1706] Not generating 'Synthesis' target for IP 'design_1_microblaze_0_0'. Target already exists and is up to date.
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0 .
INFO: [IP_Flow 19-1706] Not generating 'Synthesis' target for IP 'design_1_mig_7series_0_0'. Target already exists and is up to date.
INFO: [IP_Flow 19-1706] Not generating 'Implementation' target for IP 'design_1_mig_7series_0_0'. Target already exists and is up to date.
INFO: [IP_Flow 19-1706] Not generating 'Implementation' target for IP 'design_1_mig_7series_0_0'. Target already exists and is up to date.
INFO: [BD 41-1029] Generation completed for the IP Integrator block mig_7series_0 .
INFO: [IP_Flow 19-1706] Not generating 'Synthesis' target for IP 'design_1_dlmb_v10_0'. Target already exists and is up to date.
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/dlmb_v10 .
INFO: [IP_Flow 19-1706] Not generating 'Synthesis' target for IP 'design_1_ilmb_v10_1'. Target already exists and is up to date.
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/ilmb_v10 .