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vivado_3400.backup.log
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vivado_3400.backup.log
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#-----------------------------------------------------------
# Vivado v2015.2 (64-bit)
# SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
# Start of session at: Thu Sep 24 16:07:23 2015
# Process ID: 22817
# Log file: /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/vivado.log
# Journal file: /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/n/15/moore.1424/xillinx/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/xilinx/Vivado/2015.2/data/ip'.
open_project: Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 5900.539 ; gain = 100.449 ; free physical = 5158 ; free virtual = 30029
update_compile_order -fileset sources_1
set_property SOURCE_SET sources_1 [get_filesets sim_1]
add_files -fileset sim_1 -norecurse /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sim_1/new/tb_quinsident_unit.vhd
update_compile_order -fileset sim_1
set_property top trigger_logic_AXI [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trigger_logic_AXI' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj trigger_logic_AXI_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd" into library xbip_utils_v3_0
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0_vh_rfs.vhd" into library c_reg_fd_v12_0
INFO: [VRFC 10-307] analyzing entity c_reg_fd_v12_0_viv
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0.vhd" into library c_reg_fd_v12_0
INFO: [VRFC 10-307] analyzing entity c_reg_fd_v12_0
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" into library xbip_dsp48_wrapper_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_dsp48a_wrapper_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_dsp48a1_wrapper_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_dsp48e_wrapper_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_dsp48e1_wrapper_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_dsp48e2_wrapper_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_dsp48_wrapper_v3_0
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd" into library xbip_pipe_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_pipe_v3_0_viv
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd" into library xbip_pipe_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_pipe_v3_0
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" into library xbip_dsp48_addsub_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_dsp48_addsub_rtl
INFO: [VRFC 10-307] analyzing entity xbip_dsp48_addsub_synth
INFO: [VRFC 10-307] analyzing entity xbip_dsp48_addsub_v3_0_viv
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0.vhd" into library xbip_dsp48_addsub_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_dsp48_addsub_v3_0
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0_vh_rfs.vhd" into library xbip_addsub_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_addsub_v3_0_viv
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0.vhd" into library xbip_addsub_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_addsub_v3_0
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/c_addsub_v12_0/hdl/c_addsub_v12_0_vh_rfs.vhd" into library c_addsub_v12_0
INFO: [VRFC 10-307] analyzing entity c_addsub_v12_0_lut6_legacy
INFO: [VRFC 10-307] analyzing entity c_addsub_v12_0_base_legacy
INFO: [VRFC 10-307] analyzing entity c_addsub_v12_0_fabric_legacy
INFO: [VRFC 10-307] analyzing entity c_addsub_v12_0_legacy
INFO: [VRFC 10-307] analyzing entity c_addsub_v12_0_viv
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/c_addsub_v12_0/hdl/c_addsub_v12_0.vhd" into library c_addsub_v12_0
INFO: [VRFC 10-307] analyzing entity c_addsub_v12_0
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0_vh_rfs.vhd" into library c_gate_bit_v12_0
INFO: [VRFC 10-307] analyzing entity c_gate_bit_tile
INFO: [VRFC 10-307] analyzing entity c_gate_bit_tier
INFO: [VRFC 10-307] analyzing entity c_gate_bit_v12_0_viv
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0.vhd" into library c_gate_bit_v12_0
INFO: [VRFC 10-307] analyzing entity c_gate_bit_v12_0
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/xbip_counter_v3_0/hdl/xbip_counter_v3_0_vh_rfs.vhd" into library xbip_counter_v3_0
INFO: [VRFC 10-307] analyzing entity dsp48_counter
INFO: [VRFC 10-307] analyzing entity fabric_counter
INFO: [VRFC 10-307] analyzing entity xbip_counter_v3_0_viv
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/xbip_counter_v3_0/hdl/xbip_counter_v3_0.vhd" into library xbip_counter_v3_0
INFO: [VRFC 10-307] analyzing entity xbip_counter_v3_0
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0_vh_rfs.vhd" into library c_counter_binary_v12_0
INFO: [VRFC 10-307] analyzing entity c_counter_binary_v12_0_legacy
INFO: [VRFC 10-307] analyzing entity c_counter_binary_v12_0_viv
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0.vhd" into library c_counter_binary_v12_0
INFO: [VRFC 10-307] analyzing entity c_counter_binary_v12_0
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/c_counter_binary_0/sim/c_counter_binary_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity c_counter_binary_0
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_v8_2/simulation/blk_mem_gen_v8_2.vhd" into library blk_mem_gen_v8_2
INFO: [VRFC 10-307] analyzing entity blk_mem_axi_regs_fwd_v8_2
INFO: [VRFC 10-307] analyzing entity blk_mem_axi_write_wrapper_beh
INFO: [VRFC 10-307] analyzing entity write_netlist
INFO: [VRFC 10-307] analyzing entity blk_mem_axi_read_wrapper_beh
INFO: [VRFC 10-307] analyzing entity read_netlist
INFO: [VRFC 10-307] analyzing entity BLK_MEM_GEN_v8_2_output_stage
INFO: [VRFC 10-307] analyzing entity BLK_MEM_GEN_v8_2_softecc_output_reg_stage
INFO: [VRFC 10-307] analyzing entity BLK_MEM_GEN_v8_2_mem_module
INFO: [VRFC 10-307] analyzing entity blk_mem_gen_v8_2
INFO: [VRFC 10-307] analyzing entity beh_ff_clr
INFO: [VRFC 10-307] analyzing entity beh_ff_ce
INFO: [VRFC 10-307] analyzing entity beh_ff_pre
INFO: [VRFC 10-307] analyzing entity beh_muxf7
INFO: [VRFC 10-307] analyzing entity STATE_LOGIC
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/ip/blk_mem_gen_1/sim/blk_mem_gen_1.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity blk_mem_gen_1
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
ERROR: [VRFC 10-1081] near std_logic ; type conversion does not match type std_logic_vector [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd:75]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd:42]
INFO: [VRFC 10-240] VHDL file /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd ignored due to errors
INFO: [USF-XSim-99] Step results log file:'/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log' file for more information.
set_property top tb_quinsident_unit [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:75]
ERROR: [VRFC 10-1471] type error near q_int ; current type std_logic_vector; expected type std_logic [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:76]
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:90]
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:92]
ERROR: [VRFC 10-91] last_coincidence is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:89]
ERROR: [VRFC 10-2123] 0 definitions of operator "and" match here [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:89]
ERROR: [VRFC 10-91] last_coincidence is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:94]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:105]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:112]
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:109]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:126]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:129]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:107]
ERROR: [VRFC 10-91] delay_count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:149]
ERROR: [VRFC 10-91] delay_count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:156]
ERROR: [VRFC 10-91] delay_count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:153]
ERROR: [VRFC 10-1083] near std_logic_vector ; type conversion expression type cannot be determined uniquely [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:153]
ERROR: [VRFC 10-91] delay_count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:160]
ERROR: [VRFC 10-1081] near std_logic ; type conversion does not match type std_logic_vector [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:167]
INFO: [#UNDEF] Sorry, too many errors..
INFO: [USF-XSim-99] Step results log file:'/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:75]
ERROR: [VRFC 10-1471] type error near q_int ; current type std_logic_vector; expected type std_logic [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:76]
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:90]
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:92]
ERROR: [VRFC 10-91] last_coincidence is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:89]
ERROR: [VRFC 10-2123] 0 definitions of operator "and" match here [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:89]
ERROR: [VRFC 10-91] last_coincidence is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:94]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:105]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:112]
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:109]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:126]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:129]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:107]
ERROR: [VRFC 10-1466] type unsigned does not match with the integer literal [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:149]
ERROR: [VRFC 10-1466] type unsigned does not match with the integer literal [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:160]
ERROR: [VRFC 10-1081] near std_logic ; type conversion does not match type std_logic_vector [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:167]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:55]
INFO: [VRFC 10-240] VHDL file /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd ignored due to errors
INFO: [USF-XSim-99] Step results log file:'/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:75]
ERROR: [VRFC 10-1471] type error near q_int ; current type std_logic_vector; expected type std_logic [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:76]
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:90]
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:92]
ERROR: [VRFC 10-91] last_coincidence is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:89]
ERROR: [VRFC 10-2123] 0 definitions of operator "and" match here [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:89]
ERROR: [VRFC 10-91] last_coincidence is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:94]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:105]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:112]
ERROR: [VRFC 10-91] count is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:109]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:126]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:129]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:107]
ERROR: [VRFC 10-1081] near std_logic ; type conversion does not match type std_logic_vector [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:167]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:55]
INFO: [VRFC 10-240] VHDL file /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd ignored due to errors
INFO: [USF-XSim-99] Step results log file:'/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log' file for more information.
launch_runs impl_1 -jobs 2
[Thu Sep 24 16:33:54 2015] Launched synth_1...
Run output will be captured here: /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.runs/synth_1/runme.log
[Thu Sep 24 16:33:54 2015] Launched impl_1...
Run output will be captured here: /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.runs/impl_1/runme.log
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:107]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:114]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:128]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:131]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:109]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:55]
INFO: [VRFC 10-240] VHDL file /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd ignored due to errors
INFO: [USF-XSim-99] Step results log file:'/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:107]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:114]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:128]
ERROR: [VRFC 10-91] sate is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:131]
ERROR: [VRFC 10-91] ohers is not declared [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:129]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:55]
INFO: [VRFC 10-240] VHDL file /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd ignored due to errors
INFO: [USF-XSim-99] Step results log file:'/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sim_1/new/tb_quinsident_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity tb_quinsident_unit
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /opt/xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto 638767e3e26642c2841539cd8c14c5ac --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_quinsident_unit_behav xil_defaultlib.tb_quinsident_unit -log elaborate.log
Using 8 slave threads.
Starting static elaboration
ERROR: [VRFC 10-664] expression has 9 elements ; expected 10 [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sim_1/new/tb_quinsident_unit.vhd:89]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_quinsident_unit in library work failed.
INFO: [USF-XSim-99] Step results log file:'/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/elaborate.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sim_1/new/tb_quinsident_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity tb_quinsident_unit
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /opt/xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto 638767e3e26642c2841539cd8c14c5ac --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_quinsident_unit_behav xil_defaultlib.tb_quinsident_unit -log elaborate.log
Using 8 slave threads.
Starting static elaboration
ERROR: [VRFC 10-380] binding entity coincidence_unit does not have generic qn [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sim_1/new/tb_quinsident_unit.vhd:53]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_quinsident_unit in library work failed.
INFO: [USF-XSim-99] Step results log file:'/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/elaborate.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sim_1/new/tb_quinsident_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity tb_quinsident_unit
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /opt/xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto 638767e3e26642c2841539cd8c14c5ac --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_quinsident_unit_behav xil_defaultlib.tb_quinsident_unit -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xil_defaultlib.lib
Compiling architecture behavioral of entity xil_defaultlib.riseing_edge_persist [riseing_edge_persist_default]
Compiling architecture behavioral of entity xil_defaultlib.coincidence_unit [\coincidence_unit(10)\]
Compiling architecture behavioral of entity xil_defaultlib.tb_quinsident_unit
Built simulation snapshot tb_quinsident_unit_behav
****** Webtalk v2015.2 (64-bit)
**** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
**** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xsim.dir/tb_quinsident_unit_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xsim.dir/tb_quinsident_unit_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Thu Sep 24 16:43:17 2015. For additional details about this file, please refer to the WebTalk help file at /opt/xilinx/Vivado/2015.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Thu Sep 24 16:43:17 2015...
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 5943.699 ; gain = 0.000 ; free physical = 3965 ; free virtual = 29935
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_quinsident_unit_behav -key {Behavioral:sim_1:Functional:tb_quinsident_unit} -tclbatch {tb_quinsident_unit.tcl} -view {/n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.2
Time resolution is 1 ps
open_wave_config /n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg
WARNING: Simulation object /tb_handshake_unit/clk was not found in the design.
WARNING: Simulation object /tb_handshake_unit/reset was not found in the design.
WARNING: Simulation object /tb_handshake_unit/busy_in was not found in the design.
WARNING: Simulation object /tb_handshake_unit/mask was not found in the design.
WARNING: Simulation object /tb_handshake_unit/delay was not found in the design.
WARNING: Simulation object /tb_handshake_unit/sig_in was not found in the design.
WARNING: Simulation object /tb_handshake_unit/sig_out was not found in the design.
WARNING: Simulation object /tb_handshake_unit/uut/state was not found in the design.
WARNING: Simulation object /tb_handshake_unit/uut/b was not found in the design.
WARNING: Simulation object /tb_handshake_unit/uut/delay_done was not found in the design.
WARNING: Simulation object /tb_handshake_unit/uut/c0/L was not found in the design.
WARNING: Simulation object /tb_handshake_unit/uut/c0/Q was not found in the design.
WARNING: Simulation object /tb_handshake_unit/uut/c0/LOAD was not found in the design.
WARNING: Simulation object /tb_handshake_unit/uut/c0/THRESH0 was not found in the design.
WARNING: Simulation object /tb_handshake_unit/uut/veto was not found in the design.
source tb_quinsident_unit.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_quinsident_unit_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 5995.199 ; gain = 51.500 ; free physical = 3940 ; free virtual = 29918
run 10 us
restart
INFO: [Simtcl 6-17] Simulation restarted
run 10 us
restart
INFO: [Simtcl 6-17] Simulation restarted
run 10 us
restart
INFO: [Simtcl 6-17] Simulation restarted
run 1 us
save_wave_config {/n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sim_1/new/tb_quinsident_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity tb_quinsident_unit
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /opt/xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto 638767e3e26642c2841539cd8c14c5ac --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_quinsident_unit_behav xil_defaultlib.tb_quinsident_unit -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xil_defaultlib.lib
Compiling architecture behavioral of entity xil_defaultlib.riseing_edge_persist [riseing_edge_persist_default]
Compiling architecture behavioral of entity xil_defaultlib.coincidence_unit [\coincidence_unit(10)\]
Compiling architecture behavioral of entity xil_defaultlib.tb_quinsident_unit
Built simulation snapshot tb_quinsident_unit_behav
****** Webtalk v2015.2 (64-bit)
**** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
**** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xsim.dir/tb_quinsident_unit_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xsim.dir/tb_quinsident_unit_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Thu Sep 24 16:52:51 2015. For additional details about this file, please refer to the WebTalk help file at /opt/xilinx/Vivado/2015.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Thu Sep 24 16:52:51 2015...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_quinsident_unit_behav -key {Behavioral:sim_1:Functional:tb_quinsident_unit} -tclbatch {tb_quinsident_unit.tcl} -view {/n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.2
Time resolution is 1 ps
open_wave_config /n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg
source tb_quinsident_unit.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_quinsident_unit_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 5998.199 ; gain = 0.000 ; free physical = 3794 ; free virtual = 30543
add_wave {{/tb_quinsident_unit/uut/Q_int}}
restart
INFO: [Simtcl 6-17] Simulation restarted
run 1 us
restart
INFO: [Simtcl 6-17] Simulation restarted
run 1 us
restart
INFO: [Simtcl 6-17] Simulation restarted
run 1 us
restart
INFO: [Simtcl 6-17] Simulation restarted
run 1 us
restart
INFO: [Simtcl 6-17] Simulation restarted
run .31 us
save_wave_config {/n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
ERROR: [VRFC 10-1412] syntax error near then10 [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:149]
ERROR: [VRFC 10-1412] syntax error near if [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:167]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:55]
INFO: [VRFC 10-240] VHDL file /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd ignored due to errors
INFO: [USF-XSim-99] Step results log file:'/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xvhdl.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sim_1/new/tb_quinsident_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity tb_quinsident_unit
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /opt/xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto 638767e3e26642c2841539cd8c14c5ac --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_quinsident_unit_behav xil_defaultlib.tb_quinsident_unit -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xil_defaultlib.lib
Compiling architecture behavioral of entity xil_defaultlib.riseing_edge_persist [riseing_edge_persist_default]
Compiling architecture behavioral of entity xil_defaultlib.coincidence_unit [\coincidence_unit(10)\]
Compiling architecture behavioral of entity xil_defaultlib.tb_quinsident_unit
Built simulation snapshot tb_quinsident_unit_behav
****** Webtalk v2015.2 (64-bit)
**** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
**** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xsim.dir/tb_quinsident_unit_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xsim.dir/tb_quinsident_unit_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Thu Sep 24 17:11:22 2015. For additional details about this file, please refer to the WebTalk help file at /opt/xilinx/Vivado/2015.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Thu Sep 24 17:11:22 2015...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_quinsident_unit_behav -key {Behavioral:sim_1:Functional:tb_quinsident_unit} -tclbatch {tb_quinsident_unit.tcl} -view {/n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.2
Time resolution is 1 ps
open_wave_config /n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg
source tb_quinsident_unit.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_quinsident_unit_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 5998.199 ; gain = 0.000 ; free physical = 3264 ; free virtual = 30525
save_wave_config {/n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sim_1/new/tb_quinsident_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity tb_quinsident_unit
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /opt/xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto 638767e3e26642c2841539cd8c14c5ac --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_quinsident_unit_behav xil_defaultlib.tb_quinsident_unit -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xil_defaultlib.lib
Compiling architecture behavioral of entity xil_defaultlib.riseing_edge_persist [riseing_edge_persist_default]
Compiling architecture behavioral of entity xil_defaultlib.coincidence_unit [\coincidence_unit(10)\]
Compiling architecture behavioral of entity xil_defaultlib.tb_quinsident_unit
Built simulation snapshot tb_quinsident_unit_behav
****** Webtalk v2015.2 (64-bit)
**** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
**** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xsim.dir/tb_quinsident_unit_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xsim.dir/tb_quinsident_unit_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Thu Sep 24 17:16:54 2015. For additional details about this file, please refer to the WebTalk help file at /opt/xilinx/Vivado/2015.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Thu Sep 24 17:16:54 2015...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_quinsident_unit_behav -key {Behavioral:sim_1:Functional:tb_quinsident_unit} -tclbatch {tb_quinsident_unit.tcl} -view {/n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.2
Time resolution is 1 ps
open_wave_config /n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg
source tb_quinsident_unit.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_quinsident_unit_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 5998.199 ; gain = 0.000 ; free physical = 3265 ; free virtual = 30527
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_quinsident_unit' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
xvhdl -m64 --relax -prj tb_quinsident_unit_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity riseing_edge_persist
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity coincidence_unit
INFO: [VRFC 10-163] Analyzing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sim_1/new/tb_quinsident_unit.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity tb_quinsident_unit
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /opt/xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto 638767e3e26642c2841539cd8c14c5ac --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_quinsident_unit_behav xil_defaultlib.tb_quinsident_unit -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xil_defaultlib.lib
Compiling architecture behavioral of entity xil_defaultlib.riseing_edge_persist [riseing_edge_persist_default]
Compiling architecture behavioral of entity xil_defaultlib.coincidence_unit [\coincidence_unit(10)\]
Compiling architecture behavioral of entity xil_defaultlib.tb_quinsident_unit
Built simulation snapshot tb_quinsident_unit_behav
****** Webtalk v2015.2 (64-bit)
**** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
**** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xsim.dir/tb_quinsident_unit_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav/xsim.dir/tb_quinsident_unit_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Thu Sep 24 17:18:42 2015. For additional details about this file, please refer to the WebTalk help file at /opt/xilinx/Vivado/2015.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Thu Sep 24 17:18:42 2015...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_quinsident_unit_behav -key {Behavioral:sim_1:Functional:tb_quinsident_unit} -tclbatch {tb_quinsident_unit.tcl} -view {/n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.2
Time resolution is 1 ps
open_wave_config /n/15/moore.1424/xillinx/trigger_logic_axi_io/tb_handshake_unit_behav.wcfg
source tb_quinsident_unit.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_quinsident_unit_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 5998.199 ; gain = 0.000 ; free physical = 3263 ; free virtual = 30524
close_sim
INFO: [Simtcl 6-16] Simulation closed
reset_run synth_1
launch_runs synth_1 -jobs 2
INFO: [HDL 9-2216] Analyzing Verilog file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/all_input_delays.v" into library work [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/all_input_delays.v:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/add_module.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/add_module.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/addressable_shift_reg.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/addressable_shift_reg.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/beam_current_monitor.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/beam_current_monitor.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/coincidence_unit.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/edge_detector.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/edge_detector.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/handshake_unit.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/handshake_unit.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/new/lib.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/n_bit_counter.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/n_bit_counter.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/one_ch_delay.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/one_ch_delay.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/pulse_gen.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/pulse_gen.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/riseing_edge_persist.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/serial_in_parallel_out_shift_register.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/serial_in_parallel_out_shift_register.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_backend.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_backend.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_frontend.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/tlu_frontend.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/trigger_logic_axi.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/new/trigger_logic_axi.vhd:1]
INFO: [HDL 9-1061] Parsing VHDL file "/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/varable_delays.vhd" into library xil_defaultlib [/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.srcs/sources_1/imports/moore.1424/xillinx/trigger_logic_ac701/trigger_logic_ac701.srcs/sources_1/new/varable_delays.vhd:1]
[Thu Sep 24 17:22:06 2015] Launched synth_1...
Run output will be captured here: /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.runs/synth_1/runme.log
reset_run synth_1
launch_runs impl_1 -jobs 2
[Thu Sep 24 18:14:32 2015] Launched synth_1...
Run output will be captured here: /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.runs/synth_1/runme.log
[Thu Sep 24 18:14:32 2015] Launched impl_1...
Run output will be captured here: /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1 -jobs 2
[Thu Sep 24 18:16:03 2015] Launched synth_1...
Run output will be captured here: /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.runs/synth_1/runme.log
[Thu Sep 24 18:16:03 2015] Launched impl_1...
Run output will be captured here: /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.runs/impl_1/runme.log
launch_runs impl_1 -to_step write_bitstream -jobs 2
[Thu Sep 24 18:34:51 2015] Launched impl_1...
Run output will be captured here: /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.runs/impl_1/runme.log
reset_run impl_1 -prev_step
close_project
****** Webtalk v2015.2 (64-bit)
**** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
**** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source /n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.hw/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] '/n/15/moore.1424/xillinx/trigger_logic_axi_io/trigger_logic_axi_io.hw/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Thu Sep 24 18:35:27 2015. For additional details about this file, please refer to the WebTalk help file at /opt/xilinx/Vivado/2015.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Thu Sep 24 18:35:27 2015...
open_project /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/n/15/moore.1424/xillinx/trigger_logic_axi_io'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/xilinx/Vivado/2015.2/data/ip'.
WARNING: [BD 41-1661] One or more IPs have been locked in the design 'design_1.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
design_1_trigger_logic_AXI_0_0
open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 6083.992 ; gain = 85.672 ; free physical = 3109 ; free virtual = 30380
open_bd_design {/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd}
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.0 - axi_bram_ctrl_0
Adding component instance block -- xilinx.com:ip:axi_ethernet:7.0 - axi_ethernet_0
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_ethernet_0_dma
Adding component instance block -- xilinx.com:ip:axi_timer:2.0 - axi_timer_0
Adding component instance block -- xilinx.com:ip:axi_uartlite:2.0 - axi_uartlite_0
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.2 - blk_mem_gen_0
Adding component instance block -- xilinx.com:ip:clk_wiz:5.1 - clk_wiz_0
Adding component instance block -- xilinx.com:ip:mdm:3.2 - mdm_1
Adding component instance block -- xilinx.com:ip:microblaze:9.5 - microblaze_0
Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - microblaze_0_axi_intc
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - microblaze_0_xlconcat
Adding component instance block -- xilinx.com:ip:mig_7series:2.3 - mig_7series_0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_1
Adding component instance block -- user.org:user:trigger_logic_AXI:1.0 - trigger_logic_AXI_0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_clk_wiz_0_401M
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_data_fifo:2.1 - s04_data_fifo
Adding component instance block -- xilinx.com:ip:axi_data_fifo:2.1 - s03_data_fifo
Adding component instance block -- xilinx.com:ip:axi_data_fifo:2.1 - s02_data_fifo
Adding component instance block -- xilinx.com:ip:axi_data_fifo:2.1 - s01_data_fifo
Adding component instance block -- xilinx.com:ip:axi_data_fifo:2.1 - s00_data_fifo
Adding component instance block -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - dlmb_bram_if_cntlr
Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - dlmb_v10
Adding component instance block -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - ilmb_bram_if_cntlr
Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - ilmb_v10
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.2 - lmb_bram
Successfully read diagram <design_1> from BD file </data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd>
open_bd_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 6138.738 ; gain = 46.328 ; free physical = 3061 ; free virtual = 30332
report_ip_status -name ip_status
upgrade_ip [get_ips {design_1_trigger_logic_AXI_0_0 blk_mem_gen_1}]
Upgrading '/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd'
INFO: [IP_Flow 19-1972] Upgraded design_1_trigger_logic_AXI_0_0 from trigger_logic_AXI_v1_0 1.0 to trigger_logic_AXI_v1_0 1.0
INFO: [IP_Flow 19-3471] Wrote upgrade log to '/data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_trigger_logic_AXI_0_0/design_1_trigger_logic_AXI_0_0.upgrade_log'.
Wrote : </data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd>
upgrade_ip: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 6178.984 ; gain = 13.387 ; free physical = 3078 ; free virtual = 30302
report_ip_status -name ip_status
INFO: [Vivado 12-4158] Exported Hardware file is out of date. Exported hardware information may be inconsistent with respect to the current state of the design. It is recommended that you re-export the design and launch SDK otherwise SDK is launched with out of date hardware system file.
generate_target all [get_files /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd]
Adding component instance block -- xilinx.com:ip:axi_ethernet_buffer:2.0 - eth_buf
Adding component instance block -- xilinx.com:ip:tri_mode_ethernet_mac:9.0 - eth_mac
Successfully read diagram <bd_0> from BD file </data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/bd_0.bd>
INFO: [xilinx.com:ip:axi_intc:4.1-1] /microblaze_0_axi_intc: The AXI INTC core has been configured to operate with synchronous clocks.
WARNING: [xilinx.com:ip:microblaze:9.5-14] /microblaze_0: The D-cache cacheable segment 0x80000000 - 0xBFFFFFFF does not include the M_AXI_DC segment 0xC0000000-0xC0000FFF, which prevents this M_AXI_DC segment from being accessed by the cache. To resolve this issue change user assigned parameters C_DCACHE_BASEADDR and C_DCACHE_HIGHADDR, or modify the address map.
WARNING: [xilinx.com:ip:microblaze:9.5-14] /microblaze_0: The I-cache cacheable segment 0x80000000 - 0xBFFFFFFF does not include the M_AXI_IC segment 0xC0000000-0xC0000FFF, which prevents this M_AXI_IC segment from being accessed by the cache. To resolve this issue change user assigned parameters C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR, or modify the address map.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_bram_porta_ADDR'(12) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addrb'(32) to net 'axi_bram_ctrl_0_bram_portb_ADDR'(12) - Only lower order bits will be connected.
Verilog Output written to : /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hdl/design_1.v
Verilog Output written to : /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
Wrote : </data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/design_1.bd>
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_microblaze_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_microblaze_0_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_microblaze_0_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_microblaze_0_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_microblaze_0_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'design_1_microblaze_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_microblaze_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_mig_7series_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_mig_7series_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_mig_7series_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_mig_7series_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_mig_7series_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block mig_7series_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_dlmb_v10_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_dlmb_v10_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_dlmb_v10_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_dlmb_v10_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_dlmb_v10_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_dlmb_v10_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/dlmb_v10 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_ilmb_v10_1'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_ilmb_v10_1'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_ilmb_v10_1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_ilmb_v10_1'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_ilmb_v10_1' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_ilmb_v10_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/ilmb_v10 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_dlmb_bram_if_cntlr_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_dlmb_bram_if_cntlr_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_dlmb_bram_if_cntlr_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_dlmb_bram_if_cntlr_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_dlmb_bram_if_cntlr_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_dlmb_bram_if_cntlr_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/dlmb_bram_if_cntlr .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_ilmb_bram_if_cntlr_1'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_ilmb_bram_if_cntlr_1'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_ilmb_bram_if_cntlr_1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_ilmb_bram_if_cntlr_1'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_ilmb_bram_if_cntlr_1' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_ilmb_bram_if_cntlr_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/ilmb_bram_if_cntlr .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_lmb_bram_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_lmb_bram_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_lmb_bram_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_lmb_bram_0'...
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'design_1_lmb_bram_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_lmb_bram_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_local_memory/lmb_bram .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_microblaze_0_axi_intc_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_microblaze_0_axi_intc_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_microblaze_0_axi_intc_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_microblaze_0_axi_intc_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_microblaze_0_axi_intc_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_microblaze_0_axi_intc_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_axi_intc .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_microblaze_0_xlconcat_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_microblaze_0_xlconcat_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_microblaze_0_xlconcat_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_microblaze_0_xlconcat_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_xlconcat .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_mdm_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_mdm_1_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_mdm_1_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_mdm_1_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_mdm_1_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_mdm_1_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block mdm_1 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_proc_sys_reset_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_proc_sys_reset_1_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_proc_sys_reset_1_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_proc_sys_reset_1_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_proc_sys_reset_1_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_proc_sys_reset_1_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_proc_sys_reset_1_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_1 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_axi_timer_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_timer_0_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_axi_timer_0_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_axi_timer_0_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_axi_timer_0_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_axi_timer_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_timer_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_axi_uartlite_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_uartlite_0_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_axi_uartlite_0_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_axi_uartlite_0_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_axi_uartlite_0_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_axi_uartlite_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_axi_uartlite_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_uartlite_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_axi_bram_ctrl_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_bram_ctrl_0_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_axi_bram_ctrl_0_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_axi_bram_ctrl_0_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_axi_bram_ctrl_0_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_axi_bram_ctrl_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_bram_ctrl_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_blk_mem_gen_0_1'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_blk_mem_gen_0_1'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_blk_mem_gen_0_1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_blk_mem_gen_0_1'...
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'design_1_blk_mem_gen_0_1'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_blk_mem_gen_0_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_axi_ethernet_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_ethernet_0_0'...
INFO: [Device 21-403] Loading part xc7a200tfbg676-2
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_axi_ethernet_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_axi_ethernet_0_0'...
Verilog Output written to : /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/hdl/bd_0.v
Verilog Output written to : /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/hdl/bd_0_wrapper.v
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_ethernet_0_0/bd_0/bd_0_eth_buf_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'bd_0_eth_buf_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_axi_ethernet_0_0/bd_0/bd_0_eth_buf_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'bd_0_eth_buf_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_axi_ethernet_0_0/bd_0/bd_0_eth_buf_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block eth_buf .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_ethernet_0_0/bd_0/bd_0_eth_mac_0'...
WARNING: [IP_Flow 19-650] IP license key 'eth_avb_endpoint@2015.04' is enabled with a Hardware_Evaluation license.
WARNING: [IP_Flow 19-650] IP license key 'eth_avb_endpoint@2015.04' is enabled with a Hardware_Evaluation license.
WARNING: [IP_Flow 19-650] IP license key 'tri_mode_eth_mac@2015.04' is enabled with a Hardware_Evaluation license.
WARNING: [IP_Flow 19-650] IP license key 'tri_mode_eth_mac@2015.04' is enabled with a Hardware_Evaluation license.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_axi_ethernet_0_0/bd_0/bd_0_eth_mac_0'...
WARNING: [IP_Flow 19-650] IP license key 'eth_avb_endpoint@2015.04' is enabled with a Hardware_Evaluation license.
WARNING: [IP_Flow 19-650] IP license key 'eth_avb_endpoint@2015.04' is enabled with a Hardware_Evaluation license.
WARNING: [IP_Flow 19-650] IP license key 'tri_mode_eth_mac@2015.04' is enabled with a Hardware_Evaluation license.
WARNING: [IP_Flow 19-650] IP license key 'tri_mode_eth_mac@2015.04' is enabled with a Hardware_Evaluation license.
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_axi_ethernet_0_0/bd_0/bd_0_eth_mac_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block eth_mac .
INFO: [BD 41-1379] This design does not contain any processor.
Exporting to file /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/hw_handoff/design_1_axi_ethernet_0_0.hwh
Generated Block Design Tcl file /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/hw_handoff/design_1_axi_ethernet_0_0_bd.tcl
Generated Hardware Definition File /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/hdl/design_1_axi_ethernet_0_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ethernet_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_axi_ethernet_0_dma_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_axi_ethernet_0_dma_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_axi_ethernet_0_dma_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_axi_ethernet_0_dma_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_axi_ethernet_0_dma_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_axi_ethernet_0_dma_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ethernet_0_dma .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_clk_wiz_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_clk_wiz_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_clk_wiz_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'design_1_clk_wiz_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_clk_wiz_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_xbar_1'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_xbar_1'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_xbar_1'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_xbar_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/xbar .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_xbar_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_xbar_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_xbar_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_xbar_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_axi_periph/xbar .
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_trigger_logic_AXI_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_trigger_logic_AXI_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_trigger_logic_AXI_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Test Bench' target for IP 'design_1_trigger_logic_AXI_0_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_trigger_logic_AXI_0_0/c_counter_binary_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_trigger_logic_AXI_0_0/c_counter_binary_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_trigger_logic_AXI_0_0/blk_mem_gen_1'...
INFO: [Common 17-14] Message 'IP_Flow 19-1686' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [BD 41-1029] Generation completed for the IP Integrator block trigger_logic_AXI_0 .
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_rst_clk_wiz_0_401M_0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'design_1_rst_clk_wiz_0_401M_0' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_clk_wiz_0_401M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s00_couplers/s00_data_fifo .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s01_couplers/s01_data_fifo .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s02_couplers/s02_data_fifo .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s03_couplers/s03_data_fifo .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s04_couplers/s04_data_fifo .
INFO: [BD 41-1029] Generation completed for the IP Integrator block microblaze_0_axi_periph/m05_couplers/auto_cc .
Exporting to file /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Block Design Tcl file /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
Generated Hardware Definition File /data1/jmoore/XAPP1026/AC701_AxiEth_100Mhz_64kb/HW/project_1.srcs/sources_1/bd/design_1/hdl/design_1.hwdef