ccimx8x-sbc-express.dtsi

/*
 * Copyright 2018, Digi International Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/ {
	model = "Digi International ConnectCore 8X SBC Express.";
	compatible = "digi,ccimx8x-sbc-express", "digi,ccimx8x", "fsl,imx8qxp";
	digi,machine,name = "ccimx8x-sbc-express";

	chosen {
		bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
		stdout-path = &lpuart2;
	};

	lvds_backlight0: lvds_backlight@0 {
		compatible = "pwm-backlight";
		pwms = <&pwm_mipi_lvds0 0 100000 0>;

		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <80>;
		status = "disabled";
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_3v3_eth0: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "3v3_eth0";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			startup-delay-us = <25000>;
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>, <&pinctrl_fec1_gpio>;
	clocks = <&clk IMX8QXP_ENET0_IPG_CLK>,
		 <&clk IMX8QXP_ENET0_AHB_CLK>,
		 <&clk IMX8QXP_ENET0_REF_50MHZ_CLK>,
		 <&clk IMX8QXP_ENET0_PTP_CLK>,
		 <&clk IMX8QXP_ENET0_TX_CLK>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	phy-supply = <&reg_3v3_eth0>;
	phy-reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;
	fsl,magic-packet;
	status = "disabled";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			smsc,disable-energy-detect;
			reg = <0>;
		};
	};
};

&fec2 {
	status = "disabled";
};

/*
 * CAN0 port conflicts with LPUART0 RTS/CTS lines.
 * Before enabling the port you need to configure
 * lpuart0 node as 2 wires.
 */
&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_3v3>;
	status = "disabled";
};

/* CAN1 */
&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_3v3>;
	status = "disabled";
};

/* CAN2 */
&flexcan3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan3>;
	xceiver-supply = <&reg_3v3>;
	status = "disabled";
};

/* I2C2 available on Raspberry Pi expansion header */
&i2c2 {
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&clk IMX8QXP_I2C2_CLK>,
		 <&clk IMX8QXP_I2C2_IPG_CLK>;
	clock-names = "per", "ipg";
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_lpi2c2>;
	pinctrl-1 = <&pinctrl_lpi2c2_gpio>;
	scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
	status = "disabled";
};

/* I2C3 available on Raspberry Pi expansion header */
&i2c3 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c3>;
	status = "disabled";
};

/* MIPI-DSI0 I2C available on LVDS connector */
&i2c0_mipi_lvds0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
	pinctrl-1 = <&pinctrl_i2c0_lvds0_gpio>;
	scl-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
	clock-frequency = <100000>;
	status = "disabled";

	/*
	 * On the CC8X SBC, an inconsistent reset sequence makes
	 * the Goodix display's touch controller respond to two I2C
	 * addresses: 0x14 and 0x5D. To make sure the touchscreen
	 * works every time, the touch controller's description must
	 * be duplicated for both addresses.
	 */
	goodix_touch1: gt9271@14 {
		compatible = "goodix,gt9271";
		reg = <0x14>;
		/* Interrupt for LVDS0 */
		interrupt-parent = <&gpio4>;
		interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
		irq-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
		reload-fw-on-resume;
		skip-firmware-request;
		status = "disabled";
	};

	goodix_touch2: gt9271@5D {
		compatible = "goodix,gt9271";
		reg = <0x5D>;
		/* Interrupt for LVDS0 */
		interrupt-parent = <&gpio4>;
		interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
		irq-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
		reload-fw-on-resume;
		skip-firmware-request;
		status = "disabled";
	};
};

&ldb1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lvds0>;
	status = "disabled";

	lvds0: lvds-channel@0 {
		fsl,data-mapping = "jeida";
		fsl,data-width = <24>;
		digi,bits-per-pixel = <16>;
		status = "disabled";

		display-timings {
			native-mode = <&g101evn010_1>;

			/* AUO G101EVN01.0 */
			g101evn010_1: timing@0 {
				clock-frequency = <68930000>;
				hactive = <1280>;
				vactive = <800>;
				hfront-porch = <120>;
				hback-porch = <0>;
				hsync-len = <8>;
				vback-porch = <10>;
				vfront-porch = <0>;
				vsync-len = <6>;
				hsync-active = <1>;
				vsync-active = <1>;
				de-active = <1>;
				pixelclk-active = <0>;
			};

			/* Fusion 10" F10A-0102 */
			hsd101pfw2_1: timing@1 {
				clock-frequency = <45000000>;
				hactive = <1024>;
				vactive = <600>;
				hfront-porch = <0>;
				hback-porch = <0>;
				hsync-len = <176>;
				vback-porch = <0>;
				vfront-porch = <2>;
				vsync-len = <23>;
			};
		};
	};
};

&ldb1_phy {
	status = "disabled";
};

/* LPSPI3 on Raspberry Pi expansion header */
&lpspi3 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi3>;
	status = "disabled";
};

/* LPUART0 on XBee socket */
&lpuart0 {
	/* RTS/CTS lines multiplexed with CAN0 */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0_4wires>, <&pinctrl_xbee_gpios>;
	status = "disabled";
};

/* Console */
&lpuart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
	status = "disabled";
};

/* LPUART3 on expansion header */
&lpuart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>;
	status = "disabled";
};

&pd_dma_lpuart2 {
	debug_console;
};

&pixel_combiner {
	status = "okay";
};

&prg1 {
	status = "okay";
};

&prg2 {
	status = "okay";
};

&prg3 {
	status = "okay";
};

&prg4 {
	status = "okay";
};

&prg5 {
	status = "okay";
};

&prg6 {
	status = "okay";
};

&prg7 {
	status = "okay";
};

&prg8 {
	status = "okay";
};

&prg9 {
	status = "okay";
};

/* USB_OTG1 */
&usbotg1 {
	/*
	 * To configure this USB controller as a device set dr_mode to "otg";
	 * to configure it as a host set to "host" instead.
	 */
	dr_mode = "host";
	disable-over-current;
	status = "disabled";
};

/* USB_OTG2 */
&usbotg3 {
	dr_mode = "host";
	disable-over-current;
	status = "disabled";
};

/* Micro SD card */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	no-1-8-v;
	cd-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
	status = "disabled";
};

/* IOMUX */
&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			/* User LED */
			SC_P_MCLK_IN0_LSIO_GPIO0_IO19	0x06000020
			/* User button */
			SC_P_MCLK_OUT0_LSIO_GPIO0_IO20	0x06000020
		>;
	};

	pinctrl_lpspi3: lpspi3grp {
		fsl,pins = <
			SC_P_SPI3_SCK_ADMA_SPI3_SCK	0x0600004c
			SC_P_SPI3_SDO_ADMA_SPI3_SDO	0x0600004c
			SC_P_SPI3_SDI_ADMA_SPI3_SDI	0x0600004c
			SC_P_SPI3_CS0_ADMA_SPI3_CS0	0x0600004c
		>;
	};

	pinctrl_lpuart0_2wires: lpuart0grp_2wires {
		fsl,pins = <
			SC_P_UART0_RX_ADMA_UART0_RX		0x06000020
			SC_P_UART0_TX_ADMA_UART0_TX		0x06000020
		>;
	};

	pinctrl_lpuart0_4wires: lpuart0grp_4wires {
		fsl,pins = <
			SC_P_UART0_RX_ADMA_UART0_RX		0x06000020
			SC_P_UART0_TX_ADMA_UART0_TX		0x06000020
			SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B	0x06000020
			SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B	0x06000020
		>;
	};

	pinctrl_lpuart2: lpuart2grp {
		fsl,pins = <
			SC_P_UART2_TX_ADMA_UART2_TX	0x06000020
			SC_P_UART2_RX_ADMA_UART2_RX	0x06000020
		>;
	};

	pinctrl_lpuart3: lpuart3grp {
		fsl,pins = <
			SC_P_SCU_GPIO0_01_ADMA_UART3_TX	0x06000020
			SC_P_SCU_GPIO0_00_ADMA_UART3_RX	0x06000020
		>;
	};

	pinctrl_lvds0: lvds0grp {
		fsl,pins = <
			/* LVDS0 touch interrupt */
			SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x06000020
			/* LVDS0 PWM backlight */
			SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT	0x00000020
		>;
	};

	pinctrl_fec1_gpio: fec1gpiogrp {
		fsl,pins = <
			/* PHY reset */
			SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
			/* PHY power */
			SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08	0x06000021
			/* PHY interrupt */
			SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02	0x06000021
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			/*
			 * The SCFW of B0 defaults ENET0 domains to 2.5V:
			 * - VDD_ENET0_1P8_2P5_3P3
			 * - VDD_ENET0_VSELECT_1P8_2P5_3P3
			 * Turn the domains back to 1.8/3.3V detector
			 */
			SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
			SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0

			/* Pad settings for ENET RMII */
			SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
			SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
			SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
			SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000020
			SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
			SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
			SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
			SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
			SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
			SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x06000048
		>;
	};

	pinctrl_flexcan1: flexcan0grp {
		fsl,pins = <
			SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX		0x21
			SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX		0x21
		>;
	};

	pinctrl_flexcan2: flexcan1grp {
		fsl,pins = <
			SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX		0x21
			SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX		0x21
		>;
	};

	pinctrl_flexcan3: flexcan2grp {
		fsl,pins = <
			SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX		0x21
			SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX		0x21
		>;
	};

	pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
		fsl,pins = <
			SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
			SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
		>;
	};

	pinctrl_i2c0_lvds0_gpio: lvds0_i2c0_gpio_grp {
		fsl,pins = <
			SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 0xc6000020
			SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 0xc6000020
		>;
	};

	pinctrl_lpi2c2: lpi2c2grp {
		fsl,pins = <
			SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL	0xc6000020
			SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA	0xc6000020
		>;
	};

	pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {
		fsl,pins = <
			SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31	0xc6000020
			SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00	0xc6000020
		>;
	};

	pinctrl_lpi2c3: lpi2c3grp {
		fsl,pins = <
			SC_P_SPI3_CS1_ADMA_I2C3_SCL	0x06000020
			SC_P_MCLK_IN1_ADMA_I2C3_SDA	0x06000020
		>;
	};

	pinctrl_pcieb: pcieagrp{
		fsl,pins = <
			SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000021
			SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x06000021
			SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000021
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			/* Card detect */
			SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000021
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
			SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
			SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
			SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
			SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
			SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
		fsl,pins = <
			SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
			SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
			SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
			SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
			SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
			SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
		fsl,pins = <
			SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
			SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
			SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
			SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
			SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
			SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
		>;
	};

	pinctrl_xbee_gpios: xbeegrp {
		fsl,pins = <
			/* XBEE_RESET_N */
			SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13		0x06000021
			/* XBEE_ON/SLEEP_N */
			SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14	0x06000021
			/* XBEE_SLEEP_RQ */
			SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16	0x06000021
		>;
	};
};