/
imx6q-ccimx6sbc.dtsi
163 lines (146 loc) · 4.27 KB
/
imx6q-ccimx6sbc.dtsi
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
/*
* Copyright 2014-2018 Digi International, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/* ConnectCore 6 SBC (common) */
#include "imx6qdl-ccimx6sbc.dtsi"
/ {
model = "Digi International ConnectCore 6 Single Board Computer.";
compatible = "digi,ccimx6sbc", "digi,ccimx6", "fsl,imx6q";
digi,machine,name = "ccimx6sbc";
aliases {
mxcfb0 = &mxcfb1;
mxcfb1 = &mxcfb2;
mxcfb2 = &mxcfb3;
mxcfb3 = &mxcfb4;
};
mxcfb3: fb@2 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "lcd";
interface_pix_fmt = "RGB666";
mode_str ="FUSION7";
default_bpp = <16>;
int_clk = <0>;
late_init = <0>;
status = "disabled";
};
mxcfb4: fb@3 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "ldb";
interface_pix_fmt = "RGB666";
default_bpp = <16>;
int_clk = <0>;
late_init = <0>;
status = "disabled";
};
};
&ldb {
lvds-channel@0 {
crtc = "ipu2-di0";
primary;
};
lvds-channel@1 {
crtc = "ipu2-di1";
};
};
&mipi_dsi {
dev_id = <0>;
disp_id = <0>;
};
&i2c3 {
ov5640_mipi: ov5640_mipi@4c {
ipu_id = <1>;
csi_id = <0>;
};
/* Parallel camera CSI1 */
ov5642_2: ov5642_2@6c {
compatible = "ovti,ov564x";
reg = <0x6c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu2_2>;
clocks = <&clks 201>;
clock-names = "csi_mclk";
pwn-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
digi,alt-pwn-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
mclk = <24000000>;
mclk_source = <0>;
digi,defer-probe;
csi_id = <1>;
ipu_id = <1>;
status = "disabled";
};
};
&mipi_csi {
ipu_id = <1>;
csi_id = <0>;
};
&v4l2_cap_0 {
ipu_id = <1>;
csi_id = <0>;
};
&v4l2_cap_1 {
ipu_id = <0>;
csi_id = <0>;
};
&iomuxc {
ipu2 {
pinctrl_ipu2: ipu2 {
fsl,pins = <
/* Display IRQ */
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
/* Display contrast */
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x80000000
MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x38
MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
>;
};
pinctrl_ipu2_2: ipu2ctrl2 { /* parallel camera */
fsl,pins = <
MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x80000000
MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x80000000
MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x80000000
MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x80000000
MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x80000000
MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x80000000
MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x80000000
MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x80000000
MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0000a0b0
MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x80000000
MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x80000000
MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000
>;
};
};
};