/
ipu_disp.c
1993 lines (1755 loc) · 56.6 KB
/
ipu_disp.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright 2005-2015 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2019 NXP
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file ipu_disp.c
*
* @brief IPU display submodule API functions
*
* @ingroup IPU
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/ipu-v3.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <asm/atomic.h>
#include "ipu_param_mem.h"
#include "ipu_regs.h"
struct dp_csc_param_t {
int mode;
void *coeff;
};
#define SYNC_WAVE 0
#define NULL_WAVE (-1)
#define ASYNC_SER_WAVE 6
/* DC display ID assignments */
#define DC_DISP_ID_SYNC(di) (di)
#define DC_DISP_ID_SERIAL 2
#define DC_DISP_ID_ASYNC 3
int dmfc_type_setup;
void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first)
{
u32 dmfc_wr_chan, dmfc_dp_chan;
if (first) {
if (dmfc_type_setup > dmfc_type)
dmfc_type = dmfc_type_setup;
else
dmfc_type_setup = dmfc_type;
/* disable DMFC-IC channel*/
ipu_dmfc_write(ipu, 0x2, DMFC_IC_CTRL);
} else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
dev_dbg(ipu->dev, "DMFC high resolution has set, will not change\n");
return;
} else
dmfc_type_setup = dmfc_type;
if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
/* 1 - segment 0~3;
* 5B - segement 4, 5;
* 5F - segement 6, 7;
* 1C, 2C and 6B, 6F unused;
*/
dev_info(ipu->dev, "IPU DMFC DC HIGH RESOLUTION: 1(0~3), 5B(4,5), 5F(6,7)\n");
dmfc_wr_chan = 0x00000088;
dmfc_dp_chan = 0x00009694;
ipu->dmfc_size_28 = 256*4;
ipu->dmfc_size_29 = 0;
ipu->dmfc_size_24 = 0;
ipu->dmfc_size_27 = 128*4;
ipu->dmfc_size_23 = 128*4;
} else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
/* 1 - segment 0, 1;
* 5B - segement 2~5;
* 5F - segement 6,7;
* 1C, 2C and 6B, 6F unused;
*/
dev_info(ipu->dev, "IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)\n");
dmfc_wr_chan = 0x00000090;
dmfc_dp_chan = 0x0000968a;
ipu->dmfc_size_28 = 128*4;
ipu->dmfc_size_29 = 0;
ipu->dmfc_size_24 = 0;
ipu->dmfc_size_27 = 128*4;
ipu->dmfc_size_23 = 256*4;
} else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
/* 5B - segement 0~3;
* 5F - segement 4~7;
* 1, 1C, 2C and 6B, 6F unused;
*/
dev_info(ipu->dev, "IPU DMFC ONLY-DP HIGH RESOLUTION: 5B(0~3), 5F(4~7)\n");
dmfc_wr_chan = 0x00000000;
dmfc_dp_chan = 0x00008c88;
ipu->dmfc_size_28 = 0;
ipu->dmfc_size_29 = 0;
ipu->dmfc_size_24 = 0;
ipu->dmfc_size_27 = 256*4;
ipu->dmfc_size_23 = 256*4;
} else {
/* 1 - segment 0, 1;
* 5B - segement 4, 5;
* 5F - segement 6, 7;
* 1C, 2C and 6B, 6F unused;
*/
dev_info(ipu->dev, "IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
dmfc_wr_chan = 0x00000090;
dmfc_dp_chan = 0x00009694;
ipu->dmfc_size_28 = 128*4;
ipu->dmfc_size_29 = 0;
ipu->dmfc_size_24 = 0;
ipu->dmfc_size_27 = 128*4;
ipu->dmfc_size_23 = 128*4;
}
ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
ipu_dmfc_write(ipu, 0x202020F6, DMFC_WR_CHAN_DEF);
ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
/* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
ipu_dmfc_write(ipu, 0x2020F6F6, DMFC_DP_CHAN_DEF);
}
static int __init dmfc_setup(char *options)
{
get_option(&options, &dmfc_type_setup);
if (dmfc_type_setup > DMFC_HIGH_RESOLUTION_ONLY_DP)
dmfc_type_setup = DMFC_HIGH_RESOLUTION_ONLY_DP;
return 1;
}
__setup("dmfc=", dmfc_setup);
void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width)
{
u32 dmfc_gen1 = ipu_dmfc_read(ipu, DMFC_GENERAL1);
if (width >= HIGH_RESOLUTION_WIDTH) {
if (dma_chan == 23)
_ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DP, 0);
else if (dma_chan == 28)
_ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DC, 0);
}
if (dma_chan == 23) { /*5B*/
if (ipu->dmfc_size_23/width > 3)
dmfc_gen1 |= 1UL << 20;
else
dmfc_gen1 &= ~(1UL << 20);
} else if (dma_chan == 24) { /*6B*/
if (ipu->dmfc_size_24/width > 1)
dmfc_gen1 |= 1UL << 22;
else
dmfc_gen1 &= ~(1UL << 22);
} else if (dma_chan == 27) { /*5F*/
if (ipu->dmfc_size_27/width > 2)
dmfc_gen1 |= 1UL << 21;
else
dmfc_gen1 &= ~(1UL << 21);
} else if (dma_chan == 28) { /*1*/
if (ipu->dmfc_size_28/width > 2)
dmfc_gen1 |= 1UL << 16;
else
dmfc_gen1 &= ~(1UL << 16);
} else if (dma_chan == 29) { /*6F*/
if (ipu->dmfc_size_29/width > 1)
dmfc_gen1 |= 1UL << 23;
else
dmfc_gen1 &= ~(1UL << 23);
}
ipu_dmfc_write(ipu, dmfc_gen1, DMFC_GENERAL1);
}
void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size)
{
u32 dmfc_wr_chan = ipu_dmfc_read(ipu, DMFC_WR_CHAN);
u32 dmfc_dp_chan = ipu_dmfc_read(ipu, DMFC_DP_CHAN);
int dmfc_bs = 0;
switch (burst_size) {
case 64:
dmfc_bs = 0x40;
break;
case 32:
case 20:
dmfc_bs = 0x80;
break;
case 16:
dmfc_bs = 0xc0;
break;
default:
dev_err(ipu->dev, "Unsupported burst size %d\n",
burst_size);
return;
}
if (dma_chan == 23) { /*5B*/
dmfc_dp_chan &= ~(0xc0);
dmfc_dp_chan |= dmfc_bs;
} else if (dma_chan == 27) { /*5F*/
dmfc_dp_chan &= ~(0xc000);
dmfc_dp_chan |= (dmfc_bs << 8);
} else if (dma_chan == 28) { /*1*/
dmfc_wr_chan &= ~(0xc0);
dmfc_wr_chan |= dmfc_bs;
}
ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
}
static void _ipu_di_data_wave_config(struct ipu_soc *ipu,
int di, int wave_gen,
int access_size, int component_size)
{
u32 reg;
reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
(component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
}
static void _ipu_di_data_pin_config(struct ipu_soc *ipu,
int di, int wave_gen, int di_pin, int set,
int up, int down)
{
u32 reg;
reg = ipu_di_read(ipu, di, DI_DW_GEN(wave_gen));
reg &= ~(0x3 << (di_pin * 2));
reg |= set << (di_pin * 2);
ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
ipu_di_write(ipu, di, (down << 16) | up, DI_DW_SET(wave_gen, set));
}
static void _ipu_di_sync_config(struct ipu_soc *ipu,
int di, int wave_gen,
int run_count, int run_src,
int offset_count, int offset_src,
int repeat_count, int cnt_clr_src,
int cnt_polarity_gen_en,
int cnt_polarity_clr_src,
int cnt_polarity_trigger_src,
int cnt_up, int cnt_down)
{
u32 reg;
if ((run_count >= 0x1000) || (offset_count >= 0x1000) || (repeat_count >= 0x1000) ||
(cnt_up >= 0x400) || (cnt_down >= 0x400)) {
dev_err(ipu->dev, "DI%d counters out of range.\n", di);
return;
}
reg = (run_count << 19) | (++run_src << 16) |
(offset_count << 3) | ++offset_src;
ipu_di_write(ipu, di, reg, DI_SW_GEN0(wave_gen));
reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
(++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
reg |= (cnt_down << 16) | cnt_up;
if (repeat_count == 0) {
/* Enable auto reload */
reg |= 0x10000000;
}
ipu_di_write(ipu, di, reg, DI_SW_GEN1(wave_gen));
reg = ipu_di_read(ipu, di, DI_STP_REP(wave_gen));
reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
ipu_di_write(ipu, di, reg, DI_STP_REP(wave_gen));
}
static void _ipu_dc_map_link(struct ipu_soc *ipu,
int current_map,
int base_map_0, int buf_num_0,
int base_map_1, int buf_num_1,
int base_map_2, int buf_num_2)
{
int ptr_0 = base_map_0 * 3 + buf_num_0;
int ptr_1 = base_map_1 * 3 + buf_num_1;
int ptr_2 = base_map_2 * 3 + buf_num_2;
int ptr;
u32 reg;
ptr = (ptr_2 << 10) + (ptr_1 << 5) + ptr_0;
reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(current_map));
reg &= ~(0x1F << ((16 * (current_map & 0x1))));
reg |= ptr << ((16 * (current_map & 0x1)));
ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(current_map));
}
static void _ipu_dc_map_config(struct ipu_soc *ipu,
int map, int byte_num, int offset, int mask)
{
int ptr = map * 3 + byte_num;
u32 reg;
reg = ipu_dc_read(ipu, DC_MAP_CONF_VAL(ptr));
reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
ipu_dc_write(ipu, reg, DC_MAP_CONF_VAL(ptr));
reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(map));
}
static void _ipu_dc_map_clear(struct ipu_soc *ipu, int map)
{
u32 reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
ipu_dc_write(ipu, reg & ~(0xFFFF << (16 * (map & 0x1))),
DC_MAP_CONF_PTR(map));
}
static void _ipu_dc_write_tmpl(struct ipu_soc *ipu,
int word, u32 opcode, u32 operand, int map,
int wave, int glue, int sync, int stop)
{
u32 reg;
if (opcode == WRG) {
reg = sync;
reg |= (glue << 4);
reg |= (++wave << 11);
reg |= ((operand & 0x1FFFF) << 15);
ipu_dc_tmpl_write(ipu, reg, word * 8);
reg = (operand >> 17);
reg |= opcode << 7;
reg |= (stop << 9);
ipu_dc_tmpl_write(ipu, reg, word * 8 + 4);
} else {
reg = sync;
reg |= (glue << 4);
reg |= (++wave << 11);
reg |= (++map << 15);
reg |= (operand << 20) & 0xFFF00000;
ipu_dc_tmpl_write(ipu, reg, word * 8);
reg = (operand >> 12);
reg |= opcode << 4;
reg |= (stop << 9);
ipu_dc_tmpl_write(ipu, reg, word * 8 + 4);
}
}
static void _ipu_dc_link_event(struct ipu_soc *ipu,
int chan, int event, int addr, int priority)
{
u32 reg;
u32 address_shift;
if (event < DC_EVEN_UGDE0) {
reg = ipu_dc_read(ipu, DC_RL_CH(chan, event));
reg &= ~(0xFFFF << (16 * (event & 0x1)));
reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
ipu_dc_write(ipu, reg, DC_RL_CH(chan, event));
} else {
reg = ipu_dc_read(ipu, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
if ((event - DC_EVEN_UGDE0) & 0x1) {
reg &= ~(0x2FF << 16);
reg |= (addr << 16);
reg |= priority ? (2 << 24) : 0x0;
} else {
reg &= ~0xFC00FFFF;
if (priority)
chan = (chan >> 1) +
((((chan & 0x1) + ((chan & 0x2) >> 1))) | (chan >> 3));
else
chan = 0x7;
address_shift = ((event - DC_EVEN_UGDE0) >> 1) ? 7 : 8;
reg |= (addr << address_shift) | (priority << 3) | chan;
}
ipu_dc_write(ipu, reg, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
}
}
/* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250;
U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.;
V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;*/
static const int rgb2ycbcr_coeff[5][3] = {
{0x4D, 0x96, 0x1D},
{-0x2B, -0x55, 0x80},
{0x80, -0x6B, -0x15},
{0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */
{0x2, 0x2, 0x2}, /* S0, S1, S2 */
};
/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
static const int ycbcr2rgb_coeff[5][3] = {
{0x095, 0x000, 0x0CC},
{0x095, 0x3CE, 0x398},
{0x095, 0x0FF, 0x000},
{0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */
{0x1, 0x1, 0x1}, /*S0,S1,S2 */
};
#define mask_a(a) ((u32)(a) & 0x3FF)
#define mask_b(b) ((u32)(b) & 0x3FFF)
/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
static int _rgb_to_yuv(int n, int red, int green, int blue)
{
int c;
c = red * rgb2ycbcr_coeff[n][0];
c += green * rgb2ycbcr_coeff[n][1];
c += blue * rgb2ycbcr_coeff[n][2];
c /= 16;
c += rgb2ycbcr_coeff[3][n] * 4;
c += 8;
c /= 16;
if (c < 0)
c = 0;
if (c > 255)
c = 255;
return c;
}
/*
* Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
* Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
*/
static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
{
{DP_COM_CONF_CSC_DEF_BOTH, (void *)&rgb2ycbcr_coeff},
{0, 0}, {0, 0},
{DP_COM_CONF_CSC_DEF_BG, (void *)&rgb2ycbcr_coeff},
{DP_COM_CONF_CSC_DEF_BG, (void *)&rgb2ycbcr_coeff}
},
{
{0, 0},
{DP_COM_CONF_CSC_DEF_BOTH, (void *)&ycbcr2rgb_coeff},
{DP_COM_CONF_CSC_DEF_BG, (void *)&ycbcr2rgb_coeff},
{0, 0},
{DP_COM_CONF_CSC_DEF_BG, (void *)&ycbcr2rgb_coeff}
},
{
{0, 0},
{DP_COM_CONF_CSC_DEF_FG, (void *)&ycbcr2rgb_coeff},
{0, 0}, {0, 0}, {0, 0}
},
{
{DP_COM_CONF_CSC_DEF_FG, (void *)&rgb2ycbcr_coeff},
{0, 0}, {0, 0}, {0, 0}, {0, 0}
},
{
{DP_COM_CONF_CSC_DEF_FG, (void *)&rgb2ycbcr_coeff},
{DP_COM_CONF_CSC_DEF_FG, (void *)&ycbcr2rgb_coeff},
{0, 0}, {0, 0}, {0, 0}
}
};
void __ipu_dp_csc_setup(struct ipu_soc *ipu,
int dp, struct dp_csc_param_t dp_csc_param,
bool srm_mode_update)
{
u32 reg;
const int (*coeff)[5][3];
if (dp_csc_param.mode >= 0) {
reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
reg &= ~DP_COM_CONF_CSC_DEF_MASK;
reg |= dp_csc_param.mode;
ipu_dp_write(ipu, reg, DP_COM_CONF(dp));
}
coeff = dp_csc_param.coeff;
if (coeff) {
ipu_dp_write(ipu, mask_a((*coeff)[0][0]) |
(mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
ipu_dp_write(ipu, mask_a((*coeff)[0][2]) |
(mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
ipu_dp_write(ipu, mask_a((*coeff)[1][1]) |
(mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
ipu_dp_write(ipu, mask_a((*coeff)[2][0]) |
(mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
ipu_dp_write(ipu, mask_a((*coeff)[2][2]) |
(mask_b((*coeff)[3][0]) << 16) |
((*coeff)[4][0] << 30), DP_CSC_0(dp));
ipu_dp_write(ipu, mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
(mask_b((*coeff)[3][2]) << 16) |
((*coeff)[4][2] << 30), DP_CSC_1(dp));
}
if (srm_mode_update) {
reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
}
}
int _ipu_dp_init(struct ipu_soc *ipu,
ipu_channel_t channel, uint32_t in_pixel_fmt,
uint32_t out_pixel_fmt)
{
int in_fmt, out_fmt;
int dp;
int partial = false;
uint32_t reg;
if (channel == MEM_FG_SYNC) {
dp = DP_SYNC;
partial = true;
} else if (channel == MEM_BG_SYNC) {
dp = DP_SYNC;
partial = false;
} else if (channel == MEM_BG_ASYNC0) {
dp = DP_ASYNC0;
partial = false;
} else {
return -EINVAL;
}
in_fmt = format_to_colorspace(in_pixel_fmt);
out_fmt = format_to_colorspace(out_pixel_fmt);
if (partial) {
if (in_fmt == RGB) {
if (out_fmt == RGB)
ipu->fg_csc_type = RGB2RGB;
else
ipu->fg_csc_type = RGB2YUV;
} else {
if (out_fmt == RGB)
ipu->fg_csc_type = YUV2RGB;
else
ipu->fg_csc_type = YUV2YUV;
}
} else {
if (in_fmt == RGB) {
if (out_fmt == RGB)
ipu->bg_csc_type = RGB2RGB;
else
ipu->bg_csc_type = RGB2YUV;
} else {
if (out_fmt == RGB)
ipu->bg_csc_type = YUV2RGB;
else
ipu->bg_csc_type = YUV2YUV;
}
}
/* Transform color key from rgb to yuv if CSC is enabled */
reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
if (ipu->color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
(((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB)))) {
int red, green, blue;
int y, u, v;
uint32_t color_key = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFFFFFFL;
dev_dbg(ipu->dev, "_ipu_dp_init color key 0x%x need change to yuv fmt!\n", color_key);
red = (color_key >> 16) & 0xFF;
green = (color_key >> 8) & 0xFF;
blue = color_key & 0xFF;
y = _rgb_to_yuv(0, red, green, blue);
u = _rgb_to_yuv(1, red, green, blue);
v = _rgb_to_yuv(2, red, green, blue);
color_key = (y << 16) | (u << 8) | v;
reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(dp));
ipu->color_key_4rgb = false;
dev_dbg(ipu->dev, "_ipu_dp_init color key change to yuv fmt 0x%x!\n", color_key);
}
__ipu_dp_csc_setup(ipu, dp,
dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type],
false);
return 0;
}
void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel)
{
int dp;
int partial = false;
if (channel == MEM_FG_SYNC) {
dp = DP_SYNC;
partial = true;
} else if (channel == MEM_BG_SYNC) {
dp = DP_SYNC;
partial = false;
} else if (channel == MEM_BG_ASYNC0) {
dp = DP_ASYNC0;
partial = false;
} else {
return;
}
if (partial)
ipu->fg_csc_type = CSC_NONE;
else
ipu->bg_csc_type = CSC_NONE;
__ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], false);
}
void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt)
{
u32 reg = 0;
if ((dc_chan == 1) || (dc_chan == 5)) {
if (interlaced) {
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 3);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 2);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 1);
} else {
if (di) {
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 2, 3);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 3, 2);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 1, 1);
if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
(pixel_fmt == IPU_PIX_FMT_UYVY) ||
(pixel_fmt == IPU_PIX_FMT_YVYU) ||
(pixel_fmt == IPU_PIX_FMT_VYUY)) {
_ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 9, 5);
_ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 8, 5);
}
} else {
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 5, 3);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 6, 2);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 12, 1);
if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
(pixel_fmt == IPU_PIX_FMT_UYVY) ||
(pixel_fmt == IPU_PIX_FMT_YVYU) ||
(pixel_fmt == IPU_PIX_FMT_VYUY)) {
_ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 10, 5);
_ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 11, 5);
}
}
}
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
reg = 0x2;
reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
reg |= di << 2;
if (interlaced)
reg |= DC_WR_CH_CONF_FIELD_MODE;
} else if ((dc_chan == 8) || (dc_chan == 9)) {
/* async channels */
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
reg = 0x3;
reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
}
ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
ipu_dc_write(ipu, 0x00000000, DC_WR_CH_ADDR(dc_chan));
ipu_dc_write(ipu, 0x00000084, DC_GEN);
}
void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan)
{
if ((dc_chan == 1) || (dc_chan == 5)) {
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 0, 0);
} else if ((dc_chan == 8) || (dc_chan == 9)) {
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
}
}
int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel)
{
if (channel == MEM_DC_SYNC)
return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_1) &
DC_WR_CH_CONF_FIELD_MODE);
else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_5) &
DC_WR_CH_CONF_FIELD_MODE);
return 0;
}
void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel)
{
int di;
uint32_t reg;
uint32_t dc_chan;
int irq = 0;
if (channel == MEM_FG_SYNC)
irq = IPU_IRQ_DP_SF_END;
else if (channel == MEM_DC_SYNC)
dc_chan = 1;
else if (channel == MEM_BG_SYNC)
dc_chan = 5;
else
return;
if (channel == MEM_FG_SYNC) {
/* Enable FG channel */
reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
ipu_dp_write(ipu, reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
return;
} else if (channel == MEM_BG_SYNC) {
reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
}
di = ipu->dc_di_assignment[dc_chan];
/* Make sure other DC sync channel is not assigned same DI */
reg = ipu_dc_read(ipu, DC_WR_CH_CONF(6 - dc_chan));
if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
}
reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
clk_prepare_enable(ipu->pixel_clk[di]);
ipu->pixel_clk_en[ipu->dc_di_assignment[dc_chan]] = true;
}
static irqreturn_t dc_irq_handler(int irq, void *dev_id)
{
struct ipu_soc *ipu = dev_id;
struct completion *comp = &ipu->dc_comp;
uint32_t reg;
uint32_t dc_chan;
if (irq == IPU_IRQ_DC_FC_1)
dc_chan = 1;
else
dc_chan = 5;
if (!ipu->dc_swap) {
reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
reg = ipu_cm_read(ipu, IPU_DISP_GEN);
if (ipu->dc_di_assignment[dc_chan])
reg &= ~DI1_COUNTER_RELEASE;
else
reg &= ~DI0_COUNTER_RELEASE;
ipu_cm_write(ipu, reg, IPU_DISP_GEN);
}
complete(comp);
return IRQ_HANDLED;
}
void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap)
{
int ret;
uint32_t reg;
uint32_t csc;
uint32_t dc_chan;
int irq = 0;
int timeout = 50;
ipu->dc_swap = swap;
if (channel == MEM_DC_SYNC) {
dc_chan = 1;
irq = IPU_IRQ_DC_FC_1;
} else if (channel == MEM_BG_SYNC) {
dc_chan = 5;
irq = IPU_IRQ_DP_SF_END;
} else if (channel == MEM_FG_SYNC) {
/* Disable FG channel */
dc_chan = 5;
reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
csc = reg & DP_COM_CONF_CSC_DEF_MASK;
if (csc == DP_COM_CONF_CSC_DEF_FG)
reg &= ~DP_COM_CONF_CSC_DEF_MASK;
reg &= ~DP_COM_CONF_FG_EN;
ipu_dp_write(ipu, reg, DP_COM_CONF(DP_SYNC));
reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
if (ipu_is_channel_busy(ipu, MEM_BG_SYNC)) {
ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END),
IPUIRQ_2_STATREG(ipu->devtype,
IPU_IRQ_DP_SF_END));
while ((ipu_cm_read(ipu,
IPUIRQ_2_STATREG(ipu->devtype,
IPU_IRQ_DP_SF_END)) &
IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) {
msleep(2);
timeout -= 2;
if (timeout <= 0)
break;
}
}
return;
} else {
return;
}
init_completion(&ipu->dc_comp);
ret = ipu_request_irq(ipu, irq, dc_irq_handler, 0, NULL, ipu);
if (ret < 0) {
dev_err(ipu->dev, "DC irq %d in use\n", irq);
return;
}
ret = wait_for_completion_timeout(&ipu->dc_comp, msecs_to_jiffies(50));
ipu_free_irq(ipu, irq, ipu);
dev_dbg(ipu->dev, "DC stop timeout - %d * 10ms\n", 5 - ret);
if (ipu->dc_swap) {
/* Swap DC channel 1 and 5 settings, and disable old dc chan */
reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
reg ^= DC_WR_CH_CONF_PROG_DI_ID;
ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
}
}
void _ipu_init_dc_mappings(struct ipu_soc *ipu)
{
/* IPU_PIX_FMT_RGB24 */
_ipu_dc_map_clear(ipu, 0);
_ipu_dc_map_config(ipu, 0, 0, 7, 0xFF);
_ipu_dc_map_config(ipu, 0, 1, 15, 0xFF);
_ipu_dc_map_config(ipu, 0, 2, 23, 0xFF);
/* IPU_PIX_FMT_RGB666 */
_ipu_dc_map_clear(ipu, 1);
_ipu_dc_map_config(ipu, 1, 0, 5, 0xFC);
_ipu_dc_map_config(ipu, 1, 1, 11, 0xFC);
_ipu_dc_map_config(ipu, 1, 2, 17, 0xFC);
/* IPU_PIX_FMT_YUV444 */
_ipu_dc_map_clear(ipu, 2);
_ipu_dc_map_config(ipu, 2, 0, 15, 0xFF);
_ipu_dc_map_config(ipu, 2, 1, 23, 0xFF);
_ipu_dc_map_config(ipu, 2, 2, 7, 0xFF);
/* IPU_PIX_FMT_RGB565 */
_ipu_dc_map_clear(ipu, 3);
_ipu_dc_map_config(ipu, 3, 0, 4, 0xF8);
_ipu_dc_map_config(ipu, 3, 1, 10, 0xFC);
_ipu_dc_map_config(ipu, 3, 2, 15, 0xF8);
/* IPU_PIX_FMT_LVDS666 */
_ipu_dc_map_clear(ipu, 4);
_ipu_dc_map_config(ipu, 4, 0, 5, 0xFC);
_ipu_dc_map_config(ipu, 4, 1, 13, 0xFC);
_ipu_dc_map_config(ipu, 4, 2, 21, 0xFC);
/* IPU_PIX_FMT_VYUY 16bit width */
_ipu_dc_map_clear(ipu, 5);
_ipu_dc_map_config(ipu, 5, 0, 7, 0xFF);
_ipu_dc_map_config(ipu, 5, 1, 0, 0x0);
_ipu_dc_map_config(ipu, 5, 2, 15, 0xFF);
_ipu_dc_map_clear(ipu, 6);
_ipu_dc_map_config(ipu, 6, 0, 0, 0x0);
_ipu_dc_map_config(ipu, 6, 1, 7, 0xFF);
_ipu_dc_map_config(ipu, 6, 2, 15, 0xFF);
/* IPU_PIX_FMT_UYUV 16bit width */
_ipu_dc_map_clear(ipu, 7);
_ipu_dc_map_link(ipu, 7, 6, 0, 6, 1, 6, 2);
_ipu_dc_map_clear(ipu, 8);
_ipu_dc_map_link(ipu, 8, 5, 0, 5, 1, 5, 2);
/* IPU_PIX_FMT_YUYV 16bit width */
_ipu_dc_map_clear(ipu, 9);
_ipu_dc_map_link(ipu, 9, 5, 2, 5, 1, 5, 0);
_ipu_dc_map_clear(ipu, 10);
_ipu_dc_map_link(ipu, 10, 5, 1, 5, 2, 5, 0);
/* IPU_PIX_FMT_YVYU 16bit width */
_ipu_dc_map_clear(ipu, 11);
_ipu_dc_map_link(ipu, 11, 5, 1, 5, 2, 5, 0);
_ipu_dc_map_clear(ipu, 12);
_ipu_dc_map_link(ipu, 12, 5, 2, 5, 1, 5, 0);
/* IPU_PIX_FMT_GBR24 */
/* IPU_PIX_FMT_VYU444 */
_ipu_dc_map_clear(ipu, 13);
_ipu_dc_map_link(ipu, 13, 0, 2, 0, 0, 0, 1);
/* IPU_PIX_FMT_BGR24 */
_ipu_dc_map_clear(ipu, 14);
_ipu_dc_map_link(ipu, 14, 0, 2, 0, 1, 0, 0);
}
int _ipu_pixfmt_to_map(uint32_t fmt)
{
switch (fmt) {
case IPU_PIX_FMT_GENERIC:
case IPU_PIX_FMT_RGB24:
return 0;
case IPU_PIX_FMT_RGB666:
return 1;
case IPU_PIX_FMT_YUV444:
return 2;
case IPU_PIX_FMT_RGB565:
return 3;
case IPU_PIX_FMT_LVDS666:
return 4;
case IPU_PIX_FMT_VYUY:
return 6;
case IPU_PIX_FMT_UYVY:
return 8;
case IPU_PIX_FMT_YUYV:
return 10;
case IPU_PIX_FMT_YVYU:
return 12;
case IPU_PIX_FMT_GBR24:
case IPU_PIX_FMT_VYU444:
return 13;
case IPU_PIX_FMT_BGR24:
return 14;
}
return -1;
}
/*!
* This function sets the colorspace for of dp.
* modes.
*
* @param ipu ipu handler
* @param channel Input parameter for the logical channel ID.
*
* @param param If it's not NULL, update the csc table
* with this parameter.
*
* @return N/A
*/
void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
{
int dp;
struct dp_csc_param_t dp_csc_param;
if (channel == MEM_FG_SYNC)
dp = DP_SYNC;
else if (channel == MEM_BG_SYNC)
dp = DP_SYNC;
else if (channel == MEM_BG_ASYNC0)
dp = DP_ASYNC0;
else
return;
dp_csc_param.mode = -1;
dp_csc_param.coeff = param;
__ipu_dp_csc_setup(ipu, dp, dp_csc_param, true);
}