fsl,imx8mn-pinctrl.txt

* Freescale IMX8MN IOMUX Controller

Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.

Required properties:
- compatible: "fsl,imx8mn-iomuxc"
- reg: should contain the base physical address and size of the iomuxc
  registers.

Required properties in sub-nodes:
- fsl,pins: each entry consists of 6 integers and represents the mux and config
  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val
  input_val> are specified using a PIN_FUNC_ID macro, which can be found in
  <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last integer CONFIG is
  the pad setting value like pull-up on this pin. Please refer to i.MX8M Nano
  Reference Manual for detailed CONFIG settings.

CONFIG bits definition:
PAD_CTL_PE                      (1 << 8)
PAD_CTL_HYS                     (1 << 7)
PAD_CTL_PUE                     (1 << 6)
PAD_CTL_ODE                     (1 << 5)
PAD_CTL_SRE_SLOW                (0 << 4)
PAD_CTL_SRE_FAST                (1 << 4)
PAD_CTL_DSE_X1                  (0 << 1)
PAD_CTL_DSE_X4                  (1 << 1)
PAD_CTL_DSE_X2                  (2 << 1)
PAD_CTL_DSE_X6                  (3 << 1)

Examples:

&uart1 {
       pinctrl-names = "default";
       pinctrl-0 = <&pinctrl_uart1>;
};

iomuxc: pinctrl@30330000 {
        compatible = "fsl,imx8mn-iomuxc";
        reg = <0x0 0x30330000 0x0 0x10000>;

        pinctrl_uart1: uart1grp {
                fsl,pins = <
  <include/dt-bindings/pinctrl/pins-imx8mn.h>. The last integer CONFIG is
  the pad setting value like pull-up on this pin. Please refer to i.MX8M Nano
  Reference Manual for detailed CONFIG settings.

CONFIG bits definition:
PAD_CTL_PE                      (1 << 8)
PAD_CTL_HYS                     (1 << 7)
PAD_CTL_PUE                     (1 << 6)
PAD_CTL_ODE                     (1 << 5)
PAD_CTL_SRE_SLOW                (0 << 4)
PAD_CTL_SRE_FAST                (1 << 4)
PAD_CTL_DSE_X1                  (0 << 1)
PAD_CTL_DSE_X4                  (1 << 1)
PAD_CTL_DSE_X2                  (2 << 1)
PAD_CTL_DSE_X6                  (3 << 1)

			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
			MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
			MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
			MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19
                >;
        };
};