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i2c-imx.yaml
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i2c-imx.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-imx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
maintainers:
- Oleksij Rempel <o.rempel@pengutronix.de>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
oneOf:
- const: fsl,imx1-i2c
- const: fsl,imx21-i2c
- const: fsl,vf610-i2c
- items:
- enum:
- fsl,ls1012a-i2c
- fsl,ls1021a-i2c
- fsl,ls1028a-i2c
- fsl,ls1043a-i2c
- fsl,ls1046a-i2c
- fsl,ls1088a-i2c
- fsl,ls208xa-i2c
- fsl,lx2160a-i2c
- const: fsl,vf610-i2c
- items:
- const: fsl,imx35-i2c
- const: fsl,imx1-i2c
- items:
- const: fsl,imx7d-i2c
- const: fsl,imx21-i2c
- items:
- enum:
- fsl,imx25-i2c
- fsl,imx27-i2c
- fsl,imx31-i2c
- fsl,imx50-i2c
- fsl,imx51-i2c
- fsl,imx53-i2c
- fsl,imx6q-i2c
- fsl,imx6sl-i2c
- fsl,imx6sx-i2c
- fsl,imx6sll-i2c
- fsl,imx6ul-i2c
- fsl,imx7s-i2c
- fsl,imx8mq-i2c
- fsl,imx8mm-i2c
- fsl,imx8mn-i2c
- fsl,imx8mp-i2c
- const: fsl,imx21-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: ipg
clock-frequency:
minimum: 1
default: 100000
maximum: 400000
dmas:
items:
- description: DMA controller phandle and request line for RX
- description: DMA controller phandle and request line for TX
dma-names:
items:
- const: rx
- const: tx
sda-gpios:
maxItems: 1
scl-gpios:
maxItems: 1
digi,atecc508a-workaround:
description: ATECC508A cryptochip produces an sporadic unexpected
behavior on the i2c bus when sharing the bus with other peripherals at
a bus speed lower than 300KHz.
This property enables a workaround suggested by the chip manufacturer
(Microchip):
1- Wake the cryptochip device before communication with the other
devices on the system bus.
2- Upon completion of communication with the other device a cryptochip
Sleep command should be issued. (This is to put the device into a
known state if it did actually wake up).
digi,atecc508a-address:
description: ATECC508A bus slave address (7 bits). If not present,
the default ATECC508A slave address 0x60 is used.
digi,atecc508a-awake-delay-uS:
description: Delay in micro seconds since awake command until communication
with other devices. If not present, no delay is done.
digi,atecc508a-sleep-delay-uS:
description: Delay in micro seconds since awake command until sleep
command. This delay is used to assure the cryptochip is awake when the
sleep command is sent. If not present, no delay is done.
digi,buffer-time-us:
description: Sets the buffer time in microseconds. This is the bus free
time between stop and start conditions. Some peripherals may require
this time to operate properly.
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c@83fc4000 {
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x83fc4000 0x4000>;
interrupts = <63>;
clocks = <&clks IMX5_CLK_I2C2_GATE>;
};
- |
#include <dt-bindings/clock/vf610-clock.h>
i2c@40066000 {
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C0>;
clock-names = "ipg";
dmas = <&edma0 0 50>,
<&edma0 0 51>;
dma-names = "rx", "tx";
};