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Jit_Integer.cpp
2041 lines (1883 loc) · 47.6 KB
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Jit_Integer.cpp
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// Copyright 2008 Dolphin Emulator Project
// Licensed under GPLv2+
// Refer to the license.txt file included.
#include <array>
#include <limits>
#include <vector>
#include "Common/Assert.h"
#include "Common/BitUtils.h"
#include "Common/CPUDetect.h"
#include "Common/CommonTypes.h"
#include "Common/MathUtil.h"
#include "Common/x64Emitter.h"
#include "Core/PowerPC/Jit64/Jit.h"
#include "Core/PowerPC/Jit64/RegCache/JitRegCache.h"
#include "Core/PowerPC/Jit64Common/Jit64PowerPCState.h"
#include "Core/PowerPC/PPCAnalyst.h"
#include "Core/PowerPC/PowerPC.h"
using namespace Gen;
void Jit64::GenerateConstantOverflow(s64 val)
{
GenerateConstantOverflow(val > std::numeric_limits<s32>::max() ||
val < std::numeric_limits<s32>::min());
}
void Jit64::GenerateConstantOverflow(bool overflow)
{
if (overflow)
{
// XER[OV/SO] = 1
MOV(8, PPCSTATE(xer_so_ov), Imm8(XER_OV_MASK | XER_SO_MASK));
}
else
{
// XER[OV] = 0
AND(8, PPCSTATE(xer_so_ov), Imm8(~XER_OV_MASK));
}
}
// We could do overflow branchlessly, but unlike carry it seems to be quite a bit rarer.
void Jit64::GenerateOverflow()
{
FixupBranch jno = J_CC(CC_NO);
// XER[OV/SO] = 1
MOV(8, PPCSTATE(xer_so_ov), Imm8(XER_OV_MASK | XER_SO_MASK));
FixupBranch exit = J();
SetJumpTarget(jno);
// XER[OV] = 0
// We need to do this without modifying flags so as not to break stuff that assumes flags
// aren't clobbered (carry, branch merging): speed doesn't really matter here (this is really
// rare).
static const std::array<u8, 4> ovtable = {{0, 0, XER_SO_MASK, XER_SO_MASK}};
MOVZX(32, 8, RSCRATCH, PPCSTATE(xer_so_ov));
LEA(64, RSCRATCH2, MConst(ovtable));
MOV(8, R(RSCRATCH), MRegSum(RSCRATCH, RSCRATCH2));
MOV(8, PPCSTATE(xer_so_ov), R(RSCRATCH));
SetJumpTarget(exit);
}
void Jit64::FinalizeCarry(CCFlags cond)
{
js.carryFlagSet = false;
js.carryFlagInverted = false;
if (js.op->wantsCA)
{
// Not actually merging instructions, but the effect is equivalent (we can't have
// breakpoints/etc in between).
if (CanMergeNextInstructions(1) && js.op[1].wantsCAInFlags)
{
if (cond == CC_C || cond == CC_NC)
{
js.carryFlagInverted = cond == CC_NC;
}
else
{
// convert the condition to a carry flag (is there a better way?)
SETcc(cond, R(RSCRATCH));
SHR(8, R(RSCRATCH), Imm8(1));
}
LockFlags();
js.carryFlagSet = true;
}
else
{
JitSetCAIf(cond);
}
}
}
// Unconditional version
void Jit64::FinalizeCarry(bool ca)
{
js.carryFlagSet = false;
js.carryFlagInverted = false;
if (js.op->wantsCA)
{
if (CanMergeNextInstructions(1) && js.op[1].wantsCAInFlags)
{
if (ca)
STC();
else
CLC();
LockFlags();
js.carryFlagSet = true;
}
else if (ca)
{
JitSetCA();
}
else
{
JitClearCA();
}
}
}
void Jit64::FinalizeCarryOverflow(bool oe, bool inv)
{
if (oe)
{
// Make sure not to lose the carry flags (not a big deal, this path is rare).
PUSHF();
// XER[OV] = 0
AND(8, PPCSTATE(xer_so_ov), Imm8(~XER_OV_MASK));
FixupBranch jno = J_CC(CC_NO);
// XER[OV/SO] = 1
MOV(8, PPCSTATE(xer_so_ov), Imm8(XER_SO_MASK | XER_OV_MASK));
SetJumpTarget(jno);
POPF();
}
// Do carry
FinalizeCarry(inv ? CC_NC : CC_C);
}
// Be careful; only set needs_test to false if we can be absolutely sure flags don't need
// to be recalculated and haven't been clobbered. Keep in mind not all instructions set
// sufficient flags -- for example, the flags from SHL/SHR are *not* sufficient for LT/GT
// branches, only EQ.
// The flags from any instruction that may set OF (such as ADD/SUB) can not be used for
// LT/GT either.
void Jit64::ComputeRC(preg_t preg, bool needs_test, bool needs_sext)
{
RCOpArg arg = gpr.Use(preg, RCMode::Read);
RegCache::Realize(arg);
if (arg.IsImm())
{
MOV(64, PPCSTATE(cr_val[0]), Imm32(arg.SImm32()));
}
else if (needs_sext)
{
MOVSX(64, 32, RSCRATCH, arg);
MOV(64, PPCSTATE(cr_val[0]), R(RSCRATCH));
}
else
{
MOV(64, PPCSTATE(cr_val[0]), arg);
}
if (CheckMergedBranch(0))
{
if (arg.IsImm())
{
s32 offset = arg.SImm32();
arg.Unlock();
DoMergedBranchImmediate(offset);
}
else
{
if (needs_test)
{
TEST(32, arg, arg);
}
else
{
// If an operand to the cmp/rc op we're merging with the branch isn't used anymore, it'd be
// better to flush it here so that we don't have to flush it on both sides of the branch.
// We don't want to do this if a test is needed though, because it would interrupt macro-op
// fusion.
for (int j : ~js.op->gprInUse)
gpr.StoreFromRegister(j);
}
arg.Unlock();
DoMergedBranchCondition();
}
}
}
void Jit64::ComputeRC(const OpArg& arg, bool needs_test, bool needs_sext)
{
ASSERT_MSG(DYNA_REC, arg.IsSimpleReg() || arg.IsImm(), "Invalid ComputeRC operand");
if (arg.IsImm())
{
MOV(64, PPCSTATE(cr_val[0]), Imm32(arg.SImm32()));
}
else if (needs_sext)
{
MOVSX(64, 32, RSCRATCH, arg);
MOV(64, PPCSTATE(cr_val[0]), R(RSCRATCH));
}
else
{
MOV(64, PPCSTATE(cr_val[0]), arg);
}
if (CheckMergedBranch(0))
{
if (arg.IsImm())
{
DoMergedBranchImmediate(arg.SImm32());
}
else
{
if (needs_test)
{
TEST(32, arg, arg);
}
else
{
// If an operand to the cmp/rc op we're merging with the branch isn't used anymore, it'd be
// better to flush it here so that we don't have to flush it on both sides of the branch.
// We don't want to do this if a test is needed though, because it would interrupt macro-op
// fusion.
for (int j : ~js.op->gprInUse)
gpr.StoreFromRegister(j);
}
DoMergedBranchCondition();
}
}
}
// we can't do this optimization in the emitter because MOVZX and AND have different effects on
// flags.
void Jit64::AndWithMask(X64Reg reg, u32 mask)
{
if (mask == 0xff)
MOVZX(32, 8, reg, R(reg));
else if (mask == 0xffff)
MOVZX(32, 16, reg, R(reg));
else
AND(32, R(reg), Imm32(mask));
}
// Following static functions are used in conjunction with regimmop
static u32 Add(u32 a, u32 b)
{
return a + b;
}
static u32 Or(u32 a, u32 b)
{
return a | b;
}
static u32 And(u32 a, u32 b)
{
return a & b;
}
static u32 Xor(u32 a, u32 b)
{
return a ^ b;
}
void Jit64::regimmop(int d, int a, bool binary, u32 value, Operation doop,
void (XEmitter::*op)(int, const OpArg&, const OpArg&), bool Rc, bool carry)
{
bool needs_test = doop == Add;
// Be careful; addic treats r0 as r0, but addi treats r0 as zero.
if (a || binary || carry)
{
carry &= js.op->wantsCA;
if (gpr.IsImm(a) && !carry)
{
gpr.SetImmediate32(d, doop(gpr.Imm32(a), value));
}
else
{
RCOpArg Ra = gpr.Use(a, RCMode::Read);
RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rd);
if (doop == Add && Ra.IsSimpleReg() && !carry && d != a)
{
LEA(32, Rd, MDisp(Ra.GetSimpleReg(), value));
}
else
{
if (d != a)
MOV(32, Rd, Ra);
(this->*op)(32, Rd, Imm32(value)); // m_GPR[d] = m_GPR[_inst.RA] + _inst.SIMM_16;
}
}
if (carry)
FinalizeCarry(CC_C);
}
else if (doop == Add)
{
// a == 0, which for these instructions imply value = 0
gpr.SetImmediate32(d, value);
}
else
{
ASSERT_MSG(DYNA_REC, 0, "WTF regimmop");
}
if (Rc)
ComputeRC(d, needs_test, doop != And || (value & 0x80000000));
}
void Jit64::reg_imm(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITIntegerOff);
u32 d = inst.RD, a = inst.RA, s = inst.RS;
switch (inst.OPCD)
{
case 14: // addi
// occasionally used as MOV - emulate, with immediate propagation
if (gpr.IsImm(a) && d != a && a != 0)
{
gpr.SetImmediate32(d, gpr.Imm32(a) + (u32)(s32)inst.SIMM_16);
}
else if (inst.SIMM_16 == 0 && d != a && a != 0)
{
RCOpArg Ra = gpr.Use(a, RCMode::Read);
RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rd);
MOV(32, Rd, Ra);
}
else
{
regimmop(d, a, false, (u32)(s32)inst.SIMM_16, Add, &XEmitter::ADD); // addi
}
break;
case 15: // addis
regimmop(d, a, false, (u32)inst.SIMM_16 << 16, Add, &XEmitter::ADD);
break;
case 24: // ori
case 25: // oris
{
// check for nop
if (a == s && inst.UIMM == 0)
{
// Make the nop visible in the generated code. not much use but interesting if we see one.
NOP();
return;
}
const u32 immediate = inst.OPCD == 24 ? inst.UIMM : inst.UIMM << 16;
regimmop(a, s, true, immediate, Or, &XEmitter::OR);
break;
}
case 28: // andi
regimmop(a, s, true, inst.UIMM, And, &XEmitter::AND, true);
break;
case 29: // andis
regimmop(a, s, true, inst.UIMM << 16, And, &XEmitter::AND, true);
break;
case 26: // xori
case 27: // xoris
{
if (s == a && inst.UIMM == 0)
{
// Make the nop visible in the generated code.
NOP();
return;
}
const u32 immediate = inst.OPCD == 26 ? inst.UIMM : inst.UIMM << 16;
regimmop(a, s, true, immediate, Xor, &XEmitter::XOR, false);
break;
}
case 12: // addic
regimmop(d, a, false, (u32)(s32)inst.SIMM_16, Add, &XEmitter::ADD, false, true);
break;
case 13: // addic_rc
regimmop(d, a, true, (u32)(s32)inst.SIMM_16, Add, &XEmitter::ADD, true, true);
break;
default:
FALLBACK_IF(true);
}
}
bool Jit64::CheckMergedBranch(u32 crf) const
{
if (!analyzer.HasOption(PPCAnalyst::PPCAnalyzer::OPTION_BRANCH_MERGE))
return false;
if (!CanMergeNextInstructions(1))
return false;
const UGeckoInstruction& next = js.op[1].inst;
return (((next.OPCD == 16 /* bcx */) ||
((next.OPCD == 19) && (next.SUBOP10 == 528) /* bcctrx */) ||
((next.OPCD == 19) && (next.SUBOP10 == 16) /* bclrx */)) &&
(next.BO & BO_DONT_DECREMENT_FLAG) && !(next.BO & BO_DONT_CHECK_CONDITION) &&
static_cast<u32>(next.BI >> 2) == crf);
}
void Jit64::DoMergedBranch()
{
// Code that handles successful PPC branching.
const UGeckoInstruction& next = js.op[1].inst;
const u32 nextPC = js.op[1].address;
if (next.OPCD == 16) // bcx
{
if (next.LK)
MOV(32, PPCSTATE(spr[SPR_LR]), Imm32(nextPC + 4));
u32 destination;
if (next.AA)
destination = SignExt16(next.BD << 2);
else
destination = nextPC + SignExt16(next.BD << 2);
WriteExit(destination, next.LK, nextPC + 4);
}
else if ((next.OPCD == 19) && (next.SUBOP10 == 528)) // bcctrx
{
if (next.LK)
MOV(32, PPCSTATE(spr[SPR_LR]), Imm32(nextPC + 4));
MOV(32, R(RSCRATCH), PPCSTATE(spr[SPR_CTR]));
AND(32, R(RSCRATCH), Imm32(0xFFFFFFFC));
WriteExitDestInRSCRATCH(next.LK, nextPC + 4);
}
else if ((next.OPCD == 19) && (next.SUBOP10 == 16)) // bclrx
{
MOV(32, R(RSCRATCH), PPCSTATE(spr[SPR_LR]));
if (!m_enable_blr_optimization)
AND(32, R(RSCRATCH), Imm32(0xFFFFFFFC));
if (next.LK)
MOV(32, PPCSTATE(spr[SPR_LR]), Imm32(nextPC + 4));
WriteBLRExit();
}
else
{
PanicAlert("WTF invalid branch");
}
}
void Jit64::DoMergedBranchCondition()
{
js.downcountAmount++;
js.skipInstructions = 1;
const UGeckoInstruction& next = js.op[1].inst;
int test_bit = 8 >> (next.BI & 3);
bool condition = !!(next.BO & BO_BRANCH_IF_TRUE);
const u32 nextPC = js.op[1].address;
ASSERT(gpr.IsAllUnlocked());
FixupBranch pDontBranch;
if (test_bit & 8)
pDontBranch = J_CC(condition ? CC_GE : CC_L, true); // Test < 0, so jump over if >= 0.
else if (test_bit & 4)
pDontBranch = J_CC(condition ? CC_LE : CC_G, true); // Test > 0, so jump over if <= 0.
else if (test_bit & 2)
pDontBranch = J_CC(condition ? CC_NE : CC_E, true); // Test = 0, so jump over if != 0.
else // SO bit, do not branch (we don't emulate SO for cmp).
pDontBranch = J(true);
{
RCForkGuard gpr_guard = gpr.Fork();
RCForkGuard fpr_guard = fpr.Fork();
gpr.Flush();
fpr.Flush();
DoMergedBranch();
}
SetJumpTarget(pDontBranch);
if (!analyzer.HasOption(PPCAnalyst::PPCAnalyzer::OPTION_CONDITIONAL_CONTINUE))
{
gpr.Flush();
fpr.Flush();
WriteExit(nextPC + 4);
}
}
void Jit64::DoMergedBranchImmediate(s64 val)
{
js.downcountAmount++;
js.skipInstructions = 1;
const UGeckoInstruction& next = js.op[1].inst;
int test_bit = 8 >> (next.BI & 3);
bool condition = !!(next.BO & BO_BRANCH_IF_TRUE);
const u32 nextPC = js.op[1].address;
ASSERT(gpr.IsAllUnlocked());
bool branch;
if (test_bit & 8)
branch = condition ? val < 0 : val >= 0;
else if (test_bit & 4)
branch = condition ? val > 0 : val <= 0;
else if (test_bit & 2)
branch = condition ? val == 0 : val != 0;
else // SO bit, do not branch (we don't emulate SO for cmp).
branch = false;
if (branch)
{
gpr.Flush();
fpr.Flush();
DoMergedBranch();
}
else if (!analyzer.HasOption(PPCAnalyst::PPCAnalyzer::OPTION_CONDITIONAL_CONTINUE))
{
gpr.Flush();
fpr.Flush();
WriteExit(nextPC + 4);
}
}
void Jit64::cmpXX(UGeckoInstruction inst)
{
// USES_CR
INSTRUCTION_START
JITDISABLE(bJITIntegerOff);
int a = inst.RA;
int b = inst.RB;
u32 crf = inst.CRFD;
bool merge_branch = CheckMergedBranch(crf);
bool signedCompare;
RCOpArg comparand;
switch (inst.OPCD)
{
// cmp / cmpl
case 31:
signedCompare = (inst.SUBOP10 == 0);
comparand = signedCompare ? gpr.Use(b, RCMode::Read) : gpr.Bind(b, RCMode::Read);
RegCache::Realize(comparand);
break;
// cmpli
case 10:
signedCompare = false;
comparand = RCOpArg::Imm32((u32)inst.UIMM);
break;
// cmpi
case 11:
signedCompare = true;
comparand = RCOpArg::Imm32((u32)(s32)(s16)inst.UIMM);
break;
default:
signedCompare = false; // silence compiler warning
PanicAlert("cmpXX");
}
if (gpr.IsImm(a) && comparand.IsImm())
{
// Both registers contain immediate values, so we can pre-compile the compare result
s64 compareResult = signedCompare ? (s64)gpr.SImm32(a) - (s64)comparand.SImm32() :
(u64)gpr.Imm32(a) - (u64)comparand.Imm32();
if (compareResult == (s32)compareResult)
{
MOV(64, PPCSTATE(cr_val[crf]), Imm32((u32)compareResult));
}
else
{
MOV(64, R(RSCRATCH), Imm64(compareResult));
MOV(64, PPCSTATE(cr_val[crf]), R(RSCRATCH));
}
if (merge_branch)
{
RegCache::Unlock(comparand);
DoMergedBranchImmediate(compareResult);
}
return;
}
if (!gpr.IsImm(a) && !signedCompare && comparand.IsImm() && comparand.Imm32() == 0)
{
RCX64Reg Ra = gpr.Bind(a, RCMode::Read);
RegCache::Realize(Ra);
MOV(64, PPCSTATE(cr_val[crf]), Ra);
if (merge_branch)
{
TEST(64, Ra, Ra);
RegCache::Unlock(comparand, Ra);
DoMergedBranchCondition();
}
return;
}
const X64Reg input = RSCRATCH;
if (gpr.IsImm(a))
{
if (signedCompare)
MOV(64, R(input), Imm32(gpr.SImm32(a)));
else
MOV(32, R(input), Imm32(gpr.Imm32(a)));
}
else
{
RCOpArg Ra = gpr.Use(a, RCMode::Read);
RegCache::Realize(Ra);
if (signedCompare)
MOVSX(64, 32, input, Ra);
else
MOVZX(64, 32, input, Ra);
}
if (comparand.IsImm())
{
// sign extension will ruin this, so store it in a register
if (!signedCompare && (comparand.Imm32() & 0x80000000U) != 0)
{
MOV(32, R(RSCRATCH2), comparand);
comparand = RCOpArg::R(RSCRATCH2);
}
}
else
{
if (signedCompare)
{
MOVSX(64, 32, RSCRATCH2, comparand);
comparand = RCOpArg::R(RSCRATCH2);
}
}
if (comparand.IsImm() && comparand.Imm32() == 0)
{
MOV(64, PPCSTATE(cr_val[crf]), R(input));
// Place the comparison next to the branch for macro-op fusion
if (merge_branch)
TEST(64, R(input), R(input));
}
else
{
SUB(64, R(input), comparand);
MOV(64, PPCSTATE(cr_val[crf]), R(input));
}
if (merge_branch)
{
RegCache::Unlock(comparand);
DoMergedBranchCondition();
}
}
void Jit64::boolX(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITIntegerOff);
int a = inst.RA, s = inst.RS, b = inst.RB;
bool needs_test = false;
DEBUG_ASSERT_MSG(DYNA_REC, inst.OPCD == 31, "Invalid boolX");
if (gpr.IsImm(s, b))
{
const u32 rs_offset = gpr.Imm32(s);
const u32 rb_offset = gpr.Imm32(b);
if (inst.SUBOP10 == 28) // andx
gpr.SetImmediate32(a, rs_offset & rb_offset);
else if (inst.SUBOP10 == 476) // nandx
gpr.SetImmediate32(a, ~(rs_offset & rb_offset));
else if (inst.SUBOP10 == 60) // andcx
gpr.SetImmediate32(a, rs_offset & (~rb_offset));
else if (inst.SUBOP10 == 444) // orx
gpr.SetImmediate32(a, rs_offset | rb_offset);
else if (inst.SUBOP10 == 124) // norx
gpr.SetImmediate32(a, ~(rs_offset | rb_offset));
else if (inst.SUBOP10 == 412) // orcx
gpr.SetImmediate32(a, rs_offset | (~rb_offset));
else if (inst.SUBOP10 == 316) // xorx
gpr.SetImmediate32(a, rs_offset ^ rb_offset);
else if (inst.SUBOP10 == 284) // eqvx
gpr.SetImmediate32(a, ~(rs_offset ^ rb_offset));
}
else if (s == b)
{
if ((inst.SUBOP10 == 28 /* andx */) || (inst.SUBOP10 == 444 /* orx */))
{
if (a != s)
{
RCOpArg Rs = gpr.Use(s, RCMode::Read);
RCX64Reg Ra = gpr.Bind(a, RCMode::Write);
RegCache::Realize(Rs, Ra);
MOV(32, Ra, Rs);
}
else if (inst.Rc)
{
gpr.Bind(a, RCMode::Read).Realize();
}
needs_test = true;
}
else if ((inst.SUBOP10 == 476 /* nandx */) || (inst.SUBOP10 == 124 /* norx */))
{
if (a == s && !inst.Rc)
{
RCOpArg Ra = gpr.UseNoImm(a, RCMode::ReadWrite);
RegCache::Realize(Ra);
NOT(32, Ra);
}
else
{
RCOpArg Rs = gpr.Use(s, RCMode::Read);
RCX64Reg Ra = gpr.Bind(a, RCMode::ReadWrite);
RegCache::Realize(Rs, Ra);
MOV(32, Ra, Rs);
NOT(32, Ra);
}
needs_test = true;
}
else if ((inst.SUBOP10 == 412 /* orcx */) || (inst.SUBOP10 == 284 /* eqvx */))
{
gpr.SetImmediate32(a, 0xFFFFFFFF);
}
else if ((inst.SUBOP10 == 60 /* andcx */) || (inst.SUBOP10 == 316 /* xorx */))
{
gpr.SetImmediate32(a, 0);
}
else
{
PanicAlert("WTF!");
}
}
else if ((a == s) || (a == b))
{
RCOpArg Rb = gpr.Use(b, RCMode::Read);
RCOpArg Rs = gpr.Use(s, RCMode::Read);
RCOpArg operand = gpr.Use(a == s ? b : s, RCMode::Read);
RCX64Reg Ra = gpr.Bind(a, RCMode::ReadWrite);
RegCache::Realize(Rb, Rs, operand, Ra);
if (inst.SUBOP10 == 28) // andx
{
AND(32, Ra, operand);
}
else if (inst.SUBOP10 == 476) // nandx
{
AND(32, Ra, operand);
NOT(32, Ra);
needs_test = true;
}
else if (inst.SUBOP10 == 60) // andcx
{
if (cpu_info.bBMI1 && Rb.IsSimpleReg() && !Rs.IsImm())
{
ANDN(32, Ra, Rb.GetSimpleReg(), Rs);
}
else if (a == b)
{
NOT(32, Ra);
AND(32, Ra, operand);
}
else
{
MOV(32, R(RSCRATCH), operand);
NOT(32, R(RSCRATCH));
AND(32, Ra, R(RSCRATCH));
}
}
else if (inst.SUBOP10 == 444) // orx
{
OR(32, Ra, operand);
}
else if (inst.SUBOP10 == 124) // norx
{
OR(32, Ra, operand);
NOT(32, Ra);
needs_test = true;
}
else if (inst.SUBOP10 == 412) // orcx
{
if (a == b)
{
NOT(32, Ra);
OR(32, Ra, operand);
}
else
{
MOV(32, R(RSCRATCH), operand);
NOT(32, R(RSCRATCH));
OR(32, Ra, R(RSCRATCH));
}
}
else if (inst.SUBOP10 == 316) // xorx
{
XOR(32, Ra, operand);
}
else if (inst.SUBOP10 == 284) // eqvx
{
NOT(32, Ra);
XOR(32, Ra, operand);
}
else
{
PanicAlert("WTF");
}
}
else
{
RCOpArg Rb = gpr.Use(b, RCMode::Read);
RCOpArg Rs = gpr.Use(s, RCMode::Read);
RCX64Reg Ra = gpr.Bind(a, RCMode::Write);
RegCache::Realize(Rb, Rs, Ra);
if (inst.SUBOP10 == 28) // andx
{
MOV(32, Ra, Rs);
AND(32, Ra, Rb);
}
else if (inst.SUBOP10 == 476) // nandx
{
MOV(32, Ra, Rs);
AND(32, Ra, Rb);
NOT(32, Ra);
needs_test = true;
}
else if (inst.SUBOP10 == 60) // andcx
{
if (cpu_info.bBMI1 && Rb.IsSimpleReg() && !Rs.IsImm())
{
ANDN(32, Ra, Rb.GetSimpleReg(), Rs);
}
else
{
MOV(32, Ra, Rb);
NOT(32, Ra);
AND(32, Ra, Rs);
}
}
else if (inst.SUBOP10 == 444) // orx
{
MOV(32, Ra, Rs);
OR(32, Ra, Rb);
}
else if (inst.SUBOP10 == 124) // norx
{
MOV(32, Ra, Rs);
OR(32, Ra, Rb);
NOT(32, Ra);
needs_test = true;
}
else if (inst.SUBOP10 == 412) // orcx
{
MOV(32, Ra, Rb);
NOT(32, Ra);
OR(32, Ra, Rs);
}
else if (inst.SUBOP10 == 316) // xorx
{
MOV(32, Ra, Rs);
XOR(32, Ra, Rb);
}
else if (inst.SUBOP10 == 284) // eqvx
{
MOV(32, Ra, Rs);
NOT(32, Ra);
XOR(32, Ra, Rb);
}
else
{
PanicAlert("WTF!");
}
}
if (inst.Rc)
ComputeRC(a, needs_test);
}
void Jit64::extsXx(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITIntegerOff);
int a = inst.RA, s = inst.RS;
int size = inst.SUBOP10 == 922 ? 16 : 8;
if (gpr.IsImm(s))
{
gpr.SetImmediate32(a, (u32)(s32)(size == 16 ? (s16)gpr.Imm32(s) : (s8)gpr.Imm32(s)));
}
else
{
RCOpArg Rs = gpr.Use(s, RCMode::Read);
RCX64Reg Ra = gpr.Bind(a, RCMode::Write);
RegCache::Realize(Rs, Ra);
MOVSX(32, size, Ra, Rs);
}
if (inst.Rc)
ComputeRC(a);
}
void Jit64::subfic(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITIntegerOff);
int a = inst.RA, d = inst.RD;
RCOpArg Ra = gpr.Use(a, RCMode::Read);
RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rd);
int imm = inst.SIMM_16;
if (d == a)
{
if (imm == 0)
{
// Flags act exactly like subtracting from 0
NEG(32, Rd);
// Output carry is inverted
FinalizeCarry(CC_NC);
}
else if (imm == -1)
{
NOT(32, Rd);
// CA is always set in this case
FinalizeCarry(true);
}
else
{
NOT(32, Rd);
ADD(32, Rd, Imm32(imm + 1));
// Output carry is normal
FinalizeCarry(CC_C);
}
}
else
{
MOV(32, Rd, Imm32(imm));
SUB(32, Rd, Ra);
// Output carry is inverted
FinalizeCarry(CC_NC);
}
// This instruction has no RC flag
}
void Jit64::subfx(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITIntegerOff);
int a = inst.RA, b = inst.RB, d = inst.RD;
if (gpr.IsImm(a) && gpr.IsImm(b))
{
s32 i = gpr.SImm32(b), j = gpr.SImm32(a);
gpr.SetImmediate32(d, i - j);
if (inst.OE)
GenerateConstantOverflow((s64)i - (s64)j);
}
else
{
RCOpArg Ra = gpr.Use(a, RCMode::Read);
RCOpArg Rb = gpr.Use(b, RCMode::Read);
RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rb, Rd);
if (d == b)
{
SUB(32, Rd, Ra);
}
else if (d == a)
{
MOV(32, R(RSCRATCH), Ra);
MOV(32, Rd, Rb);
SUB(32, Rd, R(RSCRATCH));
}
else
{
MOV(32, Rd, Rb);
SUB(32, Rd, Ra);
}
if (inst.OE)
GenerateOverflow();
}
if (inst.Rc)
ComputeRC(d);
}
void Jit64::MultiplyImmediate(u32 imm, int a, int d, bool overflow)
{
RCOpArg Ra = gpr.Use(a, RCMode::Read);
RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rd);
// simplest cases first
if (imm == 0)
{
XOR(32, Rd, Rd);
return;
}
if (imm == (u32)-1)
{
if (d != a)
MOV(32, Rd, Ra);
NEG(32, Rd);
return;
}