Pinned

1. Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm Public

   The Dark Channel Prior technique is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA …

   Verilog 19 2

2. Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm Public

   The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPG…

   Verilog 21

3. RSA2048 RSA2048 Public

   Verilog 7 1

4. Video-Stitching-Using-FPGA Video-Stitching-Using-FPGA Public

   Verilog 4

5. AXIS-AXI4-AXIS AXIS-AXI4-AXIS Public

   This project is designed to delay the output of the video stream in AXI-STREAM format.

   Verilog 4

6. AVS3-RDOQ AVS3-RDOQ Public

   SystemVerilog 1