Signal fanout

[drom]

Question:
From @wavedrom group topic: https://groups.google.com/d/topic/wavedrom/iqTKBLl6mYU/discussion

Can some tell me how to make a driver gate to drive multiple gates in the next level with replication of the driver gate.
For example:
Level 0 : AND GATE
Level 1: 3 Inverters driven by the same AND GATE

Answer:
Current engine renders only tree forest structures. So, signal fanout will not be visualized.
Naming the signals with the same name will help user to navigate, but no line will appear on the schematic.

[drom]

TODO:

• scope all the cases
• sketch the cases
• appropriate grid design
• routing algorithm

[drom]

Case 1: single wire in a single sharing column. (Do we need to extend "a" ?)

{ assign: [
  ["out", ["&", "a", "b", "b"]]
]}

Case 2: multiple wires in a sharing column.

{ assign: [
  ["out", ["&", "a", "b", "a", "c", "b"]]
]}

Case 3: Horizontal extenders for wires crossing the sharing column.

{ assign: [
  ["out", ["^", "a", ["^", "b", ["^", "c", "a"]]]]
]}

Case 4: XOR

{ assign: [
  ["out",
    ['|',
      ["&", ["~", "a"], "b"],
      ["&", "a", ["~", "b"]]
    ]
  ]
]}

Case 5: Half Adder. Sharing between the trees. Fanout > 2

{ assign: [
  ["out",
    ['|',
      ["&", ["~", "a"], "b"],
      ["&", "a", ["~", "b"]]
    ]
  ],
  ["carry", ["&", "a", "b"]]
]}

Case 6: Sharing column with minimized line crossings, or minimized number of vertical lanes.

{ assign: [
  ["out",
    ['|',
      ["&", "a", "b"],
      ["&", "b", "c"],
      ["&", "a", "c"]
    ]
  ]
]}

Case 7: MUX4

{ assign: [
  ["a",
    ['|',
      ["&", ["~", "s0"], ["~", "s1"], "e0"],
      ["&", ["~", "s0"], "s1", "e1"],
      ["&", "s0", ["~", "s1"], "e2"],
      ["&", "s0", "s1", "e3"]
    ]
  ]
]}

[DmitryAGusev]

Comment to the initial question. Is it possible to add unique tag/id/name to the block, or assign a name to the output signal of any block (not only for global output)? If so, task becomes the same as for input signals in examples above.

[drom]

ok, you are right @DmitryAGusev . My pictures above have not addressed the original question. How about next example as the possible solution?

{ assign: [
  ["a",
    ['|',
      ["&", ["!s0", ["~", "s0"]], ["!s1", ["~", "s1"]], "e0"],
      ["&", "!s0", "s1", "e1"],
      ["&", "s0", "!s1", "e2"],
      ["&", "s0", "s1", "e3"]
    ]
  ]
]}

[DmitryAGusev]

Yes, this is what I meant. It will be nice to add the ability to suppress the showing of intermediate names like !s0, !s1. I.e. by using another quotes '!s1' instead of "!s1". And the same for input signal names, sometimes some of them are not important to be shown, i.e. for highlighting critical paths.

[drom]

Another important question is: How to render connect between multiple expressions? Sort of MIMO case.

Gray to Binary example:

{ assign:[
  ["b3", "g3"],
  ["b2", ["^", "b3", "g2"]],
  ["b1", ["^", "b2", "g1"]],
  ["b0", ["^", "b1", "g0"]]
]}

{
  b3 = g3
  b2 = b3 ^ g2
  b1 = b2 ^ g1
  b0 = b1 ^ g0
}

[DmitryAGusev]

It looks like the structure {assign: [ ]} should define some kind of name space. All signals within this space with similar names should be connected (unless it is suppressed explicitly by some option/flag). Two output signals with similar names cause an error. Multiple intermediate inputs can be connected to one intermediate output signal or one global input signal.

[drom]

That is correct. We have to think about the temporal variable scoping. Especially, if we going to use multiple scopes (namespaces), or / and nested scoping.