/
Instruction.C
661 lines (594 loc) · 22.5 KB
/
Instruction.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
/*
* See the dyninst/COPYRIGHT file for copyright information.
*
* We provide the Paradyn Tools (below described as "Paradyn")
* on an AS IS basis, and do not warrant its validity or performance.
* We reserve the right to update, modify, or discontinue this
* software at any time. We shall have no obligation to supply such
* updates or modifications or any other form of support to you.
*
* By your use of Paradyn, you understand and agree that we (or any
* other person or entity with proprietary rights in Paradyn) are
* under no obligation to provide either maintenance services,
* update services, notices of latent defects, or correction of
* defects for Paradyn.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define INSIDE_INSTRUCTION_API
#include <stdio.h>
#include <string>
#include <signal.h>
#include "../h/InstructionCategories.h"
#include "../h/Instruction.h"
#include "../h/Register.h"
#include "Operation_impl.h"
#include "InstructionDecoder.h"
#include "Dereference.h"
#include <boost/iterator/indirect_iterator.hpp>
#include <iostream>
#include <sstream>
#include <iomanip>
#include <set>
#include <functional>
#include <algorithm>
#include "common/src/arch-x86.h"
#include "dyninstversion.h"
using namespace std;
using namespace NS_x86;
#include "../../common/src/singleton_object_pool.h"
#include "ArchSpecificFormatters.h"
#define DECODE_OPERANDS() \
do { \
if (arch_decoded_from != Arch_cuda && arch_decoded_from != Arch_amdgpu_gfx908 && arch_decoded_from != Arch_amdgpu_gfx90a && arch_decoded_from != Arch_amdgpu_gfx940 && m_Operands.empty()) { \
decodeOperands(); \
}\
}while(0)
namespace Dyninst
{
namespace InstructionAPI
{
static const int IAPI_major_version = DYNINST_MAJOR_VERSION;
static const int IAPI_minor_version = DYNINST_MINOR_VERSION;
static const int IAPI_maintenance_version = DYNINST_PATCH_VERSION;
void Instruction::version(int& major, int& minor, int& maintenance)
{
major = IAPI_major_version;
minor = IAPI_minor_version;
maintenance = IAPI_maintenance_version;
}
int Instruction::numInsnsAllocated = 0;
INSTRUCTION_EXPORT Instruction::Instruction(Operation what,
size_t size, const unsigned char* raw,
Dyninst::Architecture arch)
: m_InsnOp(what), m_Valid(what.getID() != e_No_Entry), arch_decoded_from(arch),
formatter(&ArchSpecificFormatter::getFormatter(arch))
{
copyRaw(size, raw);
#if defined(DEBUG_INSN_ALLOCATIONS)
numInsnsAllocated++;
if((numInsnsAllocated % 1000) == 0)
{
fprintf(stderr, "Instruction CTOR, %d insns allocated\n", numInsnsAllocated);
}
#endif
}
void Instruction::copyRaw(size_t size, const unsigned char* raw)
{
if(raw)
{
m_size = size;
m_RawInsn.small_insn = 0;
if(size <= sizeof(m_RawInsn.small_insn))
{
memcpy(&m_RawInsn.small_insn, raw, size);
}
else
{
m_RawInsn.large_insn = new unsigned char[size];
memcpy(m_RawInsn.large_insn, raw, size);
}
}
else
{
m_size = 0;
m_RawInsn.small_insn = 0;
}
}
void Instruction::decodeOperands() const
{
if (!m_Valid) return;
//m_Operands.reserve(5);
InstructionDecoder dec(ptr(), size(), arch_decoded_from);
dec.doDelayedDecode(this);
}
INSTRUCTION_EXPORT Instruction::Instruction() :
m_Valid(false), m_size(0), arch_decoded_from(Arch_none), formatter(nullptr)
{
#if defined(DEBUG_INSN_ALLOCATIONS)
numInsnsAllocated++;
if((numInsnsAllocated % 1000) == 0)
{
fprintf(stderr, "Instruction CTOR, %d insns allocated\n", numInsnsAllocated);
}
#endif
}
INSTRUCTION_EXPORT Instruction::~Instruction()
{
if(m_size > sizeof(m_RawInsn.small_insn))
{
delete[] m_RawInsn.large_insn;
}
#if defined(DEBUG_INSN_ALLOCATIONS)
numInsnsAllocated--;
if((numInsnsAllocated % 1000) == 0)
{
fprintf(stderr, "Instruction DTOR, %d insns allocated\n", numInsnsAllocated);
}
#endif
}
INSTRUCTION_EXPORT Instruction::Instruction(const Instruction& o) :
m_Operands(o.m_Operands),
m_InsnOp(o.m_InsnOp),
m_Valid(o.m_Valid),
arch_decoded_from(o.arch_decoded_from),
formatter(o.formatter)
{
m_size = o.m_size;
if(o.m_size > sizeof(m_RawInsn.small_insn))
{
m_RawInsn.large_insn = new unsigned char[o.m_size];
memcpy(m_RawInsn.large_insn, o.m_RawInsn.large_insn, m_size);
}
else
{
m_RawInsn.small_insn = o.m_RawInsn.small_insn;
}
m_Successors = o.m_Successors;
#if defined(DEBUG_INSN_ALLOCATIONS)
numInsnsAllocated++;
if((numInsnsAllocated % 1000) == 0)
{
fprintf(stderr, "Instruction COPY CTOR, %d insns allocated\n", numInsnsAllocated);
}
#endif
}
INSTRUCTION_EXPORT const Instruction& Instruction::operator=(const Instruction& rhs)
{
m_Operands = rhs.m_Operands;
//m_Operands.reserve(rhs.m_Operands.size());
//std::copy(rhs.m_Operands.begin(), rhs.m_Operands.end(), std::back_inserter(m_Operands));
if(m_size > sizeof(m_RawInsn.small_insn))
{
delete[] m_RawInsn.large_insn;
}
m_size = rhs.m_size;
if(rhs.m_size > sizeof(m_RawInsn.small_insn))
{
m_RawInsn.large_insn = new unsigned char[rhs.m_size];
memcpy(m_RawInsn.large_insn, rhs.m_RawInsn.large_insn, m_size);
}
else
{
m_RawInsn.small_insn = rhs.m_RawInsn.small_insn;
}
m_InsnOp = rhs.m_InsnOp;
m_Valid = rhs.m_Valid;
formatter = rhs.formatter;
arch_decoded_from = rhs.arch_decoded_from;
m_Successors = rhs.m_Successors;
return *this;
}
INSTRUCTION_EXPORT bool Instruction::isValid() const
{
return m_Valid;
}
INSTRUCTION_EXPORT Operation& Instruction::getOperation()
{
return m_InsnOp;
}
INSTRUCTION_EXPORT const Operation& Instruction::getOperation() const
{
return m_InsnOp;
}
INSTRUCTION_EXPORT void Instruction::getOperands(std::vector<Operand>& operands) const
{
DECODE_OPERANDS();
std::copy(m_Operands.begin(), m_Operands.end(), std::back_inserter(operands));
}
INSTRUCTION_EXPORT std::vector<Operand> Instruction::getDisplayOrderedOperands() const
{
DECODE_OPERANDS();
std::vector<Operand> operands;
auto operandsInserter{std::back_inserter(operands)};
auto isNotImplicitPred = [](const Operand & x){return !x.isImplicit();};
if (formatter->operandPrintOrderReversed()) {
copy_if(m_Operands.crbegin(), m_Operands.crend(), operandsInserter, isNotImplicitPred);
} else {
copy_if(m_Operands.cbegin(), m_Operands.cend(), operandsInserter, isNotImplicitPred);
}
return operands;
}
INSTRUCTION_EXPORT Operand Instruction::getOperand(int index) const
{
DECODE_OPERANDS();
if(index < 0 || index >= (int)(m_Operands.size()))
{
// Out of range = empty operand
return Operand(Expression::Ptr(), false, false);
}
std::list<Operand>::const_iterator found = m_Operands.begin();
std::advance(found, index);
return *found;
}
INSTRUCTION_EXPORT const void* Instruction::ptr() const
{
if(m_size > sizeof(m_RawInsn.small_insn))
{
return m_RawInsn.large_insn;
}
else
{
return reinterpret_cast<const void*>(&m_RawInsn.small_insn);
}
}
INSTRUCTION_EXPORT unsigned char Instruction::rawByte(unsigned int index) const
{
if(index >= m_size) return 0;
if(m_size > sizeof(m_RawInsn.small_insn))
{
return m_RawInsn.large_insn[index];
}
else
{
return reinterpret_cast<const unsigned char*>(&m_RawInsn.small_insn)[index];
}
}
INSTRUCTION_EXPORT size_t Instruction::size() const
{
return m_size;
}
INSTRUCTION_EXPORT void Instruction::getReadSet(std::set<RegisterAST::Ptr>& regsRead) const
{
DECODE_OPERANDS();
for(std::list<Operand>::const_iterator curOperand = m_Operands.begin();
curOperand != m_Operands.end();
++curOperand)
{
curOperand->getReadSet(regsRead);
}
std::copy(m_InsnOp.implicitReads().begin(), m_InsnOp.implicitReads().end(),
std::inserter(regsRead, regsRead.begin()));
}
INSTRUCTION_EXPORT void Instruction::getWriteSet(std::set<RegisterAST::Ptr>& regsWritten) const
{
DECODE_OPERANDS();
for(std::list<Operand>::const_iterator curOperand = m_Operands.begin();
curOperand != m_Operands.end();
++curOperand)
{
curOperand->getWriteSet(regsWritten);
}
std::copy(m_InsnOp.implicitWrites().begin(), m_InsnOp.implicitWrites().end(),
std::inserter(regsWritten, regsWritten.begin()));
}
INSTRUCTION_EXPORT bool Instruction::isRead(Expression::Ptr candidate) const
{
DECODE_OPERANDS();
for(std::list<Operand >::const_iterator curOperand = m_Operands.begin();
curOperand != m_Operands.end();
++curOperand)
{
// Check if the candidate is read as an explicit operand
if(curOperand->isRead(candidate))
{
return true;
}
}
// Check if the candidate is read as an implicit operand
return m_InsnOp.isRead(candidate);
}
INSTRUCTION_EXPORT bool Instruction::isWritten(Expression::Ptr candidate) const
{
DECODE_OPERANDS();
for(std::list<Operand>::const_iterator curOperand = m_Operands.begin();
curOperand != m_Operands.end();
++curOperand)
{
if(curOperand->isWritten(candidate))
{
return true;
}
}
return m_InsnOp.isWritten(candidate);
}
INSTRUCTION_EXPORT bool Instruction::readsMemory() const
{
DECODE_OPERANDS();
if(getCategory() == c_PrefetchInsn)
{
return false;
}
for(std::list<Operand>::const_iterator curOperand = m_Operands.begin();
curOperand != m_Operands.end();
++curOperand)
{
if(curOperand->readsMemory())
{
return true;
}
}
return !m_InsnOp.getImplicitMemReads().empty();
}
INSTRUCTION_EXPORT bool Instruction::writesMemory() const
{
DECODE_OPERANDS();
for(std::list<Operand>::const_iterator curOperand = m_Operands.begin();
curOperand != m_Operands.end();
++curOperand)
{
if(curOperand->writesMemory())
{
return true;
}
}
return !m_InsnOp.getImplicitMemWrites().empty();
}
INSTRUCTION_EXPORT void Instruction::getMemoryReadOperands(std::set<Expression::Ptr>& memAccessors) const
{
DECODE_OPERANDS();
for(std::list<Operand>::const_iterator curOperand = m_Operands.begin();
curOperand != m_Operands.end();
++curOperand)
{
curOperand->addEffectiveReadAddresses(memAccessors);
}
std::copy(m_InsnOp.getImplicitMemReads().begin(), m_InsnOp.getImplicitMemReads().end(), std::inserter(memAccessors,
memAccessors.begin()));
}
INSTRUCTION_EXPORT void Instruction::getMemoryWriteOperands(std::set<Expression::Ptr>& memAccessors) const
{
DECODE_OPERANDS();
for(std::list<Operand>::const_iterator curOperand = m_Operands.begin();
curOperand != m_Operands.end();
++curOperand)
{
curOperand->addEffectiveWriteAddresses(memAccessors);
}
std::copy(m_InsnOp.getImplicitMemWrites().begin(), m_InsnOp.getImplicitMemWrites().end(), std::inserter(memAccessors,
memAccessors.begin()));
}
INSTRUCTION_EXPORT Operand Instruction::getPredicateOperand() const
{
DECODE_OPERANDS();
for(auto const &op : m_Operands) {
if (op.isTruePredicate() || op.isFalsePredicate()) {
return op;
}
}
return Operand(Expression::Ptr(), false, false);
}
INSTRUCTION_EXPORT bool Instruction::hasPredicateOperand() const
{
DECODE_OPERANDS();
for(auto const &op : m_Operands) {
if (op.isTruePredicate() || op.isFalsePredicate()) {
return true;
}
}
return false;
}
INSTRUCTION_EXPORT Expression::Ptr Instruction::getControlFlowTarget() const
{
// We assume control flow transfer instructions have the PC as
// an implicit write, and that we have decoded the control flow
// target's full location as the first and only operand.
// If this is not the case, we'll squawk for the time being...
if(getCategory() == c_NoCategory ||
getCategory() == c_CompareInsn ||
getCategory() == c_PrefetchInsn)
{
return Expression::Ptr();
}
if(getCategory() == c_ReturnInsn)
{
return makeReturnExpression();
}
DECODE_OPERANDS();
if(m_Successors.empty())
{
return Expression::Ptr();
}
return m_Successors.front().target;
}
INSTRUCTION_EXPORT ArchSpecificFormatter& Instruction::getFormatter() const {
return *formatter;
}
INSTRUCTION_EXPORT std::string Instruction::format(Address addr) const
{
// if Arch_none, this is an error and the formatter is nullptr,
// so return an error string (could also abort or except)
if (arch_decoded_from == Arch_none) {
return "ERROR_NO_ARCH_SET_FOR_INSTRUCTION";
}
DECODE_OPERANDS();
//remove this once ArchSpecificFormatter is extended for all architectures
std::string opstr = m_InsnOp.format();
opstr += " ";
std::list<Operand>::const_iterator currOperand;
std::vector<std::string> formattedOperands;
for(currOperand = m_Operands.begin();
currOperand != m_Operands.end();
++currOperand)
{
/* If this operand is implicit, don't put it in the list of operands. */
if(currOperand->isImplicit())
continue;
formattedOperands.push_back(currOperand->format(getArch(), addr));
}
#if defined(DEBUG_READ_WRITE)
std::set<RegisterAST::Ptr> tmp;
getReadSet(tmp);
cout << "Read set:" << endl;
for(std::set<RegisterAST::Ptr>::iterator i = tmp.begin();
i != tmp.end();
++i)
{
cout << (*i)->format() << " ";
}
cout << endl;
tmp.clear();
getWriteSet(tmp);
cout << "Write set:" << endl;
for(std::set<RegisterAST::Ptr>::iterator i = tmp.begin();
i != tmp.end();
++i)
{
cout << (*i)->format() << " ";
}
cout << endl;
std::set<Expression::Ptr> mem;
getMemoryReadOperands(mem);
cout << "Read mem:" << endl;
for(std::set<Expression::Ptr>::iterator i = mem.begin();
i != mem.end();
++i)
{
cout << (*i)->format() << " ";
}
cout << endl;
mem.clear();
getMemoryWriteOperands(mem);
cout << "Write mem:" << endl;
for(std::set<Expression::Ptr>::iterator i = mem.begin();
i != mem.end();
++i)
{
cout << (*i)->format() << " ";
}
cout << endl;
#endif // defined(DEBUG_READ_WRITE)
return opstr + formatter->getInstructionString(formattedOperands);
}
INSTRUCTION_EXPORT bool Instruction::allowsFallThrough() const
{
switch(m_InsnOp.getID())
{
case e_ret_far:
case e_ret_near:
case e_iret:
case e_jmp:
case e_hlt:
case e_sysret:
case e_sysexit:
case e_call:
case e_syscall:
case amdgpu_gfx908_op_S_SETPC_B64:
case amdgpu_gfx908_op_S_SWAPPC_B64:
case amdgpu_gfx90a_op_S_SETPC_B64:
case amdgpu_gfx90a_op_S_SWAPPC_B64:
case amdgpu_gfx940_op_S_SETPC_B64:
case amdgpu_gfx940_op_S_SWAPPC_B64:
return false;
case e_jae:
case e_jb:
case e_jb_jnaej_j:
case e_jbe:
case e_jcxz_jec:
case e_jl:
case e_jle:
case e_jnb_jae_j:
case e_ja:
case e_jge:
case e_jg:
case e_jno:
case e_jnp:
case e_jns:
case e_jne:
case e_jo:
case e_jp:
case e_js:
case e_je:
return true;
default:
{
DECODE_OPERANDS();
for(cftConstIter targ = m_Successors.begin();
targ != m_Successors.end();
++targ)
{
if(targ->isFallthrough) return true;
}
return m_Successors.empty();
}
}
// can't happen but make the compiler happy
return false;
}
INSTRUCTION_EXPORT bool Instruction::isLegalInsn() const
{
return (m_InsnOp.getID() != e_No_Entry);
}
INSTRUCTION_EXPORT Architecture Instruction::getArch() const {
return arch_decoded_from;
}
Expression::Ptr Instruction::makeReturnExpression() const
{
Expression::Ptr stackPtr = Expression::Ptr(new RegisterAST(MachRegister::getStackPointer(arch_decoded_from),
0, MachRegister::getStackPointer(arch_decoded_from).size()));
Expression::Ptr retLoc = Expression::Ptr(new Dereference(stackPtr, u32));
return retLoc;
}
INSTRUCTION_EXPORT InsnCategory Instruction::getCategory() const
{
if(m_InsnOp.isVectorInsn) return c_VectorInsn;
InsnCategory c = entryToCategory(m_InsnOp.getID());
if(c == c_BranchInsn && (arch_decoded_from == Arch_ppc32 || arch_decoded_from == Arch_ppc64))
{
DECODE_OPERANDS();
for(cftConstIter cft = cft_begin();
cft != cft_end();
++cft)
{
if(cft->isCall)
{
return c_CallInsn;
}
}
if(m_InsnOp.getID() == power_op_bclr)
{
return c_ReturnInsn;
}
}
return c;
}
void Instruction::addSuccessor(Expression::Ptr e,
bool isCall,
bool isIndirect,
bool isConditional,
bool isFallthrough,
bool isImplicit) const
{
CFT c(e, isCall, isIndirect, isConditional, isFallthrough);
m_Successors.push_back(c);
if (!isFallthrough) appendOperand(e, true, false, isImplicit);
}
void Instruction::appendOperand(Expression::Ptr e,
bool isRead, bool isWritten, bool isImplicit, bool trueP, bool falseP) const
{
m_Operands.push_back(Operand(e, isRead, isWritten, isImplicit, trueP, falseP));
}
}
}