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InstructionDecoder-aarch64.C
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InstructionDecoder-aarch64.C
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/*
* See the dyninst/COPYRIGHT file for copyright information.
*
* We provide the Paradyn Tools (below described as "Paradyn")
* on an AS IS basis, and do not warrant its validity or performance.
* We reserve the right to update, modify, or discontinue this
* software at any time. We shall have no obligation to supply such
* updates or modifications or any other form of support to you.
*
* By your use of Paradyn, you understand and agree that we (or any
* other person or entity with proprietary rights in Paradyn) are
* under no obligation to provide either maintenance services,
* update services, notices of latent defects, or correction of
* defects for Paradyn.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "InstructionDecoder-aarch64.h"
#include <boost/assign/list_of.hpp>
#include "../../common/src/singleton_object_pool.h"
namespace Dyninst {
namespace InstructionAPI {
typedef void (InstructionDecoder_aarch64::*operandFactory)();
typedef std::vector<operandFactory> operandSpec;
typedef std::vector<aarch64_insn_entry> aarch64_insn_table;
typedef std::map<unsigned int, aarch64_mask_entry> aarch64_decoder_table;
typedef std::map<unsigned int, unsigned int> branchMap;
typedef uint32_t Bits_t;
std::vector<std::string> InstructionDecoder_aarch64::condStringMap;
std::map<unsigned int, MachRegister> InstructionDecoder_aarch64::sysRegMap;
std::map<entryID, std::string> InstructionDecoder_aarch64::bitfieldInsnAliasMap = boost::assign::map_list_of(
aarch64_op_bfi_bfm, "bfi")(aarch64_op_bfxil_bfm, "bfxil")(aarch64_op_sbfiz_sbfm, "sbfiz")(
aarch64_op_sbfx_sbfm, "sbfx")(aarch64_op_ubfiz_ubfm, "ubfiz")(aarch64_op_ubfx_ubfm, "ubfx")(
aarch64_op_sxtb_sbfm, "sxtb")(aarch64_op_sxth_sbfm, "sxth")(aarch64_op_sxtw_sbfm, "sxtw")(
aarch64_op_uxtb_ubfm, "uxtb")(aarch64_op_uxth_ubfm, "uxth")(aarch64_op_lsl_ubfm, "lsl")(aarch64_op_lsr_ubfm, "lsr");
std::map<entryID, std::string> InstructionDecoder_aarch64::condInsnAliasMap = boost::assign::map_list_of(aarch64_op_csinc, "csinc")(aarch64_op_csinv, "csinv")(aarch64_op_csneg, "csneg")
(aarch64_op_cinc_csinc, "cinc")(aarch64_op_cset_csinc, "cset")
(aarch64_op_cinv_csinv, "cinv")(aarch64_op_csetm_csinv, "csetm")
(aarch64_op_cneg_csneg, "cneg");
struct aarch64_insn_entry {
aarch64_insn_entry(entryID o, const char *m, operandSpec ops) :
op(o), mnemonic(m), operands(ops) {
}
aarch64_insn_entry(entryID o, const char *m, operandSpec ops, Bits_t enb, Bits_t mb) :
op(o), mnemonic(m), operands(ops), _encodingBits(enb), _maskBits(mb) {
}
aarch64_insn_entry() :
op(aarch64_op_INVALID), mnemonic("INVALID") {
operands.reserve(5);
}
aarch64_insn_entry(const aarch64_insn_entry &o) :
op(o.op), mnemonic(o.mnemonic), operands(o.operands),
_encodingBits(o._encodingBits), _maskBits(o._maskBits) {
}
const aarch64_insn_entry &operator=(const aarch64_insn_entry &rhs) {
operands.reserve(rhs.operands.size());
op = rhs.op;
mnemonic = rhs.mnemonic;
operands = rhs.operands;
_encodingBits = rhs._encodingBits;
_maskBits = rhs._maskBits;
return *this;
}
entryID op;
const char *mnemonic;
operandSpec operands;
Bits_t _encodingBits;
Bits_t _maskBits;
static void buildInsnTable();
static bool built_insn_table;
static aarch64_insn_table main_insn_table;
};
struct aarch64_mask_entry {
aarch64_mask_entry(unsigned int m, branchMap bm, int tabIndex) :
mask(m), nodeBranches(bm), insnTableIndices(std::vector<int>()), insnTableIndex(tabIndex) {
}
aarch64_mask_entry(unsigned int m, branchMap bm, std::vector<int> tabIndices) :
mask(m), nodeBranches(bm), insnTableIndices(tabIndices), insnTableIndex(0) {
}
aarch64_mask_entry() :
mask(0), nodeBranches(branchMap()), insnTableIndices(std::vector<int>()), insnTableIndex(0) {
}
aarch64_mask_entry(const aarch64_mask_entry &e) :
mask(e.mask), nodeBranches(e.nodeBranches), insnTableIndices(e.insnTableIndices),
insnTableIndex(e.insnTableIndex) {
}
const aarch64_mask_entry &operator=(const aarch64_mask_entry &rhs) {
mask = rhs.mask;
nodeBranches = rhs.nodeBranches;
insnTableIndices = rhs.insnTableIndices;
insnTableIndex = rhs.insnTableIndex;
return *this;
}
unsigned int mask;
branchMap nodeBranches;
std::vector<int> insnTableIndices;
int insnTableIndex;
static void buildDecoderTable();
static bool built_decoder_table;
static bool isAliasWeakSolution;
static aarch64_decoder_table main_decoder_table;
};
InstructionDecoder_aarch64::InstructionDecoder_aarch64(Architecture a)
: InstructionDecoderImpl(a), isPstateRead(false), isPstateWritten(false), isFPInsn(false),
isSIMDInsn(false), skipRn(false), skipRm(false),
is64Bit(true), isValid(true), insn(0), insn_in_progress(NULL),
hasHw(false), hasShift(false), hasOption(false), hasN(false),
immr(0), immrLen(0), sField(0), nField(0), nLen(0),
immlo(0), immloLen(0), _szField(-1), _Q(1), size(-1),
cmode(0), op(0), simdAlphabetImm(0) {
aarch64_insn_entry::buildInsnTable();
aarch64_mask_entry::buildDecoderTable();
InstructionDecoder_aarch64::buildSysRegMap();
std::string condArray[16] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt",
"le", "al", "nv"};
InstructionDecoder_aarch64::condStringMap.assign(&condArray[0], &condArray[0] + 16);
//InstructionDecoder_aarch64::bitfieldInsnAliasMap = boost::assign::map_list_of(aarch64_op_bfi_bfm, "bfi")(aarch64_op_bfxil_bfm, "bfxil")(aarch64_op_sbfiz_sbfm, "sbfiz")(aarch64_op_sbfx_sbfm, "sbfx")(aarch64_op_ubfiz_ubfm, "ubfiz")(aarch64_op_ubfx_ubfm, "ubfx");
}
InstructionDecoder_aarch64::~InstructionDecoder_aarch64() {
}
void InstructionDecoder_aarch64::decodeOpcode(InstructionDecoder::buffer &b) {
b.start += 4;
}
using namespace std;
Instruction::Ptr InstructionDecoder_aarch64::decode(InstructionDecoder::buffer &b) {
if (b.start > b.end)
return Instruction::Ptr();
isPstateRead = isPstateWritten = false;
isFPInsn = false;
isSIMDInsn = false;
skipRm = skipRn = false;
isValid = true;
is64Bit = true;
hasHw = false;
hwField = 0;
hasShift = false;
shiftField = 0;
hasOption = false;
optionField = 0;
hasN = false;
sField = nField = nLen = 0;
immr = immrLen = 0;
op1Field = op2Field = crmField = 0;
immlo = immloLen = 0;
_szField = size = -1;
_Q = 1;
cmode = op = simdAlphabetImm = 0;
oprRotateAmt = 0;
hasb5 = false;
insn = b.start[3] << 24 | b.start[2] << 16 |
b.start[1] << 8 | b.start[0];
#if defined(DEBUG_RAW_INSN)
cout.width(0);
cout << "0x";
cout.width(8);
cout.fill('0');
cout << hex << insn << "\t";
#endif
mainDecode();
b.start += 4;
return make_shared(insn_in_progress);
}
/* replace this function with a more generic function, which is setRegWidth
void InstructionDecoder_aarch64::set32Mode()
{
// NOTE: is64Bit is set by default.
is64Bit = false;
}
*/
void InstructionDecoder_aarch64::NOTHING() {
}
void InstructionDecoder_aarch64::setFPMode() {
// NOTE: if it is fp, only isFP is set.
isFPInsn = true;
}
//TODO: consistency issue
void InstructionDecoder_aarch64::setSIMDMode() {
// NOTE: if it is SIMD insn, both isFP and isSIMD are set.
//isFPInsn = true;
isSIMDInsn = true;
}
template<unsigned int endBit, unsigned int startBit>
void InstructionDecoder_aarch64::OPRtype() {
_typeField = field<startBit, endBit>(insn);
}
void InstructionDecoder_aarch64::processHwFieldInsn(int len, int val) {
Result_Type rT = is64Bit ? u64 : u32;
unsigned int shiftAmount = hwField * 16;
Expression::Ptr lhs = Immediate::makeImmediate(
Result(rT, rT == u32 ? unsign_extend32(len, val) : unsign_extend64(len, val)));
Expression::Ptr rhs = Immediate::makeImmediate(Result(u32, unsign_extend32(6, shiftAmount)));
insn_in_progress->appendOperand(makeLeftShiftExpression(lhs, rhs, rT), true, false);
}
void InstructionDecoder_aarch64::processShiftFieldShiftedInsn(int len, int val) {
Result_Type rT;
Expression::Ptr lhs, rhs;
rT = is64Bit ? u64 : u32;
lhs = makeRmExpr();
rhs = Immediate::makeImmediate(Result(u32, unsign_extend32(len, val)));
switch (shiftField) //add-sub (shifted) and logical (shifted)
{
case 0:
insn_in_progress->appendOperand(makeLeftShiftExpression(lhs, rhs, rT), true, false);
break;
case 1:
insn_in_progress->appendOperand(makeRightLogicalShiftExpression(lhs, rhs, rT), true, false);
break;
case 2:
insn_in_progress->appendOperand(makeRightArithmeticShiftExpression(lhs, rhs, rT), true, false);
break;
case 3:
if (IS_INSN_LOGICAL_SHIFT(
insn)) //logical (shifted) -- not applicable to add-sub (shifted)
insn_in_progress->appendOperand(makeRightRotateExpression(lhs, rhs, rT), true, false);
else
isValid = false;
break;
}
}
void InstructionDecoder_aarch64::processShiftFieldImmInsn(int len, int val) {
if (shiftField == 0 || shiftField == 1) //add-sub (immediate)
{
Result_Type rT = is64Bit ? u64 : u32;
unsigned int shiftAmount = shiftField * 12;
Expression::Ptr lhs = Immediate::makeImmediate(
Result(rT, rT == u32 ? unsign_extend32(len, val) : unsign_extend64(len, val)));
Expression::Ptr rhs = Immediate::makeImmediate(Result(u32, unsign_extend32(4, shiftAmount)));
insn_in_progress->appendOperand(makeLeftShiftExpression(lhs, rhs, rT), true, false);
}
else {
isValid = false;
}
}
Expression::Ptr InstructionDecoder_aarch64::makeOptionExpression(int len, int val) {
MachRegister reg;
int encoding = field<16, 20>(insn);
reg = ((optionField & 0x3) == 0x3) ? ((encoding == 31) ? aarch64::zr : aarch64::x0) : ((encoding == 31)
? aarch64::wzr
: aarch64::w0);
if (encoding != 31)
reg = makeAarch64RegID(reg, encoding);
Expression::Ptr lhs;
switch (optionField) {
case 0:
lhs = makeRegisterExpression(reg, u8);
break;
case 1:
lhs = makeRegisterExpression(reg, u16);
break;
case 2:
lhs = makeRegisterExpression(reg, u32);
break;
case 3:
lhs = makeRegisterExpression(reg, u64);
break;
case 4:
lhs = makeRegisterExpression(reg, s8);
break;
case 5:
lhs = makeRegisterExpression(reg, s16);
break;
case 6:
lhs = makeRegisterExpression(reg, s32);
break;
case 7:
lhs = makeRegisterExpression(reg, s64);
break;
default:
isValid = false; //invalid option field
}
Result_Type rT = is64Bit ? (optionField < 4 ? u64 : s64) : (optionField < 4 ? u32 : s32);
return makeLeftShiftExpression(lhs, Immediate::makeImmediate(Result(u32, unsign_extend32(len, val))), rT);
}
void InstructionDecoder_aarch64::processOptionFieldLSRegOffsetInsn() {
if (optionField == 0x3) //option = LSL
{
int sizeVal = field<30, 31>(insn), extend;
if (field<23, 23>(insn) == 1)
sizeVal = 4;
extend = sField * sizeVal;
int extendSize = 31;
while (extendSize >= 0 && ((extend << (31 - extendSize)) & 0x80000000) == 0)
extendSize--;
//above values need to be used in a dereference expression
}
else {
//sign-extend
switch (optionField) {
case 0x2://UXTW
break;
case 0x6://SXTW
break;
case 0x7://SXTX
break;
default:
isValid = false;
break;
}
}
}
void InstructionDecoder_aarch64::processSystemInsn() {
int op0Field = field<19, 20>(insn), crnField = field<12, 15>(insn);
if (op0Field == 0) {
if (crnField == 3) //clrex, dendBit, dmb, iendBit
{
Expression::Ptr CRm = Immediate::makeImmediate(Result(u8, unsign_extend32(4, crmField)));
insn_in_progress->appendOperand(CRm, true, false);
}
else if (crnField == 2) //hint
{
int immVal = (crmField << 3) | (op2Field & 7);
Expression::Ptr imm = Immediate::makeImmediate(Result(u8, unsign_extend32(7, immVal)));
insn_in_progress->appendOperand(imm, true, false);
}
else if (crnField == 4) //msr (immediate)
{
int pstatefield = (op1Field << 3) | (op2Field & 7);
insn_in_progress->appendOperand(
Immediate::makeImmediate(Result(u8, unsign_extend32(6, pstatefield))), true, false);
insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u8, unsign_extend32(4, crmField))),
true, false);
isPstateWritten = true;
}
else {
isValid = false;
}
}
else if (op0Field == 1) //sys, sysl
{
insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u8, unsign_extend32(3, op1Field))),
true, false);
insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u8, unsign_extend32(4, crnField))),
true, false);
insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u8, unsign_extend32(4, crmField))),
true, false);
insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u8, unsign_extend32(3, op2Field))),
true, false);
bool isRtRead = (field<21, 21>(insn) == 0);
insn_in_progress->appendOperand(makeRtExpr(), isRtRead, !isRtRead);
}
else //mrs (register), msr
{
bool isRtRead = (field<21, 21>(insn) == 0);
unsigned int systemRegEncoding =
(op0Field << 14) | (op1Field << 11) | (crnField << 7) | (crmField << 3) | op2Field;
if (InstructionDecoder_aarch64::sysRegMap.count(systemRegEncoding) <= 0)
assert(!"tried to access system register not accessible in EL0");
MachRegister reg;
if ((op0Field & 0x3) == 0x3 && (crnField & 0x3) == 0x3 && (crnField & 0x8) == 0x8)
reg = aarch64::IMPLEMENTATION_DEFINED_SYSREG;
else
reg = InstructionDecoder_aarch64::sysRegMap[systemRegEncoding];
insn_in_progress->appendOperand(makeRegisterExpression(reg), !isRtRead, isRtRead);
insn_in_progress->appendOperand(makeRtExpr(), isRtRead, !isRtRead);
if (!isRtRead)
insn_in_progress->m_Operands.reverse();
}
}
Result_Type InstructionDecoder_aarch64::makeSizeType(unsigned int) {
assert(0); //not implemented
return u32;
}
// ****************
// decoding opcodes
// ****************
#define fn(x) (&InstructionDecoder_aarch64::x)
#define COMMA ,
MachRegister InstructionDecoder_aarch64::makeAarch64RegID(MachRegister base, unsigned int encoding) {
return MachRegister(base.val() + encoding);
}
template<unsigned int endBit, unsigned int startBit>
void InstructionDecoder_aarch64::OPRsize() {
size = field<startBit, endBit>(insn);
}
Expression::Ptr InstructionDecoder_aarch64::makeRdExpr() {
int encoding = field<0, 4>(insn);
MachRegister reg;
if (isSIMDInsn) {
if (IS_INSN_SIMD_ACROSS(insn)) {
//fmaxnmv, fmaxv, fminnmv, fminv
if (field<14, 14>(insn) == 0x1) {
if (_szField == 0x0)
reg = aarch64::s0;
else
isValid = false;
}
else {
int opcode = field<12, 16>(insn);
//saddlv and uaddlv with opcode field 0x03 use different sets of registers
switch (size) {
case 0x0:
reg = (opcode == 0x03) ? aarch64::h0 : aarch64::b0;
break;
case 0x1:
reg = (opcode == 0x03) ? aarch64::s0 : aarch64::h0;
break;
case 0x2:
reg = (opcode == 0x03) ? aarch64::d0 : aarch64::s0;
break;
default:
isValid = false;
}
}
}
else if (IS_INSN_SIMD_COPY(insn)) {
unsigned int op = field<29, 29>(insn);
unsigned int imm4 = field<11, 14>(insn);
if (op == 0x1)
reg = aarch64::q0;
else {
switch (imm4) {
case 0x5:
case 0x7:
reg = _Q == 0x1 ? aarch64::x0 : aarch64::w0;
break;
default:
reg = _Q == 0x1 ? aarch64::q0 : aarch64::d0;
break;
}
}
}
else if (IS_INSN_SCALAR_COPY(insn) || IS_INSN_SCALAR_SHIFT_IMM(insn)) {
int switchbit;
if (IS_INSN_SCALAR_COPY(insn))
switchbit = lowest_set_bit(field<16, 20>(insn));
else
switchbit = highest_set_bit(field<19, 22>(insn));
switch (switchbit) {
case 0x1:
reg = aarch64::b0;
break;
case 0x2:
reg = aarch64::h0;
break;
case 0x3:
reg = aarch64::s0;
break;
case 0x4:
reg = aarch64::d0;
break;
default:
isValid = false;
}
}
else if (IS_INSN_SCALAR_3DIFF(insn)) {
switch (size) {
case 0x1:
reg = aarch64::s0;
break;
case 0x2:
reg = aarch64::d0;
break;
default:
isValid = false;
}
}
else if (IS_INSN_SCALAR_INDEX(insn)) {
int opcode = field<12, 15>(insn);
//sqdmlal, sqdmlsl, sqdmull
if ((opcode & 0x3) == 0x3) {
switch (size) {
case 0x1:
reg = aarch64::s0;
break;
case 0x2:
reg = aarch64::d0;
break;
default:
isValid = false;
}
}
//sqdmulh, sqrdmulh
else if ((opcode & 0xC) == 0xC) {
switch (size) {
case 0x1:
reg = aarch64::h0;
break;
case 0x2:
reg = aarch64::s0;
break;
default:
isValid = false;
}
}
//fmla, fmls, fmul, fmulx
else if ((opcode & 0x3) == 0x1) {
switch (_szField) {
case 0x0:
reg = aarch64::s0;
break;
case 0x1:
reg = aarch64::d0;
break;
default:
isValid = false;
}
}
else
isValid = false;
}
else if (IS_INSN_SCALAR_2REG_MISC(insn) || IS_INSN_SCALAR_3SAME(insn)) {
//some instructions in this set rely on sz for choosing the register and some on size
//only one of them is set for an instruction, however
if (_szField == -1) {
switch (size) {
case 0x0:
reg = aarch64::b0;
break;
case 0x1:
reg = aarch64::h0;
break;
case 0x2:
reg = aarch64::s0;
break;
case 0x3:
reg = aarch64::d0;
break;
default:
isValid = false;
}
}
else {
switch (_szField) {
case 0x0:
reg = aarch64::s0;
break;
case 0x1: {
entryID op = insn_in_progress->getOperation().operationID;
reg = (op == aarch64_op_fcvtxn_advsimd) ? aarch64::s0 : aarch64::d0;
}
break;
default:
isValid = false;
}
}
}
else if (IS_INSN_SCALAR_PAIR(insn)) {
if (size != -1) {
if (size == 0x3)
reg = aarch64::d0;
else
isValid = false;
}
else if (_szField != -1) {
switch (_szField) {
case 0x0:
reg = aarch64::s0;
break;
case 0x1:
reg = aarch64::d0;
break;
}
}
else
isValid = false;
}
else if (IS_INSN_SIMD_MOD_IMM(insn) && _Q == 0 && op == 1 && cmode == 0xE) {
reg = aarch64::d0;
}
else if (IS_INSN_SIMD_VEC_INDEX(insn)) {
if (field<13, 13>(insn) == 0x1)
reg = aarch64::q0;
else
reg = _Q == 0x1 ? aarch64::q0 : aarch64::d0;
}
else if (IS_INSN_SIMD_3DIFF(insn)) {
entryID op = insn_in_progress->getOperation().operationID;
if (op == aarch64_op_addhn_advsimd || op == aarch64_op_subhn_advsimd ||
op == aarch64_op_raddhn_advsimd || op == aarch64_op_rsubhn_advsimd)
reg = _Q == 0x1 ? aarch64::hq0 : aarch64::d0;
else
reg = aarch64::q0;
}
// 3SAME, 2REG_MISC, EXTRACT
else
reg = _Q == 0x1 ? aarch64::q0 : aarch64::d0;
reg = makeAarch64RegID(reg, encoding);
}
else if (isFPInsn && !((IS_INSN_FP_CONV_FIX(insn) || (IS_INSN_FP_CONV_INT(insn))) && !IS_SOURCE_GP(insn))) {
if (IS_INSN_FP_DATAPROC_ONESRC(insn)) {
int opc = field<15, 16>(insn);
switch (opc) {
case 0:
reg = aarch64::s0;
break;
case 1:
reg = aarch64::d0;
break;
case 3:
reg = aarch64::h0;
break;
default:
isValid = false;
}
}
else
reg = isSinglePrec() ? aarch64::s0 : aarch64::d0;
reg = makeAarch64RegID(reg, encoding);
}
else {
if (encoding == 31)
reg = ((IS_INSN_ADDSUB_IMM(insn) || IS_INSN_ADDSUB_EXT(insn) || IS_INSN_LOGICAL_IMM(insn)) &&
!isPstateWritten) ? (is64Bit ? aarch64::sp : aarch64::wsp) : (is64Bit ? aarch64::zr
: aarch64::wzr);
else
reg = is64Bit ? aarch64::x0 : aarch64::w0;
if (isValid && encoding != 31)
reg = makeAarch64RegID(reg, encoding);
}
return makeRegisterExpression(reg);
}
void InstructionDecoder_aarch64::OPRRd() {
Expression::Ptr reg = makeRdExpr();
int cmode = field<12, 15>(insn);
bool isRdRead = false;
if (((IS_INSN_SIMD_VEC_INDEX(insn) || IS_INSN_SCALAR_INDEX(insn)) && !(cmode & 0x8)) ||
(IS_INSN_SIMD_MOD_IMM(insn) &&
(((cmode & 0x8) && !(cmode & 0x4) && (cmode & 0x1)) ||
(!(cmode & 0x8) && (cmode & 0x1)))))
isRdRead = true;
//for SIMD/Scalar vector indexed set, some instructions read Rd and some don't. This can be determined from the highest bit of the opcode field (bit 15)
insn_in_progress->appendOperand(reg, isRdRead, true);
}
void InstructionDecoder_aarch64::OPRcmode() {
cmode = field<12, 15>(insn);
}
void InstructionDecoder_aarch64::OPRop() {
op = field<29, 29>(insn);
}
void InstructionDecoder_aarch64::OPRa() {
simdAlphabetImm |= (simdAlphabetImm & 0x7F) | (field<18, 18>(insn) << 7);
}
void InstructionDecoder_aarch64::OPRb() {
simdAlphabetImm |= (simdAlphabetImm & 0xBF) | (field<17, 17>(insn) << 6);
}
void InstructionDecoder_aarch64::OPRc() {
simdAlphabetImm |= (simdAlphabetImm & 0xDF) | (field<16, 16>(insn) << 5);
}
void InstructionDecoder_aarch64::OPRd() {
simdAlphabetImm |= (simdAlphabetImm & 0xEF) | (field<9, 9>(insn) << 4);
}
void InstructionDecoder_aarch64::OPRe() {
simdAlphabetImm |= (simdAlphabetImm & 0xF7) | (field<8, 8>(insn) << 3);
}
void InstructionDecoder_aarch64::OPRf() {
simdAlphabetImm |= (simdAlphabetImm & 0xFB) | (field<7, 7>(insn) << 2);
}
void InstructionDecoder_aarch64::OPRg() {
simdAlphabetImm |= (simdAlphabetImm & 0xFD) | (field<6, 6>(insn) << 1);
}
void InstructionDecoder_aarch64::OPRh() {
simdAlphabetImm |= (simdAlphabetImm & 0xFE) | (field<5, 5>(insn));
}
void InstructionDecoder_aarch64::OPRlen() {
//reuse immlo
immlo = field<13, 14>(insn);
}
Expression::Ptr InstructionDecoder_aarch64::makeRnExpr() {
int encoding = field<5, 9>(insn);
MachRegister reg;
if (isSIMDInsn && !IS_INSN_LDST(insn)) {
if (IS_INSN_SIMD_COPY(insn)) {
unsigned int op = field<29, 29>(insn);
unsigned int imm4 = field<11, 14>(insn);
unsigned int imm5 = field<16, 20>(insn);
//ins (element)
if (op == 0x1) {
reg = (imm4 & 0x8) ? aarch64::q0 : aarch64::d0;
}
else {
switch (imm4) {
//dup (element), smov, umov
case 0x0:
case 0x5:
case 0x7:
reg = (imm5 & 0x10) ? aarch64::q0 : aarch64::d0;
break;
//dup (general), ins (general)
case 0x1:
case 0x3:
if (imm5 & 0x1 || imm5 & 0x2 || imm5 & 0x4) {
reg = encoding == 31 ? aarch64::wzr : aarch64::w0;
}
else {
reg = encoding == 31 ? aarch64::zr : aarch64::x0;
}
break;
default:
isValid = false;
break;
}
}
}
else if (IS_INSN_SCALAR_COPY(insn)) {
int imm5 = field<16, 20>(insn);
reg = (imm5 & 0x10) ? aarch64::q0 : aarch64::d0;
}
else if (IS_INSN_SCALAR_PAIR(insn)) {
if (size != -1) {
if (size == 0x3)
reg = aarch64::q0;
else
isValid = false;
}
else if (_szField != -1) {
switch (_szField) {
case 0x0:
reg = aarch64::d0;
break;
case 0x1:
reg = aarch64::q0;
break;
}
}
else
isValid = false;
}
else if (IS_INSN_SCALAR_SHIFT_IMM(insn)) {
int switchbit = highest_set_bit(field<19, 22>(insn));
bool isRnVa = false;
int opcode = field<11, 15>(insn);
if ((opcode & 0x1C) == 0x10)
isRnVa = true;
switch (switchbit) {
case 0x1:
reg = isRnVa ? aarch64::h0 : aarch64::b0;
break;
case 0x2:
reg = isRnVa ? aarch64::s0 : aarch64::h0;
break;
case 0x3:
reg = isRnVa ? aarch64::d0 : aarch64::s0;
break;
case 0x4:
isRnVa ? (isValid = false) : (reg = aarch64::d0);
break;
default:
isValid = false;
}
}
else if (IS_INSN_SCALAR_3DIFF(insn)) {
switch (size) {
case 0x1:
reg = aarch64::h0;
break;
case 0x2:
reg = aarch64::s0;
break;
default:
isValid = false;
}
}
else if (IS_INSN_SCALAR_INDEX(insn)) {
int opcode = field<12, 15>(insn);
//sqdmlal, sqdmlsl, sqdmull
//sqdmulh, sqrdmulh
if ((opcode & 0xC) == 0xC || (opcode & 0x3) == 0x3) {
switch (size) {
case 0x1:
reg = aarch64::h0;
break;
case 0x2:
reg = aarch64::s0;
break;
default:
isValid = false;
}
}
//fmla, fmls, fmul, fmulx
else if ((opcode & 0x3) == 0x1) {
switch (_szField) {
case 0x0:
reg = aarch64::s0;
break;
case 0x1:
reg = aarch64::d0;
break;
default:
isValid = false;
}
}
else
isValid = false;
}
else if (IS_INSN_SCALAR_2REG_MISC(insn) || IS_INSN_SCALAR_3SAME(insn)) {
//some instructions in this set rely on sz for choosing the register and some on size
//only one of them is set for an instruction, however
bool isRnVa = false;
int opcode = field<12, 16>(insn);
if (!IS_INSN_SCALAR_3SAME(insn) && (opcode & 0x18) == 0x10 && (opcode & 0x1) == 0x0)
isRnVa = true;
if (_szField == -1) {
switch (size) {
case 0x0:
reg = isRnVa ? aarch64::h0 : aarch64::b0;
break;
case 0x1:
reg = isRnVa ? aarch64::s0 : aarch64::h0;
break;
case 0x2:
reg = isRnVa ? aarch64::d0 : aarch64::s0;
break;
case 0x3:
isRnVa ? (isValid = false) : (reg = aarch64::d0);
break;
default:
isValid = false;
}
}
else {
switch (_szField) {
case 0x0:
isRnVa ? (isValid = false) : (reg = aarch64::s0);
break;
case 0x1:
reg = aarch64::d0;
break;
default:
isValid = false;
}
}
}
else if (IS_INSN_SIMD_VEC_INDEX(insn)) {
//the below two conditions can easily be combined into one, but would be difficult to understand
if (field<13, 13>(insn) == 0x1)
reg = _Q == 0x1 ? aarch64::hq0 : aarch64::d0;
else
//sqdmulh, mul, sqrdmulh, fmla, fmls, fmul, mla, mls, fmulx
reg = _Q == 0x1 ? aarch64::q0 : aarch64::d0;
}
else if (IS_INSN_SIMD_TAB_LOOKUP(insn)) {
reg = _Q == 1 ? aarch64::q0 : aarch64::d0;
for (int reg_index = immlo; reg_index > 0; reg_index--) {
insn_in_progress->appendOperand(
makeRegisterExpression(makeAarch64RegID(reg, (encoding + reg_index) % 32)), true,
false);
}
}
else if (IS_INSN_SIMD_3DIFF(insn)) {
entryID op = insn_in_progress->getOperation().operationID;
if (op == aarch64_op_saddw_advsimd || op == aarch64_op_ssubw_advsimd ||
op == aarch64_op_addhn_advsimd || op == aarch64_op_subhn_advsimd ||
op == aarch64_op_uaddw_advsimd || op == aarch64_op_usubw_advsimd ||
op == aarch64_op_raddhn_advsimd || op == aarch64_op_rsubhn_advsimd)
reg = aarch64::q0;
else
reg = _Q == 0x1 ? aarch64::hq0 : aarch64::d0;
}
else
reg = _Q == 0x1 ? aarch64::q0 : aarch64::d0;
if (!(reg == aarch64::wzr || reg == aarch64::zr))
reg = makeAarch64RegID(reg, encoding);
}
else if (isFPInsn && !((IS_INSN_FP_CONV_FIX(insn) || (IS_INSN_FP_CONV_INT(insn))) && IS_SOURCE_GP(insn))) {
switch (_typeField) {
case 0:
reg = aarch64::s0;
break;
case 1:
reg = aarch64::d0;
break;
case 3:
reg = aarch64::h0;
break;
default:
isValid = false;
}