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dyn_regs.C
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dyn_regs.C
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/*
* See the dyninst/COPYRIGHT file for copyright information.
*
* We provide the Paradyn Tools (below described as "Paradyn")
* on an AS IS basis, and do not warrant its validity or performance.
* We reserve the right to update, modify, or discontinue this
* software at any time. We shall have no obligation to supply such
* updates or modifications or any other form of support to you.
*
* By your use of Paradyn, you understand and agree that we (or any
* other person or entity with proprietary rights in Paradyn) are
* under no obligation to provide either maintenance services,
* update services, notices of latent defects, or correction of
* defects for Paradyn.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define DYN_DEFINE_REGS
#include "common/h/dyn_regs.h"
#include "external/rose/rose-compat.h"
#include "external/rose/powerpcInstructionEnum.h"
#include "external/rose/armv8InstructionEnum.h"
#include <iostream>
using namespace Dyninst;
boost::shared_ptr<MachRegister::NameMap> MachRegister::names()
{
static boost::shared_ptr<MachRegister::NameMap> store =
boost::shared_ptr<MachRegister::NameMap>(new MachRegister::NameMap);
return store;
}
MachRegister::MachRegister() :
reg(0)
{
}
MachRegister::MachRegister(signed int r) :
reg(r)
{
}
MachRegister::MachRegister(signed int r, const char *n) :
reg(r)
{
(*names())[r] = std::string(n);
}
MachRegister::MachRegister(signed int r, std::string n) :
reg(r)
{
(*names())[r] = n;
}
unsigned int MachRegister::regClass() const
{
return reg & 0x00ff0000;
}
MachRegister MachRegister::getBaseRegister() const {
switch (getArchitecture()) {
case Arch_x86:
if (reg & x86::GPR) return MachRegister(reg & 0xfffff0ff);
else return *this;
case Arch_x86_64:
if (reg & x86_64::GPR) return MachRegister(reg & 0xfffff0ff);
else return *this;
case Arch_ppc32:
case Arch_ppc64:
case Arch_none:
return *this;
case Arch_aarch32:
case Arch_aarch64:
//not verified
return *this;
}
return InvalidReg;
}
Architecture MachRegister::getArchitecture() const {
return (Architecture) (reg & 0xff000000);
}
bool MachRegister::isValid() const {
return (reg != InvalidReg.reg);
}
MachRegisterVal MachRegister::getSubRegValue(const MachRegister& subreg,
MachRegisterVal &orig) const
{
if (subreg.reg == reg ||
getArchitecture() == Arch_ppc32 ||
getArchitecture() == Arch_ppc64)
return orig;
assert(subreg.getBaseRegister() == getBaseRegister());
switch ((subreg.reg & 0x00000f00) >> 8) {
case 0x0: return orig;
case 0x1: return (orig & 0xff);
case 0x2: return (orig & 0xff00) >> 8;
case 0x3: return (orig & 0xffff);
case 0xf: return (orig & 0xffffffff);
default: assert(0); return orig;
}
}
std::string MachRegister::name() const {
assert(names() != NULL);
NameMap::const_iterator iter = names()->find(reg);
if (iter != names()->end()) {
return iter->second;
}
return std::string("<INVALID_REG>");
}
unsigned int MachRegister::size() const {
switch (getArchitecture())
{
case Arch_x86:
switch (reg & 0x0000ff00) {
case x86::L_REG: //L_REG
case x86::H_REG: //H_REG
return 1;
case x86::W_REG: //W_REG
return 2;
case x86::FULL: //FULL
return 4;
case x86::QUAD:
return 8;
case x86::OCT:
return 16;
case x86::FPDBL:
return 10;
case x86::BIT:
return 0;
default:
return 0;//KEVINTODO: removed sanity-check assert because of asprotect fuzz testing, could use this as a sign that the parse has gone into junk
assert(0);
}
case Arch_x86_64:
switch (reg & 0x0000ff00) {
case x86_64::L_REG: //L_REG
case x86_64::H_REG: //H_REG
return 1;
case x86_64::W_REG: //W_REG
return 2;
case x86_64::FULL: //FULL
return 8;
case x86_64::D_REG:
return 4;
case x86_64::OCT:
return 16;
case x86_64::FPDBL:
return 10;
case x86_64::BIT:
return 0;
default:
return 0; // Xiaozhu: do not assert, but return 0 as an indication of parsing junk.
assert(0);
}
case Arch_ppc32: {
int reg_class = reg & 0x00ff0000;
if (reg_class == ppc32::FPR || reg_class == ppc32::FSR)
return 8;
return 4;
}
case Arch_ppc64:
if((reg & 0x00ff0000) == aarch64::FPR)
return 16;
return 8;
case Arch_aarch32:
assert(0);
case Arch_aarch64:
if((reg & 0x00ff0000) == aarch64::FPR)
{
switch(reg & 0x0000ff00)
{
case aarch64::B_REG: return 1;
case aarch64::W_REG: return 2;
case aarch64::D_REG: return 4;
case aarch64::FULL:
case aarch64::HQ_REG: return 8;
case aarch64::Q_REG: return 16;
default:
assert(0);
return 0;
}
}
else if((reg & 0x00ff0000) == aarch64::GPR || (reg & 0x00ff0000) == aarch64::SPR ||
(reg & 0x00ff0000) == aarch64::SYSREG || (reg & 0x00ff0000) == aarch64::FLAG)
switch(reg & 0x0000ff00)
{
case aarch64::FULL : return 8;
case aarch64::D_REG: return 4;
case aarch64::BIT: return 0;
default: return 0;
}
else
return 4;
case Arch_none:
return 0;
}
return 0; //Unreachable, but disable warnings
}
bool MachRegister::operator<(const MachRegister &a) const {
return (reg < a.reg);
}
bool MachRegister::operator==(const MachRegister &a) const {
return (reg == a.reg);
}
MachRegister::operator signed int() const {
return reg;
}
signed int MachRegister::val() const {
return reg;
}
MachRegister MachRegister::getPC(Dyninst::Architecture arch)
{
switch (arch)
{
case Arch_x86:
return x86::eip;
case Arch_x86_64:
return x86_64::rip;
case Arch_ppc32:
return ppc32::pc;
case Arch_ppc64:
return ppc64::pc;
case Arch_aarch64: //aarch64: pc is not writable
return aarch64::pc;
case Arch_aarch32:
assert(0);
case Arch_none:
return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getReturnAddress(Dyninst::Architecture arch)
{
switch (arch)
{
case Arch_x86:
assert(0); //not implemented
case Arch_x86_64:
assert(0); //not implemented
case Arch_ppc32:
assert(0); //not implemented
case Arch_ppc64:
assert(0); //not implemented
case Arch_aarch64: //aarch64: x30 stores the RA for current frame
return aarch64::x30;
case Arch_aarch32:
assert(0);
case Arch_none:
return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getFramePointer(Dyninst::Architecture arch)
{
switch (arch)
{
case Arch_x86:
return x86::ebp;
case Arch_x86_64:
return x86_64::rbp;
case Arch_ppc32:
return ppc32::r1;
case Arch_ppc64:
return ppc64::r1;
case Arch_aarch64:
return aarch64::x29; //aarch64: frame pointer is X29 by convention
case Arch_none:
return InvalidReg;
default:
assert(0);
return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getStackPointer(Dyninst::Architecture arch)
{
switch (arch)
{
case Arch_x86:
return x86::esp;
case Arch_x86_64:
return x86_64::rsp;
case Arch_ppc32:
return ppc32::r1;
case Arch_ppc64:
return ppc64::r1;
case Arch_aarch64:
return aarch64::sp; //aarch64: stack pointer is an independent register
case Arch_aarch32:
assert(0);
case Arch_none:
return InvalidReg;
default:
assert(0);
return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getSyscallNumberReg(Dyninst::Architecture arch)
{
switch (arch)
{
case Arch_x86:
return x86::eax;
case Arch_x86_64:
return x86_64::rax;
case Arch_ppc32:
return ppc32::r0;
case Arch_ppc64:
return ppc64::r0;
case Arch_aarch64:
return aarch64::x8;
case Arch_aarch32:
assert(0);
case Arch_none:
return InvalidReg;
default:
assert(0);
return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getSyscallNumberOReg(Dyninst::Architecture arch)
{
switch (arch)
{
case Arch_x86:
return x86::oeax;
case Arch_x86_64:
return x86_64::orax;
case Arch_ppc32:
return ppc32::r0;
case Arch_ppc64:
return ppc64::r0;
case Arch_aarch64:
return aarch64::x8;
case Arch_none:
return InvalidReg;
default:
assert(0);
return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getSyscallReturnValueReg(Dyninst::Architecture arch)
{
switch (arch)
{
case Arch_x86:
return x86::eax;
case Arch_x86_64:
return x86_64::rax;
case Arch_ppc32:
return ppc32::r3;
case Arch_ppc64:
return ppc64::r3;
case Arch_aarch64:
return aarch64::x0; //returned value is save in x0
case Arch_none:
return InvalidReg;
default:
assert(0);
return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getArchRegFromAbstractReg(MachRegister abstract,
Dyninst::Architecture arch) {
switch(arch){
case Arch_aarch64:
if( abstract == ReturnAddr)
return aarch64::x30;
if( abstract == FrameBase)
return aarch64::x29;
if( abstract == StackTop)
return aarch64::sp;
if( abstract == CFA)
assert(0); //don't know what to do
//not abstract, return arch reg
return abstract;
default:
assert(0);
}
return Dyninst::InvalidReg;
}
MachRegister MachRegister::getZeroFlag(Dyninst::Architecture arch)
{
switch (arch)
{
case Arch_x86:
return x86::zf;
case Arch_x86_64:
return x86_64::zf;
case Arch_aarch64:
return aarch64::z;
case Arch_aarch32:
assert(0);
case Arch_none:
return InvalidReg;
}
return InvalidReg;
}
bool MachRegister::isPC() const
{
return (*this == x86_64::rip || *this == x86::eip ||
*this == ppc32::pc || *this == ppc64::pc ||
*this == aarch64::pc );
}
bool MachRegister::isFramePointer() const
{
return (*this == x86_64::rbp || *this == x86::ebp ||
*this == FrameBase ||
*this == aarch64::x29);
}
bool MachRegister::isStackPointer() const
{
return (*this == x86_64::rsp || *this == x86::esp ||
*this == ppc32::r1 || *this == ppc64::r1 ||
*this == aarch64::sp);
}
bool MachRegister::isSyscallNumberReg() const
{
return ( *this == x86_64::orax || *this == x86::oeax ||
*this == ppc32::r1 || *this == ppc64::r1 ||
*this == aarch64::x8
);
}
bool MachRegister::isSyscallReturnValueReg() const
{
if(getArchitecture() == Arch_aarch64)
assert(0);
return (*this == x86_64::rax || *this == x86::eax ||
*this == ppc32::r1 || *this == ppc64::r1 ||
*this == aarch64::x0
);
}
bool MachRegister::isFlag() const
{
int regC = regClass();
switch (getArchitecture())
{
case Arch_x86:
return regC == x86::FLAG;
case Arch_x86_64:
return regC == x86_64::FLAG;
case Arch_aarch64:
return regC == aarch64::FLAG;
default:
assert(!"Not implemented!");
}
return false;
}
COMMON_EXPORT bool Dyninst::isSegmentRegister(int regClass)
{
return 0 != (regClass & x86::SEG);
}
void MachRegister::getROSERegister(int &c, int &n, int &p)
{
// Rose: class, number, position
// Dyninst: category, base id, subrange
signed int category = (reg & 0x00ff0000);
signed int subrange = (reg & 0x0000ff00);
signed int baseID = (reg & 0x000000ff);
switch (getArchitecture()) {
case Arch_x86:
switch (category) {
case x86::GPR:
c = x86_regclass_gpr;
switch (baseID) {
case x86::BASEA:
n = x86_gpr_ax;
break;
case x86::BASEC:
n = x86_gpr_cx;
break;
case x86::BASED:
n = x86_gpr_dx;
break;
case x86::BASEB:
n = x86_gpr_bx;
break;
case x86::BASESP:
n = x86_gpr_sp;
break;
case x86::BASEBP:
n = x86_gpr_bp;
break;
case x86::BASESI:
n = x86_gpr_si;
break;
case x86::BASEDI:
n = x86_gpr_di;
break;
default:
n = 0;
break;
}
break;
case x86::SEG:
c = x86_regclass_segment;
switch (baseID) {
case 0x0:
n = x86_segreg_ds;
break;
case 0x1:
n = x86_segreg_es;
break;
case 0x2:
n = x86_segreg_fs;
break;
case 0x3:
n = x86_segreg_gs;
break;
case 0x4:
n = x86_segreg_cs;
break;
case 0x5:
n = x86_segreg_ss;
break;
default:
n = 0;
break;
}
break;
case x86::FLAG:
c = x86_regclass_flags;
switch(baseID) {
case x86::CF:
n = x86_flag_cf;
break;
case x86::PF:
n = x86_flag_pf;
break;
case x86::AF:
n = x86_flag_af;
break;
case x86::ZF:
n = x86_flag_zf;
break;
case x86::SF:
n = x86_flag_sf;
break;
case x86::TF:
n = x86_flag_tf;
break;
case x86::IF:
n = x86_flag_if;
break;
case x86::DF:
n = x86_flag_df;
break;
case x86::OF:
n = x86_flag_of;
break;
default:
assert(0);
break;
}
break;
case x86::MISC:
c = x86_regclass_unknown;
break;
case x86::XMM:
c = x86_regclass_xmm;
n = baseID;
break;
case x86::MMX:
c = x86_regclass_mm;
n = baseID;
break;
case x86::CTL:
c = x86_regclass_cr;
n = baseID;
break;
case x86::DBG:
c = x86_regclass_dr;
n = baseID;
break;
case x86::TST:
c = x86_regclass_unknown;
break;
case 0:
switch (baseID) {
case 0x10:
c = x86_regclass_ip;
n = 0;
break;
default:
c = x86_regclass_unknown;
break;
}
break;
}
break;
case Arch_x86_64:
switch (category) {
case x86_64::GPR:
c = x86_regclass_gpr;
switch (baseID) {
case x86_64::BASEA:
n = x86_gpr_ax;
break;
case x86_64::BASEC:
n = x86_gpr_cx;
break;
case x86_64::BASED:
n = x86_gpr_dx;
break;
case x86_64::BASEB:
n = x86_gpr_bx;
break;
case x86_64::BASESP:
n = x86_gpr_sp;
break;
case x86_64::BASEBP:
n = x86_gpr_bp;
break;
case x86_64::BASESI:
n = x86_gpr_si;
break;
case x86_64::BASEDI:
n = x86_gpr_di;
break;
case x86_64::BASE8:
n = x86_gpr_r8;
break;
case x86_64::BASE9:
n = x86_gpr_r9;
break;
case x86_64::BASE10:
n = x86_gpr_r10;
break;
case x86_64::BASE11:
n = x86_gpr_r11;
break;
case x86_64::BASE12:
n = x86_gpr_r12;
break;
case x86_64::BASE13:
n = x86_gpr_r13;
break;
case x86_64::BASE14:
n = x86_gpr_r14;
break;
case x86_64::BASE15:
n = x86_gpr_r15;
break;
default:
n = 0;
break;
}
break;
case x86_64::SEG:
c = x86_regclass_segment;
switch (baseID) {
case 0x0:
n = x86_segreg_ds;
break;
case 0x1:
n = x86_segreg_es;
break;
case 0x2:
n = x86_segreg_fs;
break;
case 0x3:
n = x86_segreg_gs;
break;
case 0x4:
n = x86_segreg_cs;
break;
case 0x5:
n = x86_segreg_ss;
break;
default:
n = 0;
break;
}
break;
case x86_64::FLAG:
c = x86_regclass_flags;
switch(baseID) {
case x86_64::CF:
n = x86_flag_cf;
break;
case x86_64::PF:
n = x86_flag_pf;
break;
case x86_64::AF:
n = x86_flag_af;
break;
case x86_64::ZF:
n = x86_flag_zf;
break;
case x86_64::SF:
n = x86_flag_sf;
break;
case x86_64::TF:
n = x86_flag_tf;
break;
case x86_64::IF:
n = x86_flag_if;
break;
case x86_64::DF:
n = x86_flag_df;
break;
case x86_64::OF:
n = x86_flag_of;
break;
default:
assert(0);
break;
}
break;
case x86_64::MISC:
c = x86_regclass_unknown;
break;
case x86_64::KMASK:
c = x86_regclass_kmask;
n = baseID;
break;
case x86_64::ZMM:
c = x86_regclass_zmm;
n = baseID;
break;
case x86_64::YMM:
c = x86_regclass_ymm;
n = baseID;
break;
case x86_64::XMM:
c = x86_regclass_xmm;
n = baseID;
break;
case x86_64::MMX:
c = x86_regclass_mm;
n = baseID;
break;
case x86_64::CTL:
c = x86_regclass_cr;
n = baseID;
break;
case x86_64::DBG:
c = x86_regclass_dr;
n = baseID;
break;
case x86_64::TST:
c = x86_regclass_unknown;
break;
case 0:
switch (baseID) {
case 0x10:
c = x86_regclass_ip;
n = 0;
break;
default:
c = x86_regclass_unknown;
break;
}
break;
}
break;
case Arch_ppc32:
case Arch_ppc64: // 64-bit not supported in ROSE
{
baseID = reg & 0x0000FFFF;
n = baseID;
switch(category)
{
case ppc32::GPR:
c = powerpc_regclass_gpr;
break;
case ppc32::FPR:
case ppc32::FSR:
c = powerpc_regclass_fpr;
break;
case ppc32::SPR:
{
if(baseID < 613) {
c = powerpc_regclass_spr;
} else if(baseID < 621 ) {
c = powerpc_regclass_sr;
} else {
c = powerpc_regclass_cr;
n = baseID - 621;
if(n > 7) {
n = 0;
p = powerpc_condreggranularity_whole;
} else {
p = powerpc_condreggranularity_field;
}
}
}
break;
default:
assert(!"unknown register type!");
break;
}
return;
}
break;
case Arch_aarch64: {
p = 0;
switch (category) {
case aarch64::GPR: {
c = armv8_regclass_gpr;
int regnum = baseID - (aarch64::x0 & 0xFF);
n = armv8_gpr_r0 + regnum;
}
break;
case aarch64::SPR: {
n = 0;
if (baseID == (aarch64::pstate & 0xFF)) {
c = armv8_regclass_pstate;
} else if(baseID == (aarch64::xzr & 0xFF) || baseID == (aarch64::wzr & 0xFF)) {
c = armv8_regclass_gpr;
n = armv8_gpr_zr;
} else if (baseID == (aarch64::pc & 0xFF)) {
c = armv8_regclass_pc;
} else if (baseID == (aarch64::sp & 0xFF) || baseID == (aarch64::wsp & 0xFF)) {
c = armv8_regclass_sp;
}
}
break;
case aarch64::FPR: {
c = armv8_regclass_simd_fpr;
int firstRegId;
switch(reg & 0xFF00) {
case aarch64::Q_REG: firstRegId = (aarch64::q0 & 0xFF);
break;
case aarch64::HQ_REG: firstRegId = (aarch64::hq0 & 0xFF);
p = 64;
break;
case aarch64::FULL: firstRegId = (aarch64::d0 & 0xFF);
break;
case aarch64::D_REG: firstRegId = (aarch64::s0 & 0xFF);
break;
case aarch64::W_REG: firstRegId = (aarch64::h0 & 0xFF);
break;
case aarch64::B_REG: firstRegId = (aarch64::b0 & 0xFF);
break;
default:assert(!"invalid register subcategory for ARM64!");
break;
}
n = armv8_simdfpr_v0 + (baseID - firstRegId);
}
break;
case aarch64::FLAG: {
c = armv8_regclass_pstate;
n = 0;
switch (baseID) {
case aarch64::N_FLAG:
p = armv8_pstatefield_n;
break;
case aarch64::Z_FLAG:
p = armv8_pstatefield_z;
break;
case aarch64::V_FLAG:
p = armv8_pstatefield_v;
break;
case aarch64::C_FLAG:
p = armv8_pstatefield_c;
break;
default:
assert(!"unknown flag type!");
break;
}
}
break;
default:
assert(!"unknown register type!");
break;
}
return;
}
break;
default:
c = x86_regclass_unknown;
n = 0;
break;
}
switch (getArchitecture()) {
case Arch_x86:
switch (subrange) {
case x86::OCT:
case x86::FPDBL:
p = x86_regpos_qword;
break;
case x86::H_REG:
p = x86_regpos_high_byte;
break;
case x86::L_REG:
p = x86_regpos_low_byte;
break;
case x86::W_REG:
p = x86_regpos_word;
break;
case x86::FULL:
case x86_64::D_REG:
p = x86_regpos_dword;
break;
case x86::BIT:
p = x86_regpos_all;
break;
}
break;
case Arch_x86_64:
switch (subrange) {
case x86::FULL:
case x86::OCT:
case x86::FPDBL:
p = x86_regpos_qword;
break;
case x86::H_REG:
p = x86_regpos_high_byte;
break;
case x86::L_REG:
p = x86_regpos_low_byte;
break;
case x86::W_REG:
p = x86_regpos_word;
break;
case x86_64::D_REG:
p = x86_regpos_dword;
break;
case x86::BIT:
p = x86_regpos_all;
break;
}
break;
case Arch_aarch64:
{
assert(0);
}
default:
p = x86_regpos_unknown;
}
}
MachRegister MachRegister::DwarfEncToReg(int encoding, Dyninst::Architecture arch)
{
switch (arch)
{
case Arch_x86:
switch (encoding) {
case 0: return Dyninst::x86::eax;
case 1: return Dyninst::x86::ecx;
case 2: return Dyninst::x86::edx;
case 3: return Dyninst::x86::ebx;