/
MachRegister.C
1935 lines (1859 loc) · 74.3 KB
/
MachRegister.C
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#include "common/h/registers/MachRegister.h"
#include "debug_common.h"
#include "dyn_regs.h"
#include "external/rose/amdgpuInstructionEnum.h"
#include "external/rose/armv8InstructionEnum.h"
#include "external/rose/powerpcInstructionEnum.h"
#include "external/rose/rose-compat.h"
#include <cassert>
#include <unordered_map>
namespace {
std::unordered_map<signed int, std::string> names;
const std::string invalid_reg_name{"<INVALID_REG>"};
}
namespace Dyninst {
MachRegister::MachRegister() : reg(0) {}
MachRegister::MachRegister(signed int r) : reg(r) {}
MachRegister::MachRegister(signed int r, std::string n) : reg(r) { names.emplace(r, std::move(n)); }
unsigned int MachRegister::regClass() const { return reg & 0x00ff0000; }
MachRegister MachRegister::getBaseRegister() const {
signed int category = (reg & 0x00ff0000);
switch(getArchitecture()) {
case Arch_x86:
if(category == x86::GPR)
return MachRegister(reg & 0xfffff0ff);
else if(category == x86::FLAG)
return x86::flags;
else
return *this;
case Arch_x86_64:
if(category == x86_64::GPR)
return MachRegister(reg & 0xfffff0ff);
else if(category == x86_64::FLAG)
return x86_64::flags;
else
return *this;
case Arch_ppc32:
case Arch_ppc64:
case Arch_none: return *this;
case Arch_amdgpu_gfx908:
switch(category) {
case amdgpu_gfx908::SGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx908::s0);
case amdgpu_gfx908::VGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx908::v0);
case amdgpu_gfx908::HWR: return MachRegister(reg);
default: return *this;
}
case Arch_amdgpu_gfx90a:
switch(category) {
case amdgpu_gfx90a::SGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx90a::s0);
case amdgpu_gfx90a::VGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx90a::v0);
case amdgpu_gfx90a::HWR: return MachRegister(reg);
default: return *this;
}
case Arch_amdgpu_gfx940:
switch(category) {
case amdgpu_gfx940::SGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx940::s0);
case amdgpu_gfx940::VGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx940::v0);
case amdgpu_gfx940::HWR: return MachRegister(reg);
default: return *this;
}
case Arch_aarch32:
case Arch_aarch64:
case Arch_intelGen9:
case Arch_cuda:
// not verified
return *this;
default: return InvalidReg;
}
return InvalidReg;
}
Architecture MachRegister::getArchitecture() const { return (Architecture)(reg & 0xff000000); }
bool MachRegister::isValid() const { return (reg != InvalidReg.reg); }
std::string const& MachRegister::name() const {
auto iter = names.find(reg);
if(iter != names.end()) {
return iter->second;
}
common_parsing_printf("No MachRegister found with value %x\n", static_cast<unsigned int>(reg));
return invalid_reg_name;
}
unsigned int MachRegister::size() const {
switch(getArchitecture()) {
case Arch_x86:
switch(reg & 0x0000ff00) {
case x86::L_REG: // L_REG
case x86::H_REG: // H_REG
return 1;
case x86::W_REG: // W_REG
return 2;
case x86::FULL: // FULL
return 4;
// Commented out because no register
// is defined with this size type
// case x86::QUAD:
// return 8;
case x86::OCT: return 16;
case x86::FPDBL: return 10;
case x86::BIT: return 0;
case x86::YMMS: return 32;
case x86::ZMMS: return 64;
default:
return 0;
}
break;
case Arch_x86_64:
switch(reg & 0x0000ff00) {
case x86_64::L_REG: // L_REG
case x86_64::H_REG: // H_REG
return 1;
case x86_64::W_REG: // W_REG
return 2;
case x86_64::FULL: // FULL
return 8;
case x86_64::D_REG: return 4;
case x86_64::OCT: return 16;
case x86_64::FPDBL: return 10;
case x86_64::BIT: return 0;
case x86_64::YMMS: return 32;
case x86_64::ZMMS: return 64;
default:
return 0; // Xiaozhu: return 0 as an indication of parsing junk.
}
break;
case Arch_ppc32: {
int reg_class = reg & 0x00ff0000;
if(reg_class == ppc32::FPR || reg_class == ppc32::FSR)
return 8;
return 4;
}
case Arch_ppc64: {
if((reg & 0x00ff0000) == aarch64::FPR)
return 16;
return 8;
}
case Arch_aarch32: assert(0); break;
case Arch_cuda: return 8;
case Arch_amdgpu_gfx908: {
int reg_class = (reg & 0x00ff0000);
if(reg_class == amdgpu_gfx908::SGPR || reg_class == amdgpu_gfx908::VGPR) {
return 4;
} else {
switch(reg & 0x00007f00) {
case amdgpu_gfx908::BITS_1:
case amdgpu_gfx908::BITS_2:
case amdgpu_gfx908::BITS_3:
case amdgpu_gfx908::BITS_4:
case amdgpu_gfx908::BITS_6:
case amdgpu_gfx908::BITS_7:
case amdgpu_gfx908::BITS_8: return 1;
case amdgpu_gfx908::BITS_9:
case amdgpu_gfx908::BITS_15:
case amdgpu_gfx908::BITS_16: return 2;
case amdgpu_gfx908::BITS_32: return 4;
case amdgpu_gfx908::BITS_48: return 6;
case amdgpu_gfx908::BITS_64: return 8;
case amdgpu_gfx908::BITS_128: return 16;
case amdgpu_gfx908::BITS_256: return 32;
case amdgpu_gfx908::BITS_512: return 64;
default:
common_parsing_printf(" unknown reg size %x\n", (unsigned int)reg);
assert(0);
}
}
}
break;
case Arch_amdgpu_gfx90a: {
int reg_class = (reg & 0x00ff0000);
if(reg_class == amdgpu_gfx90a::SGPR || reg_class == amdgpu_gfx90a::VGPR) {
return 4;
} else {
switch(reg & 0x00007f00) {
case amdgpu_gfx90a::BITS_1:
case amdgpu_gfx90a::BITS_2:
case amdgpu_gfx90a::BITS_3:
case amdgpu_gfx90a::BITS_4:
case amdgpu_gfx90a::BITS_6:
case amdgpu_gfx90a::BITS_7:
case amdgpu_gfx90a::BITS_8: return 1;
case amdgpu_gfx90a::BITS_9:
case amdgpu_gfx90a::BITS_15:
case amdgpu_gfx90a::BITS_16: return 2;
case amdgpu_gfx90a::BITS_32: return 4;
case amdgpu_gfx90a::BITS_48: return 6;
case amdgpu_gfx90a::BITS_64: return 8;
case amdgpu_gfx90a::BITS_128: return 16;
case amdgpu_gfx90a::BITS_256: return 32;
case amdgpu_gfx90a::BITS_512: return 64;
default:
common_parsing_printf(" unknown reg size %x\n", (unsigned int)reg);
assert(0);
}
}
}
break;
case Arch_amdgpu_gfx940: {
int reg_class = (reg & 0x00ff0000);
if(reg_class == amdgpu_gfx940::SGPR || reg_class == amdgpu_gfx940::VGPR) {
return 4;
} else {
switch(reg & 0x00007f00) {
case amdgpu_gfx940::BITS_1:
case amdgpu_gfx940::BITS_2:
case amdgpu_gfx940::BITS_3:
case amdgpu_gfx940::BITS_4:
case amdgpu_gfx940::BITS_6:
case amdgpu_gfx940::BITS_7:
case amdgpu_gfx940::BITS_8: return 1;
case amdgpu_gfx940::BITS_9:
case amdgpu_gfx940::BITS_15:
case amdgpu_gfx940::BITS_16: return 2;
case amdgpu_gfx940::BITS_32: return 4;
case amdgpu_gfx940::BITS_48: return 6;
case amdgpu_gfx940::BITS_64: return 8;
case amdgpu_gfx940::BITS_128: return 16;
case amdgpu_gfx940::BITS_256: return 32;
case amdgpu_gfx940::BITS_512: return 64;
default:
common_parsing_printf(" unknown reg size %x\n", (unsigned int)reg);
assert(0);
}
}
}
break;
case Arch_aarch64: {
if((reg & 0x00ff0000) == aarch64::FPR) {
switch(reg & 0x0000ff00) {
case aarch64::B_REG: return 1;
case aarch64::W_REG: return 2;
case aarch64::D_REG: return 4;
case aarch64::FULL:
case aarch64::HQ_REG: return 8;
case aarch64::Q_REG: return 16;
default: assert(0); return 0;
}
} else if((reg & 0x00ff0000) == aarch64::GPR || (reg & 0x00ff0000) == aarch64::SPR ||
(reg & 0x00ff0000) == aarch64::SYSREG || (reg & 0x00ff0000) == aarch64::FLAG)
switch(reg & 0x0000ff00) {
case aarch64::FULL: return 8;
case aarch64::D_REG: return 4;
case aarch64::BIT: return 0;
default: return 0;
}
else
return 4;
break;
}
case Arch_intelGen9: {
assert(0);
break;
}
case Arch_none: return 0;
}
return 0; // Unreachable, but disable warnings
}
bool MachRegister::operator<(const MachRegister& a) const { return (reg < a.reg); }
bool MachRegister::operator==(const MachRegister& a) const { return (reg == a.reg); }
MachRegister::operator signed int() const { return reg; }
signed int MachRegister::val() const { return reg; }
MachRegister MachRegister::getPC(Dyninst::Architecture arch) {
switch(arch) {
case Arch_x86: return x86::eip;
case Arch_x86_64: return x86_64::rip;
case Arch_ppc32: return ppc32::pc;
case Arch_ppc64: return ppc64::pc;
case Arch_aarch64: // aarch64: pc is not writable
return aarch64::pc;
case Arch_aarch32: return InvalidReg;
case Arch_cuda: return cuda::pc;
case Arch_intelGen9: return InvalidReg;
case Arch_amdgpu_gfx908: return amdgpu_gfx908::pc_all;
case Arch_amdgpu_gfx90a: return amdgpu_gfx90a::pc_all;
case Arch_amdgpu_gfx940: return amdgpu_gfx940::pc_all;
case Arch_none: return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getReturnAddress(Dyninst::Architecture arch) {
switch(arch) {
case Arch_x86: assert(0); break; // not implemented
case Arch_x86_64: assert(0); break; // not implemented
case Arch_ppc32: assert(0); break; // not implemented
case Arch_ppc64: assert(0); break; // not implemented
case Arch_aarch64: // aarch64: x30 stores the RA for current frame
return aarch64::x30;
case Arch_aarch32:
case Arch_cuda:
case Arch_amdgpu_gfx908:
case Arch_amdgpu_gfx90a:
case Arch_amdgpu_gfx940:
case Arch_intelGen9: assert(0); break;
case Arch_none: return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getFramePointer(Dyninst::Architecture arch) {
switch(arch) {
case Arch_x86: return x86::ebp;
case Arch_x86_64: return x86_64::rbp;
case Arch_ppc32: return ppc32::r1;
case Arch_ppc64: return ppc64::r1;
case Arch_aarch64: return aarch64::x29; // aarch64: frame pointer is X29 by convention
case Arch_aarch32:
case Arch_cuda:
case Arch_intelGen9:
case Arch_amdgpu_gfx908:
case Arch_amdgpu_gfx90a:
case Arch_amdgpu_gfx940:
case Arch_none: return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getStackPointer(Dyninst::Architecture arch) {
switch(arch) {
case Arch_x86: return x86::esp;
case Arch_x86_64: return x86_64::rsp;
case Arch_ppc32: return ppc32::r1;
case Arch_ppc64: return ppc64::r1;
case Arch_aarch64: return aarch64::sp; // aarch64: stack pointer is an independent register
case Arch_aarch32:
case Arch_cuda:
case Arch_intelGen9:
case Arch_amdgpu_gfx908:
case Arch_amdgpu_gfx90a:
case Arch_amdgpu_gfx940:
case Arch_none: return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getSyscallNumberReg(Dyninst::Architecture arch) {
switch(arch) {
case Arch_x86: return x86::eax;
case Arch_x86_64: return x86_64::rax;
case Arch_ppc32: return ppc32::r0;
case Arch_ppc64: return ppc64::r0;
case Arch_aarch64: return aarch64::x8;
case Arch_aarch32:
case Arch_cuda:
case Arch_intelGen9:
case Arch_amdgpu_gfx908:
case Arch_amdgpu_gfx90a:
case Arch_amdgpu_gfx940:
case Arch_none: return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getSyscallNumberOReg(Dyninst::Architecture arch) {
switch(arch) {
case Arch_x86: return x86::oeax;
case Arch_x86_64: return x86_64::orax;
case Arch_ppc32: return ppc32::r0;
case Arch_ppc64: return ppc64::r0;
case Arch_aarch64: return aarch64::x8;
case Arch_none: return InvalidReg;
default: assert(0); return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getSyscallReturnValueReg(Dyninst::Architecture arch) {
switch(arch) {
case Arch_x86: return x86::eax;
case Arch_x86_64: return x86_64::rax;
case Arch_ppc32: return ppc32::r3;
case Arch_ppc64: return ppc64::r3;
case Arch_aarch64: return aarch64::x0; // returned value is save in x0
case Arch_aarch32:
case Arch_cuda:
case Arch_intelGen9:
case Arch_amdgpu_gfx908:
case Arch_amdgpu_gfx90a:
case Arch_amdgpu_gfx940:
case Arch_none: return InvalidReg;
}
return InvalidReg;
}
MachRegister MachRegister::getArchRegFromAbstractReg(MachRegister abstract,
Dyninst::Architecture arch) {
switch(arch) {
case Arch_aarch64:
if(abstract == ReturnAddr)
return aarch64::x30;
if(abstract == FrameBase)
return aarch64::x29;
if(abstract == StackTop)
return aarch64::sp;
if(abstract == CFA)
assert(0); // don't know what to do
// not abstract, return arch reg
return abstract;
default: assert(0);
}
return Dyninst::InvalidReg;
}
MachRegister MachRegister::getZeroFlag(Dyninst::Architecture arch) {
switch(arch) {
case Arch_x86: return x86::zf;
case Arch_x86_64: return x86_64::zf;
case Arch_ppc32: return ppc32::cr0e;
case Arch_ppc64: return ppc64::cr0e;
case Arch_aarch64: return aarch64::z;
case Arch_aarch32:
case Arch_cuda:
case Arch_intelGen9:
case Arch_amdgpu_gfx908:
case Arch_amdgpu_gfx90a:
case Arch_amdgpu_gfx940:
case Arch_none: return InvalidReg;
}
return InvalidReg;
}
bool MachRegister::isPC() const {
if(*this == InvalidReg) return false;
return *this == getPC(getArchitecture());
}
bool MachRegister::isFramePointer() const {
if(*this == InvalidReg) return false;
return *this == FrameBase || *this == getFramePointer(getArchitecture());
}
bool MachRegister::isStackPointer() const {
if(*this == InvalidReg) return false;
return *this == StackTop || *this == getStackPointer(getArchitecture());
}
bool MachRegister::isSyscallNumberReg() const {
if(*this == InvalidReg) return false;
return *this == getSyscallNumberReg(getArchitecture());
}
bool MachRegister::isSyscallReturnValueReg() const {
if(*this == InvalidReg) return false;
return *this == getSyscallReturnValueReg(getArchitecture());
}
bool MachRegister::isFlag() const {
int regC = regClass();
switch(getArchitecture()) {
case Arch_x86: return regC == x86::FLAG;
case Arch_x86_64: return regC == x86_64::FLAG;
case Arch_aarch64: return regC == aarch64::FLAG;
case Arch_ppc32:
case Arch_ppc64: {
// For power, we have a different register representation.
// We do not use the subrange field for MachReigsters
// and all lower 32 bits are base ID
int baseID = reg & 0x0000FFFF;
return (baseID <= 731 && baseID >= 700) || (baseID <= 629 && baseID >= 621);
}
case Arch_amdgpu_gfx908:
case Arch_amdgpu_gfx90a:
case Arch_amdgpu_gfx940: {
return (reg & 0x0000F000);
}
case Arch_cuda: return false;
default: assert(!"Not implemented!");
}
return false;
}
bool MachRegister::isZeroFlag() const {
if(*this == InvalidReg) return false;
switch(getArchitecture()) {
case Arch_ppc32:
case Arch_ppc64: {
// For power, we have a different register representation.
// We do not use the subrange field for MachReigsters
// and all lower 32 bits are base ID
int baseID = reg & 0x0000FFFF;
return (baseID <= 731 && baseID >= 700 && baseID % 4 == 2) ||
(baseID <= 628 && baseID >= 621);
}
default:
return *this == getZeroFlag(getArchitecture());
}
return false;
}
// reg_idx needs to be set as the offset from base register
// offset needs to be set as the offset inside the register
static void getAmdgpuGfx908RoseRegister(int& reg_class, int& reg_idx, int& offset,
const int& reg) {
signed int category = (reg & 0x00ff0000);
signed int baseID = (reg & 0x000000ff);
offset = 0;
reg_idx = baseID;
switch(category) {
case amdgpu_gfx908::SGPR: {
reg_class = amdgpu_regclass_sgpr;
break;
}
case amdgpu_gfx908::VGPR: {
reg_class = amdgpu_regclass_vgpr;
break;
}
case amdgpu_gfx908::PC: {
reg_class = amdgpu_regclass_pc;
reg_idx = amdgpu_pc;
break;
}
case amdgpu_gfx908::HWR: {
reg_class = amdgpu_regclass_pc;
reg_idx = amdgpu_pc;
break;
}
default: {
assert(0 && "unsupported register type for amdgpu gfx908");
}
}
return;
}
static void getAmdgpuGfx90aRoseRegister(int& reg_class, int& reg_idx, int& offset,
const int& reg) {
signed int category = (reg & 0x00ff0000);
signed int baseID = (reg & 0x000000ff);
offset = 0;
reg_idx = baseID;
switch(category) {
case amdgpu_gfx90a::SGPR: {
reg_class = amdgpu_regclass_sgpr;
break;
}
case amdgpu_gfx90a::VGPR: {
reg_class = amdgpu_regclass_vgpr;
break;
}
case amdgpu_gfx90a::PC: {
reg_class = amdgpu_regclass_pc;
reg_idx = amdgpu_pc;
break;
}
case amdgpu_gfx90a::HWR: {
reg_class = amdgpu_regclass_pc;
reg_idx = amdgpu_pc;
break;
}
default: {
assert(0 && "unsupported register type for amdgpu gfx90a");
}
}
return;
}
static void getAmdgpuGfx940RoseRegister(int& reg_class, int& reg_idx, int& offset,
const int& reg) {
signed int category = (reg & 0x00ff0000);
signed int baseID = (reg & 0x000000ff);
offset = 0;
reg_idx = baseID;
switch(category) {
case amdgpu_gfx940::SGPR: {
reg_class = amdgpu_regclass_sgpr;
break;
}
case amdgpu_gfx940::VGPR: {
reg_class = amdgpu_regclass_vgpr;
break;
}
case amdgpu_gfx940::PC: {
reg_class = amdgpu_regclass_pc;
reg_idx = amdgpu_pc;
break;
}
case amdgpu_gfx940::HWR: {
reg_class = amdgpu_regclass_pc;
reg_idx = amdgpu_pc;
break;
}
default: {
assert(0 && "unsupported register type for amdgpu gfx940");
}
}
return;
}
/* This function should has a boolean return value
* to indicate whether there is a corresponding
* ROSE register.
*
* Since historically, this function does not
* have a return value. We set c to -1 to represent
* error cases
* c is set to regClass
* n is set to regNum
* p is set to regPosition
* see dataflowAPI/src/ExpressionConversionVisitor.C
*/
void MachRegister::getROSERegister(int& c, int& n, int& p) {
// Rose: class, number, position
// Dyninst: category, base id, subrange
signed int category = (reg & 0x00ff0000);
signed int subrange = (reg & 0x0000ff00);
signed int baseID = (reg & 0x000000ff);
switch(getArchitecture()) {
case Arch_amdgpu_gfx908: {
getAmdgpuGfx908RoseRegister(c, n, p, reg);
return;
}
case Arch_amdgpu_gfx90a: {
getAmdgpuGfx90aRoseRegister(c, n, p, reg);
return;
}
case Arch_amdgpu_gfx940: {
getAmdgpuGfx940RoseRegister(c, n, p, reg);
return;
}
case Arch_x86:
switch(category) {
case x86::GPR:
c = x86_regclass_gpr;
switch(baseID) {
case x86::BASEA: n = x86_gpr_ax; break;
case x86::BASEC: n = x86_gpr_cx; break;
case x86::BASED: n = x86_gpr_dx; break;
case x86::BASEB: n = x86_gpr_bx; break;
case x86::BASESP: n = x86_gpr_sp; break;
case x86::BASEBP: n = x86_gpr_bp; break;
case x86::BASESI: n = x86_gpr_si; break;
case x86::BASEDI: n = x86_gpr_di; break;
default: n = 0; break;
}
break;
case x86::SEG:
c = x86_regclass_segment;
switch(baseID) {
case 0x0: n = x86_segreg_ds; break;
case 0x1: n = x86_segreg_es; break;
case 0x2: n = x86_segreg_fs; break;
case 0x3: n = x86_segreg_gs; break;
case 0x4: n = x86_segreg_cs; break;
case 0x5: n = x86_segreg_ss; break;
default: n = 0; break;
}
break;
case x86::FLAG:
c = x86_regclass_flags;
switch(baseID) {
case x86::CF: n = x86_flag_cf; break;
case x86::PF: n = x86_flag_pf; break;
case x86::AF: n = x86_flag_af; break;
case x86::ZF: n = x86_flag_zf; break;
case x86::SF: n = x86_flag_sf; break;
case x86::TF: n = x86_flag_tf; break;
case x86::IF: n = x86_flag_if; break;
case x86::DF: n = x86_flag_df; break;
case x86::OF: n = x86_flag_of; break;
default: assert(0); break;
}
break;
case x86::MISC: c = x86_regclass_unknown; break;
case x86::XMM:
c = x86_regclass_xmm;
n = baseID;
break;
case x86::MMX:
c = x86_regclass_mm;
n = baseID;
break;
case x86::CTL:
c = x86_regclass_cr;
n = baseID;
break;
case x86::DBG:
c = x86_regclass_dr;
n = baseID;
break;
case x86::TST: c = x86_regclass_unknown; break;
case 0:
switch(baseID) {
case 0x10:
c = x86_regclass_ip;
n = 0;
break;
default: c = x86_regclass_unknown; break;
}
break;
default:
common_parsing_printf("Unknown category '%d' for Arch_x86\n", category);
break;
}
break;
case Arch_x86_64:
switch(category) {
case x86_64::GPR:
c = x86_regclass_gpr;
switch(baseID) {
case x86_64::BASEA: n = x86_gpr_ax; break;
case x86_64::BASEC: n = x86_gpr_cx; break;
case x86_64::BASED: n = x86_gpr_dx; break;
case x86_64::BASEB: n = x86_gpr_bx; break;
case x86_64::BASESP: n = x86_gpr_sp; break;
case x86_64::BASEBP: n = x86_gpr_bp; break;
case x86_64::BASESI: n = x86_gpr_si; break;
case x86_64::BASEDI: n = x86_gpr_di; break;
case x86_64::BASE8: n = x86_gpr_r8; break;
case x86_64::BASE9: n = x86_gpr_r9; break;
case x86_64::BASE10: n = x86_gpr_r10; break;
case x86_64::BASE11: n = x86_gpr_r11; break;
case x86_64::BASE12: n = x86_gpr_r12; break;
case x86_64::BASE13: n = x86_gpr_r13; break;
case x86_64::BASE14: n = x86_gpr_r14; break;
case x86_64::BASE15: n = x86_gpr_r15; break;
default: n = 0; break;
}
break;
case x86_64::SEG:
c = x86_regclass_segment;
switch(baseID) {
case 0x0: n = x86_segreg_ds; break;
case 0x1: n = x86_segreg_es; break;
case 0x2: n = x86_segreg_fs; break;
case 0x3: n = x86_segreg_gs; break;
case 0x4: n = x86_segreg_cs; break;
case 0x5: n = x86_segreg_ss; break;
default: n = 0; break;
}
break;
case x86_64::FLAG:
c = x86_regclass_flags;
switch(baseID) {
case x86_64::CF: n = x86_flag_cf; break;
case x86_64::PF: n = x86_flag_pf; break;
case x86_64::AF: n = x86_flag_af; break;
case x86_64::ZF: n = x86_flag_zf; break;
case x86_64::SF: n = x86_flag_sf; break;
case x86_64::TF: n = x86_flag_tf; break;
case x86_64::IF: n = x86_flag_if; break;
case x86_64::DF: n = x86_flag_df; break;
case x86_64::OF: n = x86_flag_of; break;
default:
c = -1;
return;
break;
}
break;
case x86_64::MISC: c = x86_regclass_unknown; break;
case x86_64::KMASK:
c = x86_regclass_kmask;
n = baseID;
break;
case x86_64::ZMM:
c = x86_regclass_zmm;
n = baseID;
break;
case x86_64::YMM:
c = x86_regclass_ymm;
n = baseID;
break;
case x86_64::XMM:
c = x86_regclass_xmm;
n = baseID;
break;
case x86_64::MMX:
c = x86_regclass_mm;
n = baseID;
break;
case x86_64::CTL:
c = x86_regclass_cr;
n = baseID;
break;
case x86_64::DBG:
c = x86_regclass_dr;
n = baseID;
break;
case x86_64::TST: c = x86_regclass_unknown; break;
case 0:
switch(baseID) {
case 0x10:
c = x86_regclass_ip;
n = 0;
break;
default: c = x86_regclass_unknown; break;
}
break;
default:
common_parsing_printf("Unknown category '%d' for Arch_x86_64\n", category);
break;
}
break;
case Arch_ppc32: {
baseID = reg & 0x0000FFFF;
n = baseID;
switch(category) {
case ppc32::GPR: c = powerpc_regclass_gpr; break;
case ppc32::FPR:
case ppc32::FSR: c = powerpc_regclass_fpr; break;
case ppc32::SPR: {
if(baseID < 613) {
c = powerpc_regclass_spr;
} else if(baseID < 621) {
c = powerpc_regclass_sr;
} else {
c = powerpc_regclass_cr;
n = 0;
p = baseID - 621;
}
} break;
default: c = -1; return;
}
return;
} break;
case Arch_ppc64: {
baseID = reg & 0x0000FFFF;
n = baseID;
switch(category) {
case ppc64::GPR: c = powerpc_regclass_gpr; break;
case ppc64::FPR:
case ppc64::FSR: c = powerpc_regclass_fpr; break;
case ppc64::SPR: {
if(baseID < 613) {
c = powerpc_regclass_spr;
} else if(baseID < 621) {
c = powerpc_regclass_sr;
} else {
c = powerpc_regclass_cr;
n = 0;
p = baseID - 621;
}
} break;
default: c = -1; return;
}
return;
} break;
case Arch_aarch64: {
p = 0;
switch(category) {
case aarch64::GPR: {
c = armv8_regclass_gpr;
int regnum = baseID - (aarch64::x0 & 0xFF);
n = armv8_gpr_r0 + regnum;
} break;
case aarch64::SPR: {
n = 0;
if(baseID == (aarch64::pstate & 0xFF)) {
c = armv8_regclass_pstate;
} else if(baseID == (aarch64::xzr & 0xFF) || baseID == (aarch64::wzr & 0xFF)) {
c = armv8_regclass_gpr;
n = armv8_gpr_zr;
} else if(baseID == (aarch64::pc & 0xFF)) {
c = armv8_regclass_pc;
} else if(baseID == (aarch64::sp & 0xFF) || baseID == (aarch64::wsp & 0xFF)) {
c = armv8_regclass_sp;
}
} break;
case aarch64::FPR: {
c = armv8_regclass_simd_fpr;
int firstRegId;
switch(reg & 0xFF00) {
case aarch64::Q_REG: firstRegId = (aarch64::q0 & 0xFF); break;
case aarch64::HQ_REG:
firstRegId = (aarch64::hq0 & 0xFF);
p = 64;
break;
case aarch64::FULL: firstRegId = (aarch64::d0 & 0xFF); break;
case aarch64::D_REG: firstRegId = (aarch64::s0 & 0xFF); break;
case aarch64::W_REG: firstRegId = (aarch64::h0 & 0xFF); break;
case aarch64::B_REG: firstRegId = (aarch64::b0 & 0xFF); break;
default: assert(!"invalid register subcategory for ARM64!"); break;
}
n = armv8_simdfpr_v0 + (baseID - firstRegId);
} break;
case aarch64::FLAG: {
c = armv8_regclass_pstate;
n = 0;
switch(baseID) {
case aarch64::N_FLAG: p = armv8_pstatefield_n; break;
case aarch64::Z_FLAG: p = armv8_pstatefield_z; break;
case aarch64::V_FLAG: p = armv8_pstatefield_v; break;
case aarch64::C_FLAG: p = armv8_pstatefield_c; break;
default: c = -1; return;
}
} break;
default:
// We do not want to assert here.
// Set these output variable to invalid values and let the
// semantics code to throw exceptions
p = -1;
c = -1;
n = -1;
break;
}
return;
} break;
default:
c = x86_regclass_unknown;
n = 0;
break;
}
switch(getArchitecture()) {
case Arch_x86:
switch(subrange) {
case x86::OCT:
case x86::FPDBL: p = x86_regpos_qword; break;
case x86::H_REG: p = x86_regpos_high_byte; break;
case x86::L_REG: p = x86_regpos_low_byte; break;
case x86::W_REG: p = x86_regpos_word; break;
case x86::FULL:
case x86_64::D_REG: p = x86_regpos_dword; break;
case x86::BIT: p = x86_regpos_all; break;
default:
common_parsing_printf("Unknown subrange value '%d' for Arch_x86\n", subrange);
break;
}
break;
case Arch_x86_64:
switch(subrange) {
case x86::FULL:
case x86::OCT:
case x86::FPDBL: p = x86_regpos_qword; break;
case x86::H_REG: p = x86_regpos_high_byte; break;
case x86::L_REG: p = x86_regpos_low_byte; break;
case x86::W_REG: p = x86_regpos_word; break;
case x86_64::D_REG: p = x86_regpos_dword; break;
case x86::BIT: p = x86_regpos_all; break;
default:
common_parsing_printf("Unknown subrange value '%d' for Arch_x86_64\n", subrange);
break;
}
break;
case Arch_aarch64: {
c = -1;
return;
}
default: p = x86_regpos_unknown;
}
}
MachRegister MachRegister::DwarfEncToReg(int encoding, Dyninst::Architecture arch) {
switch(arch) {
case Arch_x86:
switch(encoding) {
case 0: return Dyninst::x86::eax;
case 1: return Dyninst::x86::ecx;
case 2: return Dyninst::x86::edx;
case 3: return Dyninst::x86::ebx;
case 4: return Dyninst::x86::esp;
case 5: return Dyninst::x86::ebp;
case 6: return Dyninst::x86::esi;
case 7: return Dyninst::x86::edi;
case 8: return Dyninst::x86::eip;
case 9: return Dyninst::x86::flags;
case 10: return Dyninst::InvalidReg;
case 11: return Dyninst::x86::st0;