New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
New instruction decoding problem in master branch #88
Comments
The issue is, |
Current fix seems to lead to an assertion failure at |
Could you post that stacktrace of your issue? I'm getting an assert in instructionAPI and I think your assert was in common. |
Here it is.
|
I think I figured it out, there was a table indexing issue where the decoder went passed the end of the table (oops). |
We are moving on the right direction, but not there yet. Objdump shows:
I got
The operand order and the operand size (ebx vs rbx) seem different. |
You're right, I added them in AT&T syntax order and dyninst was uses Intel order. |
I don't think there will be any semantics for that instruction because I just added it to dyninst, is that okay? |
After adding that change, I am now getting an assert in the x86 instruction semantics:
assert message:
|
In the xhpl binary provided from Rice, objdump shows the following instruction at the given address:
9aeef7: 49 63 fa movslq %r10d,%rdi
Current master branch decodes the instruction as
9aeef7 : arpl R10W, DI
The text was updated successfully, but these errors were encountered: