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I have a requirement to monitor data on a serial interface.
I plan to use the two standard UARTS on the Pico to do this (one to monitor the data being transmitted by the controller and one to monitor data sent by the connected device(s)).
The protocol in use has a 9 bit per byte structure where the 9th bit is used as follows
The controller SETS (1) the 9th bit if it is transmitting an address and CLEARS (0) it if transmitting data
The slave device(s) CLEARS (0) the 9th bit when sending data EXCEPT for the last byte where the 9th bit is SET (1).
When monitoring these signals I'd like to be able to determine whether the controller is sending and address or data and whether the slave has finished sending its reply.
According to the RP2040 data sheet the uarts can be set to 8 bits plus a fixed parity bit using the PEN, EPS and SPS bits of the Line Control Register. Additionally the receive FIFO is 12 bits wide with the additional four bits being Framing error, Parity Error, Break Error and Overrun Error.
So I figure that if I can set the bits in the Line Control register to have have a '0' as the parity bit I can detect Address transmission from the controller or end of data from the slave device by monitoring the Parity Error bit that accompanies the data from the FIFO.
Do you have any suggestions how I might be able to do that as none of the standard Arduino serial interface functions have any facility for this.
Thanks
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I have a requirement to monitor data on a serial interface.
I plan to use the two standard UARTS on the Pico to do this (one to monitor the data being transmitted by the controller and one to monitor data sent by the connected device(s)).
The protocol in use has a 9 bit per byte structure where the 9th bit is used as follows
When monitoring these signals I'd like to be able to determine whether the controller is sending and address or data and whether the slave has finished sending its reply.
According to the RP2040 data sheet the uarts can be set to 8 bits plus a fixed parity bit using the PEN, EPS and SPS bits of the Line Control Register. Additionally the receive FIFO is 12 bits wide with the additional four bits being Framing error, Parity Error, Break Error and Overrun Error.
So I figure that if I can set the bits in the Line Control register to have have a '0' as the parity bit I can detect Address transmission from the controller or end of data from the slave device by monitoring the Parity Error bit that accompanies the data from the FIFO.
Do you have any suggestions how I might be able to do that as none of the standard Arduino serial interface functions have any facility for this.
Thanks
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