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ControlFlowEvaluator.cpp
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ControlFlowEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2018 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <stddef.h> // for size_t
#include <stdint.h> // for int32_t, uint8_t, etc
#include <stdio.h> // for NULL, printf
#include "codegen/CodeGenerator.hpp" // for CodeGenerator, etc
#include "codegen/FrontEnd.hpp" // for TR_FrontEnd, etc
#include "codegen/InstOpCode.hpp" // for InstOpCode, etc
#include "codegen/Instruction.hpp" // for Instruction, etc
#include "codegen/Linkage.hpp" // for Linkage, REGNUM
#include "codegen/Machine.hpp" // for Machine
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp" // for RealRegister, etc
#include "codegen/RecognizedMethods.hpp"
#include "codegen/Register.hpp" // for Register
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterPair.hpp" // for RegisterPair
#include "codegen/TreeEvaluator.hpp"
#include "codegen/S390Evaluator.hpp"
#include "compile/Compilation.hpp" // for Compilation, etc
#include "compile/Method.hpp" // for TR_Method
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "compile/VirtualGuard.hpp" // for TR_VirtualGuard
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "env/CHTable.hpp" // for TR_AOTGuardSite, etc
#endif
#include "env/TRMemory.hpp" // for TR_HeapMemory, etc
#include "env/jittypes.h" // for intptrj_t, uintptrj_t
#include "il/Block.hpp" // for Block
#include "il/DataTypes.hpp" // for DataTypes::Int32, etc
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp" // for ILOpCode, etc
#include "il/Node.hpp" // for Node, etc
#include "il/Node_inlines.hpp"
#include "il/Symbol.hpp" // for Symbol
#include "il/SymbolReference.hpp" // for SymbolReference
#include "il/TreeTop.hpp" // for TreeTop
#include "il/TreeTop_inlines.hpp" // for TreeTop::getNode, etc
#include "il/symbol/AutomaticSymbol.hpp" // for AutomaticSymbol
#include "il/symbol/LabelSymbol.hpp" // for LabelSymbol, etc
#include "il/symbol/MethodSymbol.hpp" // for MethodSymbol
#include "il/symbol/ResolvedMethodSymbol.hpp"
#include "infra/Assert.hpp" // for TR_ASSERT
#include "infra/Bit.hpp" // for leadingZeroes
#include "infra/BitVector.hpp" // for TR_BitVector
#include "infra/List.hpp" // for List
#include "ras/Debug.hpp" // for TR_DebugBase
#include "ras/Delimiter.hpp" // for Delimiter
#include "z/codegen/BinaryAnalyser.hpp"
#include "z/codegen/BinaryCommutativeAnalyser.hpp"
#include "z/codegen/CompareAnalyser.hpp"
#include "z/codegen/S390GenerateInstructions.hpp"
#include "z/codegen/S390HelperCallSnippet.hpp"
#include "z/codegen/S390Instruction.hpp"
#include "z/codegen/S390OutOfLineCodeSection.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "z/codegen/S390Register.hpp"
#endif
#include "z/codegen/TranslateEvaluator.hpp"
extern TR::Instruction *
generateS390PackedCompareAndBranchOps(TR::Node * node,
TR::CodeGenerator * cg,
TR::InstOpCode::S390BranchCondition fBranchOpCond,
TR::InstOpCode::S390BranchCondition rBranchOpCond,
TR::InstOpCode::S390BranchCondition &retBranchOpCond,
TR::LabelSymbol *branchTarget = NULL);
//#define TRACE_EVAL
#if defined(TRACE_EVAL)
#define EVAL_BLOCK
#if defined (EVAL_BLOCK)
#define PRINT_ME(string,node,cg) TR::Delimiter evalDelimiter(TR::comp(),TR::comp()->getOption(TR_TraceCG),"EVAL", string)
#else
extern void PRINT_ME(char * string, TR::Node * node, TR::CodeGenerator * cg);
#endif
#else
#define PRINT_ME(string,node,cg)
#endif
extern TR::Register *
iDivRemGenericEvaluator(TR::Node * node, TR::CodeGenerator * cg, bool isDivision, TR::MemoryReference * divchkDivisorMR);
TR::InstOpCode::S390BranchCondition generateS390CompareOps(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::S390BranchCondition fBranchOpCond, TR::InstOpCode::S390BranchCondition rBranchOpCond);
TR::Instruction * generateS390CompareOps(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::S390BranchCondition fBranchOpCond, TR::InstOpCode::S390BranchCondition rBranchOpCond, TR::LabelSymbol *branchTarget);
void killRegisterIfNotLocked(TR::CodeGenerator * cg, TR::RealRegister::RegNum reg, TR::Instruction * instr , TR::RegisterDependencyConditions * deps = NULL)
{
TR::Register *dummy = NULL;
if (cg->machine()->getS390RealRegister(reg)->getState() != TR::RealRegister::Locked)
{
if (deps == NULL)
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
dummy = cg->allocateRegister();
deps->addPostCondition(dummy, TR::RealRegister::GPR4);
dummy->setPlaceholderReg();
instr->setDependencyConditions(deps);
cg->stopUsingRegister(dummy);
}
}
/**
* Helper to generate virtual guard if node is so flagged. In 32 bit mode the NOP instruction,
* a BRC, has only a +ve displacement of 2^12 (4k), and so in some cases it is not safe to use it
* on a G5 platform (no problems with BRCL). At this point, since instructions have not yet
* been generated, there is no good way to guage how far away the label will be, so we cannot
* even determine if it is safe. Will never be enabled for G5 hardware
* Note that some instructions *must* have a virtual guard generated for them.
*/
static bool
virtualGuardHelper(TR::Node * node, TR::CodeGenerator * cg)
{
#ifdef J9_PROJECT_SPECIFIC
TR::Compilation *comp = cg->comp();
if ((!node->isNopableInlineGuard() && !node->isHCRGuard() && !node->isOSRGuard()) ||
!cg->getSupportsVirtualGuardNOPing())
{
return false;
}
TR_VirtualGuard * virtualGuard = comp->findVirtualGuardInfo(node);
if (!node->isHCRGuard() && !node->isOSRGuard() && !(comp->performVirtualGuardNOPing() &&
comp->isVirtualGuardNOPingRequired(virtualGuard)) &&
virtualGuard->canBeRemoved())
{
return false;
}
if (node->getOpCodeValue() != TR::ificmpne && node->getOpCodeValue() != TR::iflcmpne && node->getOpCodeValue() != TR::ifacmpne)
{
//TR_ASSERT( 0, "virtualGuardHelper: not expecting reversed comparison");
return false;
}
TR_VirtualGuardSite * site = NULL;
if (comp->compileRelocatableCode())
{
site = (TR_VirtualGuardSite *)comp->addAOTNOPSite();
TR_AOTGuardSite *aotSite = (TR_AOTGuardSite *)site;
aotSite->setType(virtualGuard->getKind());
aotSite->setNode(node);
switch (virtualGuard->getKind())
{
case TR_DirectMethodGuard:
case TR_NonoverriddenGuard:
case TR_InterfaceGuard:
case TR_MethodEnterExitGuard:
case TR_HCRGuard:
//case TR_AbstractGuard:
aotSite->setGuard(virtualGuard);
break;
case TR_ProfiledGuard:
break;
default:
TR_ASSERT(0, "got AOT guard in node but virtual guard not one of known guards supported for AOT. Guard: %d", virtualGuard->getKind());
break;
}
}
else if (!node->isSideEffectGuard())
{
TR_VirtualGuard * virtualGuard = comp->findVirtualGuardInfo(node);
site = virtualGuard->addNOPSite();
}
else
{
site = comp->addSideEffectNOPSite();
}
TR::RegisterDependencyConditions * deps;
if (node->getNumChildren() == 3)
{
TR::Node * third = node->getChild(2);
cg->evaluate(third);
deps = generateRegisterDependencyConditions(cg, third, 0);
}
else
{
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions((uint16_t) 0, (uint16_t) 0, cg);
}
if(virtualGuard->shouldGenerateChildrenCode())
cg->evaluateChildrenWithMultipleRefCount(node);
generateVirtualGuardNOPInstruction(cg, node, site, deps, node->getBranchDestination()->getNode()->getLabel());
cg->recursivelyDecReferenceCount(node->getFirstChild());
cg->recursivelyDecReferenceCount(node->getSecondChild());
traceMsg(comp, "virtualGuardHelper for %s %s\n",
comp->getDebug()?comp->getDebug()->getVirtualGuardKindName(virtualGuard->getKind()):"???Guard" , virtualGuard->mergedWithHCRGuard()?"merged with HCRGuard":"");
return true;
#else
return false;
#endif
}
//////////////////////////////////////////////////////////////////////////////////////////////////
// Long Compare Helper code
//
#define CMP4BOOLEAN true
#define CMP4CONTROLFLOW false
static TR::Register *
generateS390lcmpEvaluator(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic brOpCode, TR::InstOpCode::S390BranchCondition condCmpHighFalse, TR::InstOpCode::S390BranchCondition condCmpHighTrue,
TR::InstOpCode::S390BranchCondition condCmpLowTrue, bool isBoolean)
{
TR::LabelSymbol * falseTarget;
TR::LabelSymbol * isFalse = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol * trueTarget;
TR::LabelSymbol * isTrue = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
bool internalControlFlowStarted=false;
TR::Register * targetRegister = NULL;
TR::Node * firstChild = node->getFirstChild();
TR::Node * secondChild = node->getSecondChild();
TR::RegisterDependencyConditions * deps = NULL;
bool isGRAEnabled = false;
TR::RegisterPair * targetRegisterPair = NULL;
bool isUnsignedCmp = node->getOpCode().isUnsignedCompare();
TR::MemoryReference * lowLogicalOpMR = NULL;
TR::MemoryReference * highLogicalOpMR = NULL;
int32_t numGlobalDeps = 0;
if (node->getNumChildren() == 3)
{
TR::Node * thirdChild = node->getChild(2);
numGlobalDeps = thirdChild->getNumChildren();
}
TR::Register * targetLogicalOpReg = NULL;
TR::Register * sourceLogicalOpReg = NULL;
bool splitLogicalOp = false;
TR::InstOpCode::Mnemonic logicalRX=TR::InstOpCode::BAD;
TR::InstOpCode::Mnemonic logicalRR=TR::InstOpCode::BAD;
if (!isBoolean && numGlobalDeps < 8 && // Needs to be tuned
(node->getOpCodeValue()==TR::iflcmpne || node->getOpCodeValue()==TR::iflcmpeq ||
node->getOpCodeValue()==TR::iflucmpne || node->getOpCodeValue()==TR::iflucmpeq ) &&
secondChild->getOpCode().isLoadConst() && secondChild->getLongInt()==0)
{
TR::Register * firstReg = cg->evaluate(firstChild);
TR::Register * workReg = NULL;
trueTarget = node->getBranchDestination()->getNode()->getLabel();
TR_ClobberEvalData data;
if (cg->canClobberNodesRegister(firstChild, 1, &data) &&
data.canClobberHighWord())
{
workReg = firstReg->getHighOrder();
}
else
{
workReg = cg->allocateRegister();
generateRRInstruction(cg, TR::InstOpCode::LR, node, workReg, firstReg->getHighOrder());
}
if (node->getNumChildren() == 3)
{
TR::Node * thirdChild = node->getChild(2);
cg->evaluate(thirdChild);
deps = generateRegisterDependencyConditions(cg, thirdChild, 6);
deps->addPostConditionIfNotAlreadyInserted(workReg, TR::RealRegister::AssignAny);
cg->decReferenceCount(thirdChild);
}
generateRRInstruction(cg, TR::InstOpCode::OR, node, workReg, firstReg->getLowOrder());
TR::InstOpCode::S390BranchCondition cmpOpCode = TR::InstOpCode::COND_BE;
if (node->getOpCodeValue()==TR::iflcmpne || node->getOpCodeValue()==TR::iflucmpne)
{
cmpOpCode = TR::InstOpCode::COND_BNE;
}
generateS390BranchInstruction(cg, brOpCode, cmpOpCode, node, trueTarget, deps);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
cg->stopUsingRegister(workReg);
return NULL;
}
else if (numGlobalDeps < 8 && // Needs to be tuned
(node->getOpCodeValue()==TR::iflcmpne || node->getOpCodeValue()==TR::iflcmpeq ||
node->getOpCodeValue()==TR::iflucmpne || node->getOpCodeValue()==TR::iflucmpeq ) &&
firstChild->getReferenceCount()==1 && firstChild->getRegister()==NULL &&
secondChild->getOpCode().isLoadConst() && secondChild->getLongInt()==0 &&
secondChild->getRegister()==NULL &&
(firstChild->getOpCodeValue() == TR::land ||
firstChild->getOpCodeValue() == TR::lor ||
firstChild->getOpCodeValue() == TR::lxor ) )
{
splitLogicalOp = true;
TR::Node * firstLogicalOpChild;
TR::Node * secondLogicalOpChild;
if (firstChild->getOpCodeValue()== TR::land)
{
logicalRX = TR::InstOpCode::N;
logicalRR = TR::InstOpCode::NR;
}
else if (firstChild->getOpCodeValue()== TR::lor)
{
logicalRX = TR::InstOpCode::O;
logicalRR = TR::InstOpCode::OR;
}
else if (firstChild->getOpCodeValue()== TR::lxor)
{
logicalRX = TR::InstOpCode::X;
logicalRR = TR::InstOpCode::XR;
}
else
{
TR_ASSERT( 0,"generateS390lcmpEvaluator: unknown opcode \n");
}
TR_S390BinaryCommutativeAnalyser tempLogicalOp(cg);
if (cg->whichChildToEvaluate(firstChild) == 0)
{
firstLogicalOpChild = firstChild->getFirstChild();
secondLogicalOpChild = firstChild->getSecondChild();
}
else
{
firstLogicalOpChild = firstChild->getSecondChild();
secondLogicalOpChild = firstChild->getFirstChild();
}
TR::Register * firstLogicalOpRegister = firstLogicalOpChild->getRegister();
TR::Register * secondLogicalOpRegister = secondLogicalOpChild->getRegister();
tempLogicalOp.setInputs(firstLogicalOpChild, firstLogicalOpRegister,
secondLogicalOpChild, secondLogicalOpRegister,
false, false, cg->comp());
if (tempLogicalOp.getEvalChild1())
{
firstLogicalOpRegister = cg->evaluate(firstLogicalOpChild);
}
if (tempLogicalOp.getEvalChild2())
{
secondLogicalOpRegister = cg->evaluate(secondLogicalOpChild);
}
tempLogicalOp.remapInputs(firstLogicalOpChild, firstLogicalOpRegister,
secondLogicalOpChild, secondLogicalOpRegister);
if (tempLogicalOp.getOpReg1Reg2())
{
generateRRInstruction(cg, logicalRR, firstChild, firstLogicalOpRegister->getHighOrder(), secondLogicalOpRegister->getHighOrder());
targetLogicalOpReg = firstLogicalOpRegister->getLowOrder();
sourceLogicalOpReg = secondLogicalOpRegister->getLowOrder();
firstChild->setRegister(firstLogicalOpRegister);
}
else if (tempLogicalOp.getOpReg2Reg1())
{
generateRRInstruction(cg, logicalRR, firstChild, secondLogicalOpRegister->getHighOrder(), firstLogicalOpRegister->getHighOrder());
targetLogicalOpReg = secondLogicalOpRegister->getLowOrder();
sourceLogicalOpReg = firstLogicalOpRegister->getLowOrder();
firstChild->setRegister(secondLogicalOpRegister);
}
else if (tempLogicalOp.getCopyRegs())
{
TR::RegisterPair * tempReg = cg->allocateConsecutiveRegisterPair(cg->allocateRegister(), cg->allocateRegister());
generateRRInstruction(cg, TR::InstOpCode::LR, firstChild, tempReg->getHighOrder(), firstLogicalOpRegister->getHighOrder());
generateRRInstruction(cg, TR::InstOpCode::LR, firstChild, tempReg->getLowOrder(), firstLogicalOpRegister->getLowOrder());
generateRRInstruction(cg, logicalRR, firstChild, tempReg->getHighOrder(), secondLogicalOpRegister->getHighOrder());
targetLogicalOpReg = tempReg->getLowOrder();
sourceLogicalOpReg = secondLogicalOpRegister->getLowOrder();
firstChild->setRegister(tempReg);
}
else
{
TR_ASSERT( !tempLogicalOp.getInvalid(), "TR_S390ControlFlowEvaluatore::invalid case\n");
if (tempLogicalOp.getOpReg3Mem2() || tempLogicalOp.getOpReg1Mem2())
{
TR::RegisterPair * tempReg = (TR::RegisterPair *) firstLogicalOpRegister;
if (tempLogicalOp.getOpReg3Mem2())
{
tempReg = cg->allocateConsecutiveRegisterPair(cg->allocateRegister(),
cg->allocateRegister());
generateRRInstruction(cg, TR::InstOpCode::LR, firstChild, tempReg->getHighOrder(),
firstLogicalOpRegister->getHighOrder());
generateRRInstruction(cg, TR::InstOpCode::LR, firstChild, tempReg->getLowOrder(),
firstLogicalOpRegister->getLowOrder());
}
highLogicalOpMR = generateS390MemoryReference(secondLogicalOpChild, cg);
lowLogicalOpMR = generateS390MemoryReference(*highLogicalOpMR, 4, cg);
generateRXInstruction(cg, logicalRX, firstChild, tempReg->getHighOrder(), highLogicalOpMR);
targetLogicalOpReg = tempReg->getLowOrder();
firstChild->setRegister(tempReg);
}
else
{
TR::RegisterPair * tempReg = (TR::RegisterPair *) secondLogicalOpRegister;
if (tempLogicalOp.getOpReg3Mem1())
{
tempReg = cg->allocateConsecutiveRegisterPair(cg->allocateRegister(),
cg->allocateRegister());
generateRRInstruction(cg, TR::InstOpCode::LR, firstChild, tempReg->getHighOrder(),
secondLogicalOpRegister->getHighOrder());
generateRRInstruction(cg, TR::InstOpCode::LR, firstChild, tempReg->getLowOrder(),
secondLogicalOpRegister->getLowOrder());
}
highLogicalOpMR = generateS390MemoryReference(firstLogicalOpChild, cg);
lowLogicalOpMR = generateS390MemoryReference(*highLogicalOpMR, 4, cg);
generateRXInstruction(cg, logicalRX, firstChild, tempReg->getHighOrder(), highLogicalOpMR);
targetLogicalOpReg = tempReg->getLowOrder();
firstChild->setRegister(tempReg);
}
}
targetRegisterPair = (TR::RegisterPair *) firstChild->getRegister();
cg->decReferenceCount(firstLogicalOpChild);
cg->decReferenceCount(secondLogicalOpChild);
}
else
{
targetRegisterPair = (TR::RegisterPair *) cg->evaluate(firstChild);
}
if (secondChild->getOpCode().isLoadConst())
{
// if second child is complicated then control flow region start will be generated later
TR::LabelSymbol * cflowRegionStart = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
cflowRegionStart->setStartInternalControlFlow();
internalControlFlowStarted = true;
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cflowRegionStart);
}
if (isBoolean)
{
targetRegister = cg->allocateRegister();
// Assume the condition is true.
generateLoad32BitConstant(cg, node, 1, targetRegister, true);
trueTarget = isTrue;
falseTarget = isFalse;
}
else
{
trueTarget = node->getBranchDestination()->getNode()->getLabel();
falseTarget = isFalse;
}
if (secondChild->getOpCode().isLoadConst())
{
int32_t h_value = secondChild->getLongIntHigh();
int32_t l_value = secondChild->getLongIntLow();
TR::Register * lowOrder = targetRegisterPair->getLowOrder();
TR::Register * highOrder = targetRegisterPair->getHighOrder();
// GRA
if (node->getNumChildren() == 3)
{
TR::Node * thirdChild = node->getChild(2);
cg->evaluate(thirdChild);
deps = generateRegisterDependencyConditions(cg, thirdChild, 7);
deps->addPostConditionIfNotAlreadyInserted(highOrder, TR::RealRegister::AssignAny);
deps->addPostConditionIfNotAlreadyInserted(lowOrder, TR::RealRegister::AssignAny);
}
else
{
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 9, cg);
// deps->addPostCondition(targetRegisterPair, TR::RealRegister::EvenOddPair);
// deps->addPostCondition(highOrder, TR::RealRegister::LegalEvenOfPair);
// deps->addPostCondition(lowOrder, TR::RealRegister::LegalOddOfPair);
// Don't need to make these into a pair. They are treated independently
deps->addPostCondition(highOrder, TR::RealRegister::AssignAny);
deps->addPostCondition(lowOrder, TR::RealRegister::AssignAny);
}
// HIGH ORDER
if (isUnsignedCmp)
{
generateS390ImmOp(cg, TR::InstOpCode::CL, node, highOrder, NULL, h_value, deps);
}
else
{
generateS390ImmOp(cg, TR::InstOpCode::C, node, highOrder, highOrder, h_value, deps);
}
// See if condition is FALSE
if (condCmpHighFalse != TR::InstOpCode::COND_NOP)
{
generateS390BranchInstruction(cg, brOpCode, condCmpHighFalse, node, falseTarget);
}
// See if we can assert the condition as TRUE
if (condCmpHighTrue != TR::InstOpCode::COND_NOP)
{
generateS390BranchInstruction(cg, brOpCode, condCmpHighTrue, node, trueTarget);
}
if (splitLogicalOp)
{
// Insert the low order op
if (lowLogicalOpMR)
{
generateRXInstruction(cg, logicalRX, firstChild, targetLogicalOpReg, lowLogicalOpMR);
if (lowLogicalOpMR->getIndexRegister())
{
deps->addPostConditionIfNotAlreadyInserted(lowLogicalOpMR->getIndexRegister(), TR::RealRegister::AssignAny);
}
if (lowLogicalOpMR->getBaseRegister())
{
deps->addPostConditionIfNotAlreadyInserted(lowLogicalOpMR->getBaseRegister(), TR::RealRegister::AssignAny);
}
deps->addPostConditionIfNotAlreadyInserted(targetLogicalOpReg, TR::RealRegister::AssignAny);
}
else
{
generateRRInstruction(cg, logicalRR, firstChild, targetLogicalOpReg, sourceLogicalOpReg);
deps->addPostConditionIfNotAlreadyInserted(sourceLogicalOpReg, TR::RealRegister::AssignAny);
deps->addPostConditionIfNotAlreadyInserted(targetLogicalOpReg, TR::RealRegister::AssignAny);
}
}
else
{
generateS390ImmOp(cg, TR::InstOpCode::CL, node, lowOrder, lowOrder, l_value, deps);
}
// Perform required branch on compare of low values
if (condCmpLowTrue != 0)
{
generateS390BranchInstruction(cg, brOpCode, condCmpLowTrue, node, trueTarget);
}
if (node->getNumChildren() == 3)
{
TR::Node * thirdChild = node->getChild(2);
cg->decReferenceCount(thirdChild);
}
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
}
else
{
TR_S390CompareAnalyser temp(cg);
deps = temp.longOrderedCompareAndBranchAnalyser(node, brOpCode, condCmpLowTrue, condCmpHighTrue, condCmpHighFalse, trueTarget, falseTarget, internalControlFlowStarted);
}
if (!isBoolean)
{
// FALSE, set up deps here if it's the last label
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, isFalse, deps);
if (internalControlFlowStarted)
isFalse->setEndInternalControlFlow();
}
else if (isBoolean)
{
// FALSE
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, isFalse);
if (!internalControlFlowStarted)
isFalse->setStartInternalControlFlow();
generateLoad32BitConstant(cg, node, 0, targetRegister, true);
// Force early assignment of bool value to avoid spills in control flow.
// We don't need an equivalent dep on the gra deps as it is by defn not generated
// when we do a bool if.
deps->addPostConditionIfNotAlreadyInserted(targetRegister, TR::RealRegister::AssignAny);
// TRUE, set up deps here
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, isTrue,deps);
isTrue->setEndInternalControlFlow();
}
return node->setRegister(targetRegister);
}
static TR::Register *
generateS390lcmpEvaluator64(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic brOp, TR::InstOpCode::S390BranchCondition brCond, bool isBoolean)
{
TR_ASSERT( TR::Compiler->target.is64Bit() || cg->use64BitRegsOn32Bit(),"lcmpEvaluator64() is for 64bit code-gen only!");
TR::RegisterDependencyConditions * deps = NULL;
TR::LabelSymbol * isTrue = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
isTrue->setEndInternalControlFlow();
bool isUnsigned = node->getOpCode().isUnsignedCompare();
TR::Instruction *instr;
TR::Register * targetRegister = NULL;
TR::Node * firstChild = node->getFirstChild();
TR_ASSERT(isBoolean, "Coparison node %p is not boolean\n",node);
if (cg->use64BitRegsOn32Bit())
targetRegister = cg->allocate64bitRegister();
else
targetRegister = cg->allocateRegister();
// Assume the condition is true.
genLoadLongConstant(cg, node, 1, targetRegister);
TR::Node * secondChild = node->getSecondChild();
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
int64_t long_value = secondChild->getLongInt();
TR::Register * cmpRegister = cg->evaluate(firstChild);
generateS390ImmOp(cg, isUnsigned ? TR::InstOpCode::CLG : TR::InstOpCode::CG, node, cmpRegister, cmpRegister, long_value);
instr = generateS390BranchInstruction(cg, brOp, brCond, node, isTrue);
}
else
{
// We should use the Binary analyzer here
TR::Node * firstChild = node->getFirstChild();
TR::Register * cmpRegister = cg->evaluate(firstChild);
TR::Register * srcReg = cg->evaluate(secondChild);
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 3, cg);
deps->addPostConditionIfNotAlreadyInserted(cmpRegister,TR::RealRegister::AssignAny);
deps->addPostConditionIfNotAlreadyInserted(srcReg,TR::RealRegister::AssignAny);
instr = generateS390CompareAndBranchInstruction(cg, isUnsigned ? TR::InstOpCode::CLGR : TR::InstOpCode::CGR, node, cmpRegister, srcReg, brCond, isTrue, false, false);
}
instr->setStartInternalControlFlow();
deps->addPostConditionIfNotAlreadyInserted(targetRegister,TR::RealRegister::AssignAny);
// FALSE
genLoadLongConstant(cg, node, 0, targetRegister);
// TRUE
instr = generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, isTrue,deps);
isTrue->setEndInternalControlFlow();
node->setRegister(targetRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return targetRegister;
}
/**
* Generate code to perform a comparison that returns 1 , -1, or 0
* Handles TR::fcmpl, TR::fcmpg, TR::dcmpl, and TR::dcmpg
*/
TR::Register *
OMR::Z::TreeEvaluator::fcmplEvaluator(TR::Node * node, TR::CodeGenerator * cg)
{
PRINT_ME("fcmpl", node, cg);
TR::InstOpCode::Mnemonic branchOp;
TR::InstOpCode::S390BranchCondition brCond ;
// Create a label
TR::LabelSymbol * doneCmp = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
// Create a register
TR::Register * targetRegister = cg->allocateRegister();
// Generate compare code, find out if ops were reversed
brCond = generateS390CompareOps(node, cg, TR::InstOpCode::COND_BH, TR::InstOpCode::COND_BL);
branchOp = TR::InstOpCode::BRC;
// Assume A == B, set targetRegister value to 0
// TODO: Can we allow setting the condition code here by moving the load before the compare?
generateLoad32BitConstant(cg, node, 0, targetRegister, false);
// done if A==B
TR::RegisterDependencyConditions *deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
deps->addPostCondition(targetRegister,TR::RealRegister::AssignAny);
TR::Instruction *cursor = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BE, node, doneCmp);
cursor->setStartInternalControlFlow();
// Found A != B, assume A > B, set targetRegister value to 1
generateLoad32BitConstant(cg, node, 1, targetRegister, false);
//done if A>B
generateS390BranchInstruction(cg, branchOp, brCond, node, doneCmp);
//found either A<B or either of A and B is NaN
//For TR::fcmpg instruction, done if either of A and B is NaN
if (node->getOpCodeValue() == TR::fcmpg || node->getOpCodeValue() == TR::dcmpg)
{
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_MASK1, node, doneCmp);
}
//Got here? means either A<B or (TR::fcmpl instruction and (A==NaN || B==NaN))
//set targetRegister value to -1
generateLoad32BitConstant(cg, node, -1, targetRegister, true);
// DONE
doneCmp->setEndInternalControlFlow();
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, doneCmp, deps);
node->setRegister(targetRegister);
return targetRegister;
}
inline TR::InstOpCode::S390BranchCondition
generateS390Compare(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic branchOp, TR::InstOpCode::S390BranchCondition fBranchOpCond, TR::InstOpCode::S390BranchCondition rBranchOpCond)
{
// Generate compare code, find out if ops were reversed
TR::InstOpCode::S390BranchCondition branchOpCond = generateS390CompareOps(node, cg, fBranchOpCond, rBranchOpCond);
return branchOpCond;
}
/**
* 32bit version lcmpEvaluator: long compare (1 if child1 > child2, 0 if child1 == child2,
* -1 if child1 < child2 or unordered)
*/
TR::Register *
lcmpHelper(TR::Node * node, TR::CodeGenerator * cg)
{
TR_ASSERT( TR::Compiler->target.is32Bit(), "this is for 32bit code-gen only!");
// There is probably a better way to implement this. Should re-visit if we get the chance.
// As things stand now, we will to LCR R1,R1 when R1=0 which is useless... But still probably
// cheaper than an extra branch.
TR::LabelSymbol * labelGT = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol * labelLT = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::Register * targetRegister = cg->allocateRegister();
TR::Node * firstChild = node->getFirstChild();
TR::Node * secondChild = node->getSecondChild();
TR::RegisterPair * src1RegPair = (TR::RegisterPair *) cg->evaluate(firstChild);
TR::RegisterPair * src2RegPair = NULL;
TR::Instruction * cursor = NULL;
TR::Instruction * cursor2 = NULL;
TR::RegisterDependencyConditions * dependencies = NULL;
// Do high Order first
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
// We only need deps for scr1reg in this case
dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 4, cg);
// dependencies->addPostCondition(src1RegPair, TR::RealRegister::EvenOddPair);
// Forcing these registers to be pairs is too strict because we treat them independently anyways
dependencies->addPostCondition(src1RegPair->getHighOrder(), TR::RealRegister::AssignAny);
dependencies->addPostCondition(src1RegPair->getLowOrder(), TR::RealRegister::AssignAny);
}
else
{
// Get src2RegPair if it isn't a const
src2RegPair = (TR::RegisterPair *) cg->evaluate(secondChild);
// We need deps for both scr regs in this case
dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 7, cg);
// Forcing these registers to be pairs is too strict because we treat them independently anyways
// dependencies->addPostCondition(src1RegPair, TR::RealRegister::EvenOddPair);
dependencies->addPostCondition(src1RegPair->getHighOrder(), TR::RealRegister::AssignAny);
dependencies->addPostCondition(src1RegPair->getLowOrder(), TR::RealRegister::AssignAny);
// Fix the case when second child register == first register to avoid duplicates.
// dependencies->addPostConditionIfNotAlreadyInserted(src2RegPair, TR::RealRegister::EvenOddPair);
dependencies->addPostConditionIfNotAlreadyInserted(src2RegPair->getHighOrder(), TR::RealRegister::AssignAny);
dependencies->addPostConditionIfNotAlreadyInserted(src2RegPair->getLowOrder(), TR::RealRegister::AssignAny);
}
dependencies->addPostCondition(targetRegister, TR::RealRegister::AssignAny);
if (secondChild->getOpCode().isLoadConst() && secondChild->getLongInt()==0)
{
TR::Register * tempRegister = cg->allocateRegister();
generateRRInstruction(cg, TR::InstOpCode::XR, node, tempRegister, tempRegister);
generateRRInstruction(cg, TR::InstOpCode::XR, node, targetRegister, targetRegister);
generateRRInstruction(cg, TR::InstOpCode::SLR, node, tempRegister, src1RegPair->getLowOrder());
generateRRInstruction(cg, TR::InstOpCode::SLBR, node, targetRegister, src1RegPair->getHighOrder());
TR::Register * tempHORegister = src1RegPair->getHighOrder();
TR_ClobberEvalData data;
bool clobberHighWord = cg->canClobberNodesRegister(firstChild, 1, &data) && data.canClobberHighWord();
if (!clobberHighWord)
{
tempHORegister = cg->allocateRegister();
generateRRInstruction(cg, TR::InstOpCode::LR, node, tempHORegister, src1RegPair->getHighOrder());
}
generateRSInstruction(cg, TR::InstOpCode::SRA, node, tempHORegister, tempHORegister, 31);
generateRSInstruction(cg, TR::InstOpCode::SRL, node, targetRegister, targetRegister, 31);
generateRRInstruction(cg, TR::InstOpCode::OR, node, targetRegister, tempHORegister);
cg->stopUsingRegister(tempRegister);
if (!clobberHighWord)
cg->stopUsingRegister(tempHORegister);
}
else
{
// Assume LT
generateRIInstruction(cg, TR::InstOpCode::LHI, node, targetRegister, -1);
// Do high Order first
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
// Set the CC using a comp.
generateS390ImmOp(cg, TR::InstOpCode::C, node, src1RegPair->getHighOrder(), src1RegPair->getHighOrder(),
secondChild->getLongIntHigh());
}
else
{
// Set the CC using a comp.
generateRRInstruction(cg, TR::InstOpCode::CR, node, src1RegPair->getHighOrder(), src2RegPair->getHighOrder());
}
// If LT we are done
cursor = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BL, node, labelLT);
// If GT, we invert the result register
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BH, node, labelGT);
// High order words were equal
// Do Low Order
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
// Set the CC using a comp.
// We cannot load this value easily with ops, we must use the lit pool
generateS390ImmOp(cg, TR::InstOpCode::C, node, src1RegPair->getLowOrder(), src1RegPair->getLowOrder(),
secondChild->getLongIntLow());
}
else
{
// Set the CC using a comp.
generateRRInstruction(cg, TR::InstOpCode::CR, node, src1RegPair->getLowOrder(), src2RegPair->getLowOrder());
}
// If LT, we are done
cursor2 = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BL, node, labelLT);
if(cursor)
cursor->setStartInternalControlFlow();
else
cursor2->setStartInternalControlFlow();
// If GT, invert the result
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BH, node, labelGT);
// The two longs are equal
generateRIInstruction(cg, TR::InstOpCode::LHI, node, targetRegister, 0);
// We can go through this path if GT, or if EQ.
// We use LCR to avoid having to branch over this piece of code.
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, labelGT);
generateRRInstruction(cg, TR::InstOpCode::LCR, node, targetRegister, targetRegister);
// We branch here when LT (no change to assumed -1 result)
labelLT->setEndInternalControlFlow();
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, labelLT, dependencies);
}
node->setRegister(targetRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return targetRegister;
}
/**
* \brief
* Compares 2 numbers are returns the greater of the 2.
* ONLY SUPPORTS imax, imin, lmax, lmin
*
* \detail
* Uses a load and conditional store to select the correct value.
* ONLY SUPPORTS imax, imin, lmax, lmin
*
* \param node
* The node representing a call to max or min.
*
* \param cg
* The code generator used to generate the instructions.
*
* \param isMax
* Boolean representing the type of function, either a max or min call.
*
* \return
* A register containing the return value of the Java call. The return value
* will be the greater or lesser of the 2 children for max and min functions, respectively.
*/
static TR::Register * maxMinHelper(TR::Node *node, TR::CodeGenerator *cg, bool isMax)
{
TR_ASSERT_FATAL(cg->getS390ProcessorInfo()->supportsArch(TR_S390ProcessorInfo::TR_z196),
"cannot evaluate %s on z10 or below", node->getOpCode().getName());
TR::Register *registerA = cg->gprClobberEvaluate(node->getFirstChild());
TR::Register *registerB = cg->evaluate(node->getSecondChild());
// Mask is 4 to pick b when a is Lower for max, 2 to pick b when a is higher for min
const uint8_t mask = isMax ? 0x4 : 0x2;
if (node->getOpCodeValue() == TR::imax || node->getOpCodeValue() == TR::imin)
{
generateRRInstruction(cg, TR::InstOpCode::CR, node, registerA, registerB);
generateRRFInstruction(cg, TR::InstOpCode::LOCR, node, registerA, registerB, mask, true);
}
else if (node->getOpCodeValue() == TR::lmax || node->getOpCodeValue() == TR::lmin)
{
if (TR::Compiler->target.is64Bit() || cg->use64BitRegsOn32Bit())
{
generateRREInstruction(cg, TR::InstOpCode::CGR, node, registerA, registerB);
generateRRFInstruction(cg, TR::InstOpCode::LOCGR, node, registerA, registerB, mask, true);
}
else
{
TR::LabelSymbol * done = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::Instruction* cursor = NULL;
TR::RegisterDependencyConditions * regDeps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 6, cg);
regDeps->addPostCondition(registerA, TR::RealRegister::EvenOddPair);
regDeps->addPostCondition(registerA->getHighOrder(), TR::RealRegister::LegalEvenOfPair);
regDeps->addPostCondition(registerA->getLowOrder(), TR::RealRegister::LegalOddOfPair);
regDeps->addPostCondition(registerB, TR::RealRegister::EvenOddPair);
regDeps->addPostCondition(registerB->getHighOrder(), TR::RealRegister::LegalEvenOfPair);
regDeps->addPostCondition(registerB->getLowOrder(), TR::RealRegister::LegalOddOfPair);
generateRRInstruction(cg, TR::InstOpCode::CR, node, registerA->getHighOrder(), registerB->getHighOrder());
generateRRFInstruction(cg, TR::InstOpCode::LOCR, node, registerA->getHighOrder(), registerB->getHighOrder(), mask, true);
generateRRFInstruction(cg, TR::InstOpCode::LOCR, node, registerA->getLowOrder(), registerB->getLowOrder(), mask, true);
cursor = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BRNE, node, done);
cursor->setStartInternalControlFlow();
generateRRInstruction(cg, TR::InstOpCode::CLR, node, registerA->getLowOrder(), registerB->getLowOrder());
generateRRFInstruction(cg, TR::InstOpCode::LOCR, node, registerA->getHighOrder(), registerB->getHighOrder(), mask, true);
generateRRFInstruction(cg, TR::InstOpCode::LOCR, node, registerA->getLowOrder(), registerB->getLowOrder(), mask, true);
cursor = generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, done, regDeps);
cursor->setEndInternalControlFlow();
}
}
else
{
TR_ASSERT_FATAL(node->getOpCodeValue(), "Opcode %s cannot be evaluated by maxMinHelper\n", node->getOpCode().getName());
}
node->setRegister(registerA);
cg->decReferenceCount(node->getFirstChild());
cg->decReferenceCount(node->getSecondChild());
return registerA;
}
TR::Register *
OMR::Z::TreeEvaluator::maxEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return maxMinHelper(node, cg, true);
}
TR::Register *
OMR::Z::TreeEvaluator::minEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return maxMinHelper(node, cg, false);
}
/**
* 64bit version lcmpEvaluator Helper: long compare (1 if child1 > child2, 0 if child1 == child2,
* -1 if child1 < child2 or unordered)
*/
TR::Register *
lcmpHelper64(TR::Node * node, TR::CodeGenerator * cg)
{
TR_ASSERT( TR::Compiler->target.is64Bit() || cg->use64BitRegsOn32Bit(), "this is for 64bit code-gen only!");
// TODO:There is probably a better way to implement this. Should re-visit if we get the chance.
// As things stand now, we will to LCR R1,R1 when R1=0 which is useless... But still probably
// cheaper than an extra branch.
TR::LabelSymbol * labelGT = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol * labelLT = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::Register * targetRegister = cg->allocate64bitRegister();