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BinaryCommutativeAnalyser.cpp
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BinaryCommutativeAnalyser.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include "x/codegen/BinaryCommutativeAnalyser.hpp"
#include <stddef.h>
#include <stdint.h>
#include "codegen/Analyser.hpp"
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "codegen/X86Evaluator.hpp"
#include "compile/Compilation.hpp"
#include "env/IO.hpp"
#include "env/CompilerEnv.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/ILProps.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "infra/Assert.hpp"
#include "x/codegen/X86Instruction.hpp"
#include "x/codegen/X86Ops.hpp"
static void
zeroExtendTo32BitRegister(TR::Node *node,
TR::Register *reg,
int32_t sourceSize,
TR::CodeGenerator *cg)
{
TR_X86OpCodes op;
switch (sourceSize)
{
case 1:
op = MOVZXReg4Reg1;
break;
case 2:
op = MOVZXReg4Reg2;
break;
default:
op = BADIA32Op;
break;
}
if (op != BADIA32Op)
generateRegRegInstruction(op, node, reg, reg, cg);
}
/*
* \brief
* this API is for check nodes(like OverflowCHK) with certain operation where the operands
* are given explicitly by the caller and are not the first and second child of the given root node
*
* \param root
* the check node
* \param firstChild, secondChild
* the operands for the operation
*/
void TR_X86BinaryCommutativeAnalyser::genericAnalyserWithExplicitOperands(TR::Node *root,
TR::Node *firstChild,
TR::Node *secondChild,
TR_X86OpCodes regRegOpCode,
TR_X86OpCodes regMemOpCode,
TR_X86OpCodes copyOpCode,
bool nonClobberingDestination) //false by default
{
TR_ASSERT(root->getOpCodeValue() == TR::OverflowCHK, "unsupported opcode %s for genericAnalyserWithExplicitOperands on node %p\n", _cg->comp()->getDebug()->getName(root->getOpCodeValue()), root);
TR::Register *tempReg = genericAnalyserImpl(root, firstChild, secondChild, regRegOpCode, regMemOpCode, copyOpCode, nonClobberingDestination);
_cg->decReferenceCount(firstChild);
_cg->decReferenceCount(secondChild);
_cg->stopUsingRegister(tempReg);
}
/*
* \brief
* this API is for regular operation nodes where the first child and second child are the operands by default
*/
void TR_X86BinaryCommutativeAnalyser::genericAnalyser(TR::Node *root,
TR_X86OpCodes regRegOpCode,
TR_X86OpCodes regMemOpCode,
TR_X86OpCodes copyOpCode,
bool nonClobberingDestination) //false by default
{
TR::Node *firstChild = NULL;
TR::Node *secondChild = NULL;
TR::Register *targetRegister = NULL;
if (_cg->whichChildToEvaluate(root) == 0)
{
firstChild = root->getFirstChild();
secondChild = root->getSecondChild();
setReversedOperands(false);
}
else
{
setReversedOperands(true);
firstChild = root->getSecondChild();
secondChild = root->getFirstChild();
}
targetRegister = genericAnalyserImpl(root, firstChild, secondChild, regRegOpCode, regMemOpCode, copyOpCode, nonClobberingDestination);
root->setRegister(targetRegister);
_cg->decReferenceCount(firstChild);
_cg->decReferenceCount(secondChild);
}
/*
* users should call the genericAnalyser or genericAnalyserWithExplicitOperands APIs instead of calling this one directly
*/
TR::Register* TR_X86BinaryCommutativeAnalyser::genericAnalyserImpl(TR::Node *root,
TR::Node *firstChild,
TR::Node *secondChild,
TR_X86OpCodes regRegOpCode,
TR_X86OpCodes regMemOpCode,
TR_X86OpCodes copyOpCode,
bool nonClobberingDestination)
{
TR::Register *targetRegister;
TR::Register *firstRegister = firstChild->getRegister();
TR::Register *secondRegister = secondChild->getRegister();
setInputs(firstChild, firstRegister, secondChild, secondRegister, nonClobberingDestination);
if (getEvalChild1())
{
firstRegister = _cg->evaluate(firstChild);
}
if (getEvalChild2())
{
secondRegister = _cg->evaluate(secondChild);
firstRegister = firstChild->getRegister();
}
if (getOpReg1Reg2())
{
generateRegRegInstruction(regRegOpCode, root, firstRegister, secondRegister, _cg);
targetRegister = firstRegister;
}
else if (getOpReg2Reg1())
{
generateRegRegInstruction(regRegOpCode, root, secondRegister, firstRegister, _cg);
targetRegister = secondRegister;
notReversedOperands();
}
else if (getCopyReg1())
{
TR::Register *tempReg;
if (TR_X86OpCode::fprOp(copyOpCode) == 0)
{
tempReg = _cg->allocateRegister();
}
else if (TR_X86OpCode::singleFPOp(copyOpCode))
{
tempReg = _cg->allocateSinglePrecisionRegister(TR_X87);
}
else
{
tempReg = _cg->allocateRegister(TR_X87);
}
targetRegister = tempReg;
generateRegRegInstruction(copyOpCode, root, tempReg, firstRegister, _cg);
generateRegRegInstruction(regRegOpCode, root, tempReg, secondRegister, _cg);
}
else if (getCopyReg2())
{
TR::Register *tempReg;
if (TR_X86OpCode::fprOp(copyOpCode) == 0)
{
tempReg = _cg->allocateRegister();
}
else if (TR_X86OpCode::singleFPOp(copyOpCode))
{
tempReg = _cg->allocateSinglePrecisionRegister(TR_X87);
}
else
{
tempReg = _cg->allocateRegister(TR_X87);
}
targetRegister = tempReg;
generateRegRegInstruction(copyOpCode, root, tempReg, secondRegister, _cg);
generateRegRegInstruction(regRegOpCode, root, tempReg, firstRegister, _cg);
notReversedOperands();
}
else if (getOpReg1Mem2())
{
TR::MemoryReference *tempMR = generateX86MemoryReference(secondChild, _cg);
if (regMemOpCode == TEST4MemReg || regMemOpCode == TEST8MemReg)
{
generateMemRegInstruction(regMemOpCode, root, tempMR, firstRegister, _cg);
}
else
{
generateRegMemInstruction(regMemOpCode, root, firstRegister, tempMR, _cg);
}
targetRegister = firstRegister;
tempMR->decNodeReferenceCounts(_cg);
}
else
{
TR::MemoryReference *tempMR = generateX86MemoryReference(firstChild, _cg);
if (regMemOpCode == TEST4MemReg || regMemOpCode == TEST8MemReg)
{
generateMemRegInstruction(regMemOpCode, root, tempMR, secondRegister, _cg);
}
else
{
generateRegMemInstruction(regMemOpCode, root, secondRegister, tempMR, _cg);
}
targetRegister = secondRegister;
tempMR->decNodeReferenceCounts(_cg);
notReversedOperands();
}
return targetRegister;
}
void TR_X86BinaryCommutativeAnalyser::genericLongAnalyser(TR::Node *root,
TR_X86OpCodes lowRegRegOpCode,
TR_X86OpCodes highRegRegOpCode,
TR_X86OpCodes lowRegMemOpCode,
TR_X86OpCodes lowRegMemOpCode2Byte,
TR_X86OpCodes lowRegMemOpCode1Byte,
TR_X86OpCodes highRegMemOpCode,
TR_X86OpCodes copyOpCode)
{
TR::Node *firstChild;
TR::Node *secondChild;
if (_cg->whichChildToEvaluate(root) == 0)
{
firstChild = root->getFirstChild();
secondChild = root->getSecondChild();
setReversedOperands(false);
}
else
{
setReversedOperands(true);
firstChild = root->getSecondChild();
secondChild = root->getFirstChild();
}
TR::Register *firstRegister = firstChild->getRegister();
TR::Register *secondRegister = secondChild->getRegister();
bool firstHighZero = false;
bool secondHighZero = false;
bool useFirstHighOrder = false;
bool useSecondHighOrder = false;
TR::Node *bypassedFirstUnsignedConversionChild = NULL;
TR::Node *bypassedSecondUnsignedConversionChild = NULL;
// Can generate better code for long operations when one or more children have their
// high order word as a zero. Examples are xu2l conversion operators, right unsigned shifts by 32 or more bits
// and just things that value propagation has found are in the range of an unsigned int.
// we can avoid the evaluation when we don't need the result of such nodes for another parent.
//
if (firstChild->isHighWordZero())
{
firstHighZero = true;
TR::ILOpCodes firstOp = firstChild->getOpCodeValue();
if (firstChild->getReferenceCount() == 1 && firstRegister == 0)
{
// We cannot use a non-long grandchild that has not been zero-extended.
if ((firstOp == TR::lushr &&
firstChild->getSecondChild()->getOpCodeValue() == TR::iconst &&
(firstChild->getSecondChild()->getInt() & TR::TreeEvaluator::shiftMask(true)) == 32))
{
bypassedFirstUnsignedConversionChild = firstChild;
//only decrease RC for bypassed node and the constant node because we bypass the lushr node but keep the reference to its first child
_cg->decReferenceCount(bypassedFirstUnsignedConversionChild);
_cg->decReferenceCount(firstChild->getSecondChild());
firstChild = firstChild->getFirstChild();
firstRegister = firstChild->getRegister();
if (firstOp == TR::lushr)
{
useFirstHighOrder = true;
}
// adjust low opcode based on size of the child we're loading from mem (66327)
switch (firstChild->getSize())
{
case 1 :
lowRegMemOpCode = lowRegMemOpCode1Byte;
break;
case 2 :
lowRegMemOpCode = lowRegMemOpCode2Byte;
break;
}
}
}
}
if (secondChild->isHighWordZero())
{
secondHighZero = true;
TR::ILOpCodes secondOp = secondChild->getOpCodeValue();
if (secondChild->getReferenceCount() == 1 && secondRegister == 0)
{
// We cannot use a non-long grandchild that has not been zero-extended.
if ((secondOp == TR::lushr &&
secondChild->getSecondChild()->getOpCodeValue() == TR::iconst &&
(secondChild->getSecondChild()->getInt() & TR::TreeEvaluator::shiftMask(true)) == 32))
{
bypassedSecondUnsignedConversionChild = secondChild;
//only decrease RC for bypassed node and the constant node because we bypass the lushr node but keep the reference to its first child
_cg->decReferenceCount(bypassedSecondUnsignedConversionChild);
_cg->decReferenceCount(secondChild->getSecondChild());
secondChild = secondChild->getFirstChild();
secondRegister = secondChild->getRegister();
if (secondOp == TR::lushr)
{
useSecondHighOrder = true;
}
// adjust low opcode based on size of the child we're loading from mem
switch (secondChild->getSize())
{
case 1 :
lowRegMemOpCode = lowRegMemOpCode1Byte;
break;
case 2 :
lowRegMemOpCode = lowRegMemOpCode2Byte;
break;
}
}
}
}
// Bypassing a conversion child makes it behave a bit like a
// pseudo-PassThrough node, and so we have to get very conservative about
// when we clobber (at least until x86 codegen gets smarter about
// pseudo-PassThroughs generally).
//
const bool dontClobberAnything = bypassedFirstUnsignedConversionChild || bypassedSecondUnsignedConversionChild;
setInputs(firstChild, firstRegister, secondChild, secondRegister, false, dontClobberAnything);
if (getEvalChild1())
{
firstRegister = _cg->evaluate(firstChild);
if (bypassedFirstUnsignedConversionChild)
zeroExtendTo32BitRegister(bypassedFirstUnsignedConversionChild, firstRegister, firstChild->getSize(), _cg);
}
if (getEvalChild2())
{
secondRegister = _cg->evaluate(secondChild);
if (bypassedSecondUnsignedConversionChild)
zeroExtendTo32BitRegister(bypassedSecondUnsignedConversionChild, secondRegister, secondChild->getSize(), _cg);
}
if (firstHighZero && firstRegister && firstRegister->getRegisterPair())
{
if (!useFirstHighOrder)
{
firstRegister = firstRegister->getLowOrder();
}
else
{
firstRegister = firstRegister->getHighOrder();
}
}
if (secondHighZero && secondRegister && secondRegister->getRegisterPair())
{
if (!useSecondHighOrder)
{
secondRegister = secondRegister->getLowOrder();
}
else
{
secondRegister = secondRegister->getHighOrder();
}
}
TR::Register *twoLow;
TR::Register *twoHigh;
TR::Register *oneLow;
TR::Register *oneHigh;
if (getOpReg1Reg2())
{
if (!firstHighZero)
{
oneLow = firstRegister->getLowOrder();
oneHigh = firstRegister->getHighOrder();
}
else
{
oneLow = firstRegister;
oneHigh = 0;
}
if (!secondHighZero)
{
twoLow = secondRegister->getLowOrder();
twoHigh = secondRegister->getHighOrder();
}
else
{
twoLow = secondRegister;
twoHigh = 0;
}
generateRegRegInstruction(lowRegRegOpCode, root, oneLow, twoLow, _cg);
if (firstHighZero)
{
if (secondHighZero)
{
oneHigh = _cg->allocateRegister();
generateRegRegInstruction(XOR4RegReg, root, oneHigh, oneHigh, _cg);
}
else
{
if (root->getOpCodeValue() == TR::land)
{
oneHigh = _cg->allocateRegister();
generateRegRegInstruction(XOR4RegReg, root, oneHigh, oneHigh, _cg);
}
else
{
if (secondChild->getReferenceCount() == 1)
{
oneHigh = twoHigh;
}
else
{
oneHigh = _cg->allocateRegister();
generateRegRegInstruction(copyOpCode, root, oneHigh, twoHigh, _cg);
}
}
}
}
else if (secondHighZero)
{
if (root->getOpCodeValue() == TR::land)
{
generateRegRegInstruction(XOR4RegReg, root, oneHigh, oneHigh, _cg);
}
}
else
{
generateRegRegInstruction(highRegRegOpCode, root, oneHigh, twoHigh, _cg);
}
root->setRegister(_cg->allocateRegisterPair(oneLow, oneHigh));
}
else if (getOpReg2Reg1())
{
if (!firstHighZero)
{
oneLow = firstRegister->getLowOrder();
oneHigh = firstRegister->getHighOrder();
}
else
{
oneLow = firstRegister;
oneHigh = 0;
}
if (!secondHighZero)
{
twoLow = secondRegister->getLowOrder();
twoHigh = secondRegister->getHighOrder();
}
else
{
twoLow = secondRegister;
twoHigh = 0;
}
generateRegRegInstruction(lowRegRegOpCode, root, twoLow, oneLow, _cg);
if (firstHighZero)
{
if (secondHighZero)
{
twoHigh = _cg->allocateRegister();
generateRegRegInstruction(XOR4RegReg, root, twoHigh, twoHigh, _cg);
}
else
{
if (root->getOpCodeValue() == TR::land)
{
generateRegRegInstruction(XOR4RegReg, root, twoHigh, twoHigh, _cg);
}
}
}
else if (secondHighZero)
{
twoHigh = _cg->allocateRegister();
if (root->getOpCodeValue() == TR::land)
{
generateRegRegInstruction(XOR4RegReg, root, twoHigh, twoHigh, _cg);
}
else
{
generateRegRegInstruction(copyOpCode, root, twoHigh, oneHigh, _cg);
}
}
else
{
generateRegRegInstruction(highRegRegOpCode, root, twoHigh, oneHigh, _cg);
}
root->setRegister(_cg->allocateRegisterPair(twoLow, twoHigh));
notReversedOperands();
}
else if (getCopyRegs())
{
TR::Register *copyReg;
TR::Register *copyLow;
TR::Register *copyHigh;
TR::Register *sourceReg;
TR::Register *sourceLow;
TR::Register *sourceHigh = NULL;
bool copyHighZero = false;
bool sourceHighZero = false;
if (getCopyReg1())
{
copyReg = firstRegister;
sourceReg = secondRegister;
copyHighZero = firstHighZero;
sourceHighZero = secondHighZero;
}
else
{
copyReg = secondRegister;
sourceReg = firstRegister;
copyHighZero = secondHighZero;
sourceHighZero = firstHighZero;
notReversedOperands();
}
copyLow = _cg->allocateRegister();
TR::Register *temp;
if (copyHighZero)
{
temp = copyReg;
}
else
{
temp = copyReg->getLowOrder();
}
generateRegRegInstruction(copyOpCode, root, copyLow, temp, _cg);
if (sourceHighZero)
{
sourceLow = sourceReg;
}
else
{
sourceLow = sourceReg->getLowOrder();
sourceHigh = sourceReg->getHighOrder();
}
generateRegRegInstruction(lowRegRegOpCode, root, copyLow, sourceLow, _cg);
copyHigh = _cg->allocateRegister();
if (copyHighZero)
{
if (sourceHighZero)
{
generateRegRegInstruction(XOR4RegReg, root, copyHigh, copyHigh, _cg);
}
else
{
if (root->getOpCodeValue() == TR::land)
{
generateRegRegInstruction(XOR4RegReg, root, copyHigh, copyHigh, _cg);
}
else
{
generateRegRegInstruction(copyOpCode, root, copyHigh, sourceHigh, _cg);
}
}
}
else if (sourceHighZero)
{
if (root->getOpCodeValue() == TR::land)
{
generateRegRegInstruction(XOR4RegReg, root, copyHigh, copyHigh, _cg);
}
else
{
generateRegRegInstruction(copyOpCode, root, copyHigh, copyReg->getHighOrder(), _cg);
}
}
else
{
generateRegRegInstruction(copyOpCode, root, copyHigh, copyReg->getHighOrder(), _cg);
generateRegRegInstruction(highRegRegOpCode, root, copyHigh, sourceHigh, _cg);
}
root->setRegister(_cg->allocateRegisterPair(copyLow, copyHigh));
}
else
{
TR::MemoryReference *lowMR = NULL;
TR::MemoryReference *highMR = NULL;
TR::Register *targetReg = NULL;
TR::Register *targetLow = NULL;
TR::Register *targetHigh = NULL;
bool targetHighZero = false;
bool memHighZero = false;
bool useMemHighOrder = false;
if (getOpReg1Mem2())
{
lowMR = generateX86MemoryReference(secondChild, _cg);
targetReg = firstRegister;
targetHighZero = firstHighZero;
memHighZero = secondHighZero;
useMemHighOrder = useSecondHighOrder;
}
else
{
lowMR = generateX86MemoryReference(firstChild, _cg);
targetReg = secondRegister;
targetHighZero = secondHighZero;
memHighZero = firstHighZero;
useMemHighOrder = useFirstHighOrder;
notReversedOperands();
}
if (targetHighZero)
{
targetLow = targetReg;
}
else
{
targetLow = targetReg->getLowOrder();
targetHigh = targetReg->getHighOrder();
}
if (useMemHighOrder)
{
lowMR->getSymbolReference().addToOffset(4);
}
generateRegMemInstruction(lowRegMemOpCode, root, targetLow, lowMR, _cg);
if (memHighZero)
{
if (targetHighZero)
targetHigh = _cg->allocateRegister();
if (root->getOpCodeValue() == TR::land || targetHighZero)
{
generateRegRegInstruction(XOR4RegReg, root, targetHigh, targetHigh, _cg);
}
}
else if (targetHighZero)
{
targetHigh = _cg->allocateRegister();
if (root->getOpCodeValue() == TR::land)
{
generateRegRegInstruction(XOR4RegReg, root, targetHigh, targetHigh, _cg);
}
else
{
highMR = generateX86MemoryReference(*lowMR, 4, _cg);
generateRegMemInstruction(L4RegMem, root, targetHigh, highMR, _cg);
}
}
else
{
highMR = generateX86MemoryReference(*lowMR, 4, _cg);
generateRegMemInstruction(highRegMemOpCode, root, targetHigh, highMR, _cg);
}
root->setRegister(_cg->allocateRegisterPair(targetLow, targetHigh));
lowMR->decNodeReferenceCounts(_cg);
}
_cg->decReferenceCount(firstChild);
_cg->decReferenceCount(secondChild);
}
/*
* \brief
* this API is intended for regular add operation nodes where the first child and second child are the operands by default
*/
void TR_X86BinaryCommutativeAnalyser::integerAddAnalyser(TR::Node *root,
TR_X86OpCodes regRegOpCode,
TR_X86OpCodes regMemOpCode,
bool needsEflags, // false by default
TR::Node *carry )// 0 by default
{
TR::Node *firstChild = NULL;
TR::Node *secondChild = NULL;
TR::Register *targetRegister;
if (_cg->whichChildToEvaluate(root) == 0)
{
firstChild = root->getFirstChild();
secondChild = root->getSecondChild();
setReversedOperands(false);
}
else
{
firstChild = root->getSecondChild();
secondChild = root->getFirstChild();
setReversedOperands(true);
}
targetRegister = integerAddAnalyserImpl(root, firstChild, secondChild, regRegOpCode, regMemOpCode, needsEflags, carry);
root->setRegister(targetRegister);
_cg->decReferenceCount(firstChild);
_cg->decReferenceCount(secondChild);
}
/*
* \brief
* this API is for check nodes(like OverflowCHK) with an add operation where the operands
* are given explicitly by the caller and are not the first and second child of the given root node
*
* \param root
* the check node
* \param firstChild, secondChild
* the operands for the add operation
*/
void TR_X86BinaryCommutativeAnalyser::integerAddAnalyserWithExplicitOperands(TR::Node *root,
TR::Node *firstChild,
TR::Node *secondChild,
TR_X86OpCodes regRegOpCode,
TR_X86OpCodes regMemOpCode,
bool needsEflags, // false by default
TR::Node *carry)// 0 by default
{
TR_ASSERT(root->getOpCodeValue() == TR::OverflowCHK, "unsupported opcode %s for integerAddAnalyserWithGivenOperands on node %p\n", _cg->comp()->getDebug()->getName(root->getOpCodeValue()), root);
TR::Register *tempReg = integerAddAnalyserImpl(root, firstChild, secondChild, regRegOpCode, regMemOpCode, needsEflags, carry);
_cg->decReferenceCount(firstChild);
_cg->decReferenceCount(secondChild);
_cg->stopUsingRegister(tempReg);
}
/*
* users should call the integerAddAnalyser or integerAddAnalyserWithGivenOperands APIs instead of calling this one directly
*/
TR::Register *TR_X86BinaryCommutativeAnalyser::integerAddAnalyserImpl(TR::Node *root,
TR::Node *firstChild,
TR::Node *secondChild,
TR_X86OpCodes regRegOpCode,
TR_X86OpCodes regMemOpCode,
bool needsEflags,
TR::Node *carry)
{
TR::Register *targetRegister;
TR::Compilation* comp = _cg->comp();
TR::Register *firstRegister = firstChild->getRegister();
TR::Register *secondRegister = secondChild->getRegister();
setInputs(firstChild, firstRegister, secondChild, secondRegister);
// Must prevent creating registers that are marked as containing
// both collected reference and internal pointers at the same time
//
if (root->isInternalPointer())
{
// If a register is marked as containing a collected reference, adjust
// the _inputs fields as to mark it unclobberable
//
if (firstRegister &&
((!firstRegister->containsInternalPointer()) || (firstRegister->getPinningArrayPointer() != root->getPinningArrayPointer())))
resetClob1();
if (secondRegister &&
((!secondRegister->containsInternalPointer()) || (secondRegister->getPinningArrayPointer() != root->getPinningArrayPointer())))
resetClob2();
}
if (comp->generateArraylets() && root->getOpCodeValue() == TR::aiadd)
{
// result of this add is probably an internal pointer into the arraylet spine
// so make sure that, if either child is marked as collectible, we won't
// reuse its register for this internal pointer
if (firstRegister && firstRegister->containsCollectedReference())
resetClob1();
if (secondRegister && secondRegister->containsCollectedReference())
resetClob2();
}
if (getEvalChild1())
{
firstRegister = _cg->evaluate(firstChild);
}
if (getEvalChild2())
{
secondRegister = _cg->evaluate(secondChild);
firstRegister = firstChild->getRegister();
}
// comp()->useCompressedPointers
// ladd
// iu2l
// the firstChild is not commoned
//
TR::TreeEvaluator::genNullTestSequence(root, firstRegister, firstRegister, _cg);
// maybe a register that did not exist before has just been created,
// and this new register contains a collected reference
// arraylets: aiadd is technically internal pointer into spine object, but isn't marked as internal pointer
if (root->isInternalPointer() || (comp->generateArraylets() && root->getOpCodeValue() == TR::aiadd))
{
// check whether a newly created register contains collected reference
if ((getEvalChild1() && ((!firstRegister->containsInternalPointer()) || (firstRegister->getPinningArrayPointer() != root->getPinningArrayPointer()))) ||
(getEvalChild2() && ((!secondRegister->containsInternalPointer()) || (secondRegister->getPinningArrayPointer() != root->getPinningArrayPointer()))))
{
// need to call again setInputs to mark the fact that
// the newly created register cannot be clobbered
setInputs(firstChild, firstRegister, secondChild, secondRegister, false, true);
// if we need to copy registers, make sure we have both registers available
if (getCopyRegs())
{
if (!firstRegister)
firstRegister = _cg->evaluate(firstChild);
if (!secondRegister)
secondRegister = _cg->evaluate(secondChild);
}
}
}
if (carry != 0)
TR_X86ComputeCC::setCarryBorrow(carry, false, _cg);
if (getOpReg1Reg2())
{
generateRegRegInstruction(regRegOpCode, root, firstRegister, secondRegister, _cg);
targetRegister = firstRegister;
}
else if (getOpReg2Reg1())
{
generateRegRegInstruction(regRegOpCode, root, secondRegister, firstRegister, _cg);
targetRegister = secondRegister;
notReversedOperands();
}
else if (getCopyRegs())
{
TR::Register *tempReg;
if (firstRegister->containsCollectedReference() ||
secondRegister->containsCollectedReference() ||
firstRegister->containsInternalPointer() ||
secondRegister->containsInternalPointer())
{
if (root->isInternalPointer())
{
tempReg = _cg->allocateRegister();
if (root->getPinningArrayPointer())
{
tempReg->setContainsInternalPointer();
tempReg->setPinningArrayPointer(root->getPinningArrayPointer());
}
}
else if (comp->generateArraylets() && root->getOpCodeValue() == TR::aiadd)
// arraylets: aiadd is technically internal pointer into spine object, but isn't marked as internal pointer
tempReg = _cg->allocateRegister();
else
tempReg = _cg->allocateCollectedReferenceRegister();
}
else
{
tempReg = _cg->allocateRegister();
}
targetRegister = tempReg;
bool is64Bit = TR_X86OpCode(regRegOpCode).hasLongSource();
// if eflags are required then we cannot use LEA as it doesn't set or use them
if (needsEflags || (carry != 0))
{
generateRegRegInstruction(MOVRegReg(is64Bit), root, tempReg, firstRegister, _cg);
generateRegRegInstruction(regRegOpCode, root, tempReg, secondRegister, _cg);
}
else
{
TR::MemoryReference *tempMR = generateX86MemoryReference(_cg);
tempMR->setBaseRegister(firstRegister);
tempMR->setIndexRegister(secondRegister);
generateRegMemInstruction(LEARegMem(is64Bit), root, tempReg, tempMR, _cg);
}
}
else if (getOpReg1Mem2())
{
TR::MemoryReference *tempMR = generateX86MemoryReference(secondChild, _cg);
generateRegMemInstruction(regMemOpCode, root, firstRegister, tempMR, _cg);
targetRegister = firstRegister;
tempMR->decNodeReferenceCounts(_cg);
}
else
{
TR::MemoryReference *tempMR = generateX86MemoryReference(firstChild, _cg);
generateRegMemInstruction(regMemOpCode, root, secondRegister, tempMR, _cg);
targetRegister = secondRegister;
tempMR->decNodeReferenceCounts(_cg);
notReversedOperands();
}
return targetRegister;
}
// Volatile memory operands are not allowed in long additions
// if we are compiling for an SMP machine, as the carry flag can
// get clobbered by the memory barrier immediately preceding the
// ADC4RegMem instruction.
//
bool TR_X86BinaryCommutativeAnalyser::isVolatileMemoryOperand(TR::Node *node)
{
TR::Compilation *comp = _cg->comp();
TR_ASSERT_FATAL(comp, "isVolatileMemoryOperand should only be called during a compilation!");
if (comp->target().isSMP() && node->getOpCode().isMemoryReference())
{
TR_ASSERT(node->getSymbolReference(), "expecting a symbol reference\n");
TR::Symbol *sym = node->getSymbolReference()->getSymbol();
return (sym && sym->isVolatile());
}
return false;
}
/*
* \brief
* this API is for check nodes(like OverflowCHK) an ladd operation where the operands
* are given explicitly by the caller and are not the first and second child of the given root node
*
* \param root
* the check node
* \param firstChild, secondChild
* the operands for the add operation
*/
void TR_X86BinaryCommutativeAnalyser::longAddAnalyserWithExplicitOperands(TR::Node *root, TR::Node *firstChild, TR::Node *secondChild)
{
TR_ASSERT(root->getOpCodeValue() == TR::OverflowCHK, "unsupported opcode %s for longAddAnalyserWithExplicitOperands on node %p\n", _cg->comp()->getDebug()->getName(root->getOpCodeValue()), root);
TR::Register *tempReg= longAddAnalyserImpl(root, firstChild, secondChild);
_cg->decReferenceCount(firstChild);
_cg->decReferenceCount(secondChild);
_cg->stopUsingRegister(tempReg);
}
/*
* \brief
* this API is intended for regular ladd operation nodes where the first child and second child are the operands by default
*/
void TR_X86BinaryCommutativeAnalyser::longAddAnalyser(TR::Node *root)
{
TR::Node *firstChild = NULL;
TR::Node *secondChild = NULL;
if (_cg->whichChildToEvaluate(root) == 0)
{
firstChild = root->getFirstChild();
secondChild = root->getSecondChild();
setReversedOperands(false);
}
else
{
firstChild = root->getSecondChild();
secondChild = root->getFirstChild();
setReversedOperands(true);
}
TR::Register * targetRegister = longAddAnalyserImpl(root, firstChild, secondChild);
root->setRegister(targetRegister);
_cg->decReferenceCount(firstChild);
_cg->decReferenceCount(secondChild);
}
/*
* users should call the longAddAnalyser or longAddAnalyserWithExplicitOperands APIs instead of calling this one directly
*/
TR::Register* TR_X86BinaryCommutativeAnalyser::longAddAnalyserImpl(TR::Node *root, TR::Node *&firstChild, TR::Node *&secondChild)
{
TR::Register *twoLow = NULL;
TR::Register *twoHigh = NULL;
TR::Register *oneLow = NULL;
TR::Register *oneHigh = NULL;
TR::Register *targetRegister = NULL;
TR_X86OpCodes regRegOpCode = ADD4RegReg;
TR_X86OpCodes regMemOpCode = ADD4RegMem;