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S390Debug.cpp
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S390Debug.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#if defined (_MSC_VER) && (_MSC_VER < 1900)
#define snprintf _snprintf_s
#endif
#include <limits.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "codegen/CodeGenPhase.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/GCRegisterMap.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/Snippet.hpp"
#include "codegen/UnresolvedDataSnippet.hpp"
#include "compile/Compilation.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/IO.hpp"
#include "env/TRMemory.hpp"
#include "env/defines.h"
#include "env/jittypes.h"
#include "il/AutomaticSymbol.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/RegisterMappedSymbol.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "infra/Assert.hpp"
#include "infra/List.hpp"
#include "infra/SimpleRegex.hpp"
#include "ras/Debug.hpp"
#include "z/codegen/S390Instruction.hpp"
#include "z/codegen/S390OutOfLineCodeSection.hpp"
namespace TR { class Block; }
#define OPCODE_SPACING 8
extern const char *BranchConditionToNameMap[];
/** Need to use this since xlc doesn't seem to understand %hx modifier for fprintf */
#define maskHalf(val) (0x0000FFFF & (val))
void
TR_Debug::printPrefix(TR::FILE *pOutFile, TR::Instruction * instr)
{
if (pOutFile == NULL)
{
return;
}
printPrefix(pOutFile, instr, instr->getBinaryEncoding(), instr->getBinaryLength());
if (_comp->cg()->traceBCDCodeGen())
{
#ifdef J9_PROJECT_SPECIFIC
if (instr->getNode() && (instr->getNode()->getOpCode().isBinaryCodedDecimalOp()) &&
(instr->getOpCodeValue() == TR::InstOpCode::CVB || instr->getOpCodeValue() == TR::InstOpCode::CVBG ||
instr->getOpCodeValue() == TR::InstOpCode::CVD || instr->getOpCodeValue() == TR::InstOpCode::CVDG ||
instr->getOpCodeValue() == TR::InstOpCode::OI || instr->getOpCodeValue() == TR::InstOpCode::NI || instr->getOpCodeValue() == TR::InstOpCode::MVI ||
instr->getKind() == TR::Instruction::IsSIL || instr->getKind() == TR::Instruction::IsSI || instr->getKind() == TR::Instruction::IsSIY ||
instr->getKind() == TR::Instruction::IsSS1 || instr->getKind() == TR::Instruction::IsSS2))
{
if (instr->getOpCodeValue() == TR::InstOpCode::CVB || instr->getOpCodeValue() == TR::InstOpCode::CVBG)
{
trfprintf(pOutFile, " , #%d ", instr->getMemoryReference()->getSymbolReference()->getReferenceNumber());
}
else
{
if (instr->getNode() && instr->getNode()->getOpCodeValue() != TR::BBStart && instr->getRegisterOperand(1))
trfprintf(pOutFile, "#%d (%s)", instr->getMemoryReference()->getSymbolReference()->getReferenceNumber(),instr->getRegisterOperand(1)->getRegisterName(_comp));
else
trfprintf(pOutFile, "#%d ", instr->getMemoryReference()->getSymbolReference()->getReferenceNumber());
if (instr->getKind() == TR::Instruction::IsSS1 || instr->getKind() == TR::Instruction::IsSS2)
{
TR::MemoryReference *memRef = (instr->getKind() == TR::Instruction::IsSS1) ?
((TR::S390SS1Instruction *)(instr))->getMemoryReference2() :
((TR::S390SS2Instruction *)(instr))->getMemoryReference2();
if (memRef && memRef->getSymbolReference() && instr->getNode()->getOpCodeValue() != TR::BBStart && instr->getRegisterOperand(0))
trfprintf(pOutFile, ", #%d (%s)", memRef->getSymbolReference()->getReferenceNumber(), instr->getRegisterOperand(0)->getRegisterName(_comp));
else if (memRef && memRef->getSymbolReference())
trfprintf(pOutFile, ", #%d ", memRef->getSymbolReference()->getReferenceNumber());
else
trfprintf(pOutFile, " ");
}
else
{
trfprintf(pOutFile, " ");
}
}
}
else
#endif
{
trfprintf(pOutFile, " ");
}
}
}
void
TR_Debug::printz(TR::FILE *pOutFile, TR::Instruction * instr, const char *title)
{
printz(pOutFile, instr);
}
void
TR_Debug::printz(TR::FILE *pOutFile, TR::Instruction * instr)
{
if (pOutFile == NULL)
{
return;
}
// dump the inst's pre deps
if (instr->getOpCodeValue() != TR::InstOpCode::ASSOCREGS && _comp->cg()->getCodeGeneratorPhase() <= TR::CodeGenPhase::BinaryEncodingPhase)
dumpDependencies(pOutFile, instr, true, false);
switch (instr->getKind())
{
case TR::Instruction::IsLabel:
print(pOutFile, (TR::S390LabelInstruction *) instr);
break;
case TR::Instruction::IsBranch:
print(pOutFile, (TR::S390BranchInstruction *) instr);
break;
case TR::Instruction::IsBranchOnCount:
print(pOutFile, (TR::S390BranchOnCountInstruction *) instr);
break;
case TR::Instruction::IsBranchOnIndex:
print(pOutFile, (TR::S390BranchOnIndexInstruction *) instr);
break;
case TR::Instruction::IsImm:
print(pOutFile, (TR::S390ImmInstruction *) instr);
break;
case TR::Instruction::IsImmSnippet:
print(pOutFile, (TR::S390ImmSnippetInstruction *) instr);
break;
case TR::Instruction::IsImmSym:
print(pOutFile, (TR::S390ImmSymInstruction *) instr);
break;
case TR::Instruction::IsImm2Byte:
print(pOutFile, (TR::S390Imm2Instruction *) instr);
break;
case TR::Instruction::IsReg:
print(pOutFile, (TR::S390RegInstruction *) instr);
break;
case TR::Instruction::IsRR:
print(pOutFile, (TR::S390RRInstruction *) instr);
break;
case TR::Instruction::IsRRE:
{
TR::InstOpCode::Mnemonic opCode = instr->getOpCodeValue();
if (opCode == TR::InstOpCode::TROO || opCode == TR::InstOpCode::TRTO || opCode == TR::InstOpCode::TROT || opCode == TR::InstOpCode::TRTT)
print(pOutFile, (TR::S390TranslateInstruction *) instr);
else
print(pOutFile, (TR::S390RRInstruction *) instr);
break;
}
case TR::Instruction::IsRRD: // RRD is encoded use RRF
case TR::Instruction::IsRRF:
case TR::Instruction::IsRRF2:
case TR::Instruction::IsRRF3:
case TR::Instruction::IsRRF4:
case TR::Instruction::IsRRF5:
print(pOutFile, (TR::S390RRFInstruction *) instr);
break;
case TR::Instruction::IsRRR:
print(pOutFile, (TR::S390RRRInstruction *) instr);
break;
case TR::Instruction::IsRI:
print(pOutFile, (TR::S390RIInstruction *) instr);
break;
case TR::Instruction::IsRIL:
print(pOutFile, (TR::S390RILInstruction *) instr);
break;
case TR::Instruction::IsRS:
print(pOutFile, (TR::S390RSInstruction *) instr);
break;
case TR::Instruction::IsRSL:
print(pOutFile, (TR::S390RSLInstruction *) instr);
break;
case TR::Instruction::IsRSLb:
print(pOutFile, (TR::S390RSLbInstruction *) instr);
break;
case TR::Instruction::IsRSY:
print(pOutFile, (TR::S390RSInstruction *) instr);
break;
case TR::Instruction::IsRX:
print(pOutFile, (TR::S390RXInstruction *) instr);
break;
case TR::Instruction::IsRXE:
print(pOutFile, (TR::S390RXEInstruction *) instr);
break;
case TR::Instruction::IsRXY:
print(pOutFile, (TR::S390RXInstruction *) instr);
break;
case TR::Instruction::IsRXYb:
print(pOutFile, (TR::S390MemInstruction *) instr);
break;
case TR::Instruction::IsRXF:
print(pOutFile, (TR::S390RXFInstruction *) instr);
break;
case TR::Instruction::IsSMI:
print(pOutFile, (TR::S390SMIInstruction *) instr);
break;
case TR::Instruction::IsMII:
print(pOutFile, (TR::S390MIIInstruction *) instr);
break;
case TR::Instruction::IsMem:
print(pOutFile, (TR::S390MemInstruction *) instr);
break;
case TR::Instruction::IsSS1:
print(pOutFile, (TR::S390SS1Instruction *) instr);
break;
case TR::Instruction::IsSS2:
print(pOutFile, (TR::S390SS2Instruction *) instr);
break;
case TR::Instruction::IsSS4:
print(pOutFile, (TR::S390SS4Instruction *) instr);
break;
case TR::Instruction::IsSSF:
print(pOutFile, (TR::S390SSFInstruction *) instr);
break;
case TR::Instruction::IsSI:
case TR::Instruction::IsSIY:
print(pOutFile, (TR::S390SIInstruction *) instr);
break;
case TR::Instruction::IsSIL:
print(pOutFile, (TR::S390SILInstruction *) instr);
break;
case TR::Instruction::IsS:
print(pOutFile, (TR::S390SInstruction *) instr);
break;
case TR::Instruction::IsNOP:
print(pOutFile, (TR::S390NOPInstruction *) instr);
break;
case TR::Instruction::IsAlignmentNop:
print(pOutFile, (TR::S390AlignmentNopInstruction *) instr);
break;
#ifdef J9_PROJECT_SPECIFIC
case TR::Instruction::IsVirtualGuardNOP:
print(pOutFile, (TR::S390VirtualGuardNOPInstruction *) instr);
break;
#endif
case TR::Instruction::IsAnnot:
print(pOutFile, (TR::S390AnnotationInstruction *) instr);
break;
case TR::Instruction::IsPseudo:
print(pOutFile, (TR::S390PseudoInstruction *) instr);
break;
case TR::Instruction::IsRRS:
print(pOutFile, (TR::S390RRSInstruction *) instr);
break;
case TR::Instruction::IsRIE:
print(pOutFile, (TR::S390RIEInstruction *) instr);
break;
case TR::Instruction::IsRIS:
print(pOutFile, (TR::S390RISInstruction *) instr);
break;
case TR::Instruction::IsOpCodeOnly:
print(pOutFile, (TR::S390OpCodeOnlyInstruction *) instr);
break;
case TR::Instruction::IsI:
print(pOutFile, (TR::S390IInstruction *) instr);
break;
case TR::Instruction::IsSSE:
print(pOutFile, (TR::S390SSEInstruction *) instr);
break;
case TR::Instruction::IsIE:
print(pOutFile, (TR::S390IEInstruction *) instr);
break;
case TR::Instruction::IsVRIa:
case TR::Instruction::IsVRIb:
case TR::Instruction::IsVRIc:
case TR::Instruction::IsVRId:
case TR::Instruction::IsVRIe:
case TR::Instruction::IsVRIf:
case TR::Instruction::IsVRIg:
case TR::Instruction::IsVRIh:
case TR::Instruction::IsVRIi:
print(pOutFile, (TR::S390VRIInstruction *) instr);
break;
case TR::Instruction::IsVRRa:
case TR::Instruction::IsVRRb:
case TR::Instruction::IsVRRc:
case TR::Instruction::IsVRRd:
case TR::Instruction::IsVRRe:
case TR::Instruction::IsVRRf:
case TR::Instruction::IsVRRg:
case TR::Instruction::IsVRRh:
case TR::Instruction::IsVRRi:
print(pOutFile, (TR::S390VRRInstruction *) instr);
break;
case TR::Instruction::IsVRSa:
case TR::Instruction::IsVRSb:
case TR::Instruction::IsVRSc:
case TR::Instruction::IsVRSd:
case TR::Instruction::IsVRV:
case TR::Instruction::IsVRX:
case TR::Instruction::IsVSI:
print(pOutFile, (TR::S390VStorageInstruction *) instr);
break;
default:
TR_ASSERT( 0, "unexpected instruction kind");
// fall thru
case TR::Instruction::IsNotExtended:
case TR::Instruction::IsE:
{
// ASSOCREGS piggy backs on a vanilla TR::Instruction
// if (instr->getOpCodeValue() == TR::InstOpCode::ASSOCREGS) break;
if ((instr->getOpCodeValue() == TR::InstOpCode::ASSOCREGS) && /*(debug("traceMsg90RA"))*/
(_comp->getOption(TR_TraceRA)))
{
if (_comp->cg()->getCodeGeneratorPhase() < TR::CodeGenPhase::BinaryEncodingPhase)
printAssocRegDirective(pOutFile, instr);
}
else
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s", instr->getOpCode().getMnemonicName());
trfflush(pOutFile);
}
}
}
// dump the inst's post deps
if (instr->getOpCodeValue() != TR::InstOpCode::ASSOCREGS && _comp->cg()->getCodeGeneratorPhase() <= TR::CodeGenPhase::BinaryEncodingPhase)
dumpDependencies(pOutFile, instr, false, true);
}
TR::Instruction*
TR_Debug::getOutlinedTargetIfAny(TR::Instruction *instr)
{
TR::LabelSymbol *label;
switch (instr->getKind())
{
#ifdef J9_PROJECT_SPECIFIC
case TR::Instruction::IsVirtualGuardNOP:
label = ((TR::S390VirtualGuardNOPInstruction *)instr)->getLabelSymbol();
break;
#endif
case TR::Instruction::IsBranch:
label = ((TR::S390BranchInstruction *)instr)->getLabelSymbol();
break;
case TR::Instruction::IsRIE:
label = ((TR::S390RIEInstruction *)instr)->getLabelSymbol();
break;
default:
return NULL;
}
if (!label || !label->isStartOfColdInstructionStream())
return NULL;
return label->getInstruction();
}
void TR_Debug::printS390OOLSequences(TR::FILE *pOutFile)
{
auto oiIterator = _cg->getS390OutOfLineCodeSectionList().begin();
while (oiIterator != _cg->getS390OutOfLineCodeSectionList().end())
{
trfprintf(pOutFile, "\n------------ start out-of-line instructions\n");
TR::Instruction *instr = (*oiIterator)->getFirstInstruction();
do {
print(pOutFile, instr);
instr = instr->getNext();
} while (instr != (*oiIterator)->getAppendInstruction());
if ((*oiIterator)->getAppendInstruction())
{
print(pOutFile, (*oiIterator)->getAppendInstruction());
}
trfprintf(pOutFile, "\n------------ end out-of-line instructions\n");
++oiIterator;
}
}
void
TR_Debug::dumpDependencies(TR::FILE *pOutFile, TR::Instruction * instr, bool pre, bool post)
{
TR::RegisterDependencyConditions *deps = instr->getDependencyConditions();
if (pOutFile == NULL || !deps || _comp->getOption(TR_DisableTraceRegDeps))
return;
if (pre)
{
if (deps->getNumPreConditions() > 0)
{
trfprintf(pOutFile, "\n PRE:");
printRegisterDependencies(pOutFile, deps->getPreConditions(), deps->getNumPreConditions());
}
}
if (post)
{
if (deps->getNumPostConditions() > 0)
{
trfprintf(pOutFile, "\n POST:");
printRegisterDependencies(pOutFile, deps->getPostConditions(), deps->getNumPostConditions());
}
}
trfflush(pOutFile);
}
void
TR_Debug::printInstructionComment(TR::FILE *pOutFile, int32_t tabStops, TR::Instruction *instr, bool needsStartComment)
{
while (tabStops-- > 0)
{
trfprintf(pOutFile, "\t");
}
dumpInstructionComments(pOutFile, instr, needsStartComment);
}
void
TR_Debug::printAssocRegDirective(TR::FILE *pOutFile, TR::Instruction * instr)
{
TR_S390RegisterDependencyGroup * depGroup = instr->getDependencyConditions()->getPostConditions();
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s", instr->getOpCode().getMnemonicName());
trfflush(pOutFile);
int first = TR::RealRegister::FirstGPR;
int last = TR::RealRegister::LastFPR;
for (int j = 0; j < last; ++j)
{
TR::RegisterDependency * dependency = depGroup->getRegisterDependency(j);
if ((intptr_t) dependency->getRegister() > 0)
{
TR::Register * virtReg = dependency->getRegister();
printS390RegisterDependency(pOutFile, virtReg, j+1, dependency->getRefsRegister(), dependency->getDefsRegister());
}
}
trfflush(pOutFile);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390RRSInstruction * instr)
{
// Prints RRS format in "Opcode R1,R2,D4(B4) (mask=M3)"
// print the line prefix.
printPrefix(pOutFile, instr);
// print the opcode.
trfprintf(pOutFile, "%-*s", OPCODE_SPACING, instr->getOpCode().getMnemonicName());
// grab the registers.
TR::Register * targetRegister = instr->getRegisterOperand(1);
TR::Register * sourceRegister = instr->getRegisterOperand(2);
// print the registers
print(pOutFile, targetRegister);
trfprintf(pOutFile, ",");
print(pOutFile, sourceRegister);
trfprintf(pOutFile, ",");
// print the branch destination memref
print(pOutFile, instr->getBranchDestinationLabel(), instr);
// finally, print the branch mask.
TR::InstOpCode::S390BranchCondition cond = instr->getBranchCondition();
const char * brCondName;
uint8_t mask = instr->getMask(); mask >>= 4;
brCondName = BranchConditionToNameMap[cond];
trfprintf(pOutFile, "%s(mask=0x%1x), ", brCondName, mask );
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390IEInstruction * instr)
{
if (pOutFile == NULL)
{
return;
}
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%-*s%d,%d", OPCODE_SPACING, instr->getOpCode().getMnemonicName(), instr->getImmediateField1(), instr->getImmediateField2());
printInstructionComment(pOutFile, 1, instr, true);
trfflush(pOutFile);
}
/**
* Prints RIE format, either:
* "Opcode R1,R2,imm (mask=)"
* "Opcode R1,imm,I2 (mask=)"
* "Opcode R1,I2 (mask=)"
*/
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390RIEInstruction * instr)
{
// let's determine what form of RIE we are dealing with
bool RIE1 = (instr->getRieForm() == TR::S390RIEInstruction::RIE_RR);
bool RIE2 = (instr->getRieForm() == TR::S390RIEInstruction::RIE_RI8);
bool RIE3 = (instr->getRieForm() == TR::S390RIEInstruction::RIE_RI16A);
bool RIE4 = (instr->getRieForm() == TR::S390RIEInstruction::RIE_RRI16);
bool RIE5 = (instr->getRieForm() == TR::S390RIEInstruction::RIE_IMM);
bool RIE6 = (instr->getRieForm() == TR::S390RIEInstruction::RIE_RI16G);
// print the line prefix
printPrefix(pOutFile, instr);
// print the opcode
trfprintf(pOutFile, "%-*s", OPCODE_SPACING, instr->getOpCode().getMnemonicName());
// grab the registers.
TR::Register * targetRegister = instr->getRegisterOperand(1);
TR::Register * sourceRegister = instr->getRegisterOperand(2);
// we can print the first register since we should always have it
print(pOutFile, targetRegister);
trfprintf(pOutFile, ",");
if(RIE1)
{
// we have the rightSide, so go ahead and print that now
print(pOutFile, sourceRegister);
trfprintf(pOutFile, ",");
// we'll print the immedate branch info now
print(pOutFile, instr->getBranchDestinationLabel());
trfprintf(pOutFile, ",");
}
else if(RIE2)
{
// we'll print the immedate branch info now
print(pOutFile, instr->getBranchDestinationLabel());
trfprintf(pOutFile, ",");
// print the immediate value
trfprintf(pOutFile, "%d,", instr->getSourceImmediate8());
}
else if(RIE4)
{
print(pOutFile, sourceRegister);
trfprintf(pOutFile, ",");
// print the immediate value
trfprintf(pOutFile, "%d,", instr->getSourceImmediate16());
}
else if(RIE5)
{
// print the source regiser (R2)
print(pOutFile, sourceRegister);
trfprintf(pOutFile, ",");
// print the immediate value
trfprintf(pOutFile, "%u,", (uint8_t)instr->getSourceImmediate8One());
// print the immediate value
trfprintf(pOutFile, "%u,", (uint8_t)instr->getSourceImmediate8Two());
}
else
{
// print the immediate value
trfprintf(pOutFile, "%d,", instr->getSourceImmediate16());
}
if (RIE5)
{
// print the immediate value
trfprintf(pOutFile, "%u", (uint8_t)instr->getSourceImmediate8());
}
else if(!RIE4)
{
// finally, print the branch mask.
TR::InstOpCode::S390BranchCondition cond = instr->getBranchCondition();
const char * brCondName;
uint8_t mask = instr->getMask(); mask >>= 4;
brCondName = BranchConditionToNameMap[cond];
trfprintf(pOutFile, "%s(mask=0x%1x), ", brCondName, mask );
}
printInstructionComment(pOutFile, 1, instr, true);
trfflush(pOutFile);
}
/**
* Prints RIS format in "Opcode R1,D4(B4),I2 (mask=)"
*/
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390RISInstruction * instr)
{
// print opcode
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%-*s", OPCODE_SPACING, instr->getOpCode().getMnemonicName());
// we can print the first register since we should always have it
print(pOutFile, instr->getRegisterOperand(1));
trfprintf(pOutFile, ",");
// print the branch destination memref.
print(pOutFile, instr->getMemoryReference(), instr);
trfprintf(pOutFile, ",");
// print the branch destination memref.
trfprintf(pOutFile,"%d", instr->getSourceImmediate(), instr);
// finally, print the branch mask.
TR::InstOpCode::S390BranchCondition cond = instr->getBranchCondition();
const char * brCondName;
uint8_t mask = instr->getMask(); mask >>= 4;
brCondName = BranchConditionToNameMap[cond];
trfprintf(pOutFile, "%s(mask=0x%1x), ", brCondName, mask );
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390LabelInstruction * instr)
{
TR::LabelSymbol * label = instr->getLabelSymbol();
const char * symbolName = getName(label);
printPrefix(pOutFile, instr);
if (instr->getOpCodeValue() == TR::InstOpCode::LABEL)
{
{
trfprintf(pOutFile, symbolName);
trfprintf(pOutFile, ":");
}
if (label->isStartInternalControlFlow())
{
trfprintf(pOutFile, "\t# (Start of internal control flow)");
}
else if (label->isEndInternalControlFlow())
{
trfprintf(pOutFile, "\t# (End of internal control flow)");
}
}
else
{
trfprintf(pOutFile, "%-*s", OPCODE_SPACING, instr->getOpCode().getMnemonicName());
if (instr->getCallSnippet())
{
print(pOutFile, instr->getCallSnippet()->getSnippetLabel());
intptr_t labelLoc = (intptr_t) instr->getCallSnippet()->getSnippetLabel()->getCodeLocation();
if (labelLoc)
{
trfprintf(pOutFile, ", labelTargetAddr=0x%p", labelLoc);
}
}
else
{
print(pOutFile, instr->getLabelSymbol());
intptr_t labelLoc = (intptr_t) instr->getLabelSymbol()->getCodeLocation();
if (labelLoc)
{
trfprintf(pOutFile, ", labelTargetAddr=0x%p", labelLoc);
}
}
}
printInstructionComment(pOutFile, 1, instr, true);
trfflush(pOutFile);
}
#ifdef J9_PROJECT_SPECIFIC
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390VirtualGuardNOPInstruction * instr)
{
printPrefix(pOutFile, instr);
TR::LabelSymbol * label = instr->getLabelSymbol();
if (instr->getNode()->isHCRGuard() && instr->getBinaryLength() == 0)
trfprintf(pOutFile, "VGNOP (empty patch) \t");
else
trfprintf(pOutFile, "VGNOP \t");
print(pOutFile, instr->getLabelSymbol());
intptr_t labelLoc = (intptr_t) instr->getLabelSymbol()->getCodeLocation();
if (labelLoc)
{
trfprintf(pOutFile, ", labelTargetAddr=0x%p", labelLoc);
}
printInstructionComment(pOutFile, 1, instr, true);
trfflush(pOutFile);
}
#endif
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390BranchInstruction * instr)
{
printPrefix(pOutFile, instr);
TR::InstOpCode::S390BranchCondition cond = instr->getBranchCondition();
const char * brCondName;
uint8_t mask = instr->getMask(); mask >>= 4;
brCondName = BranchConditionToNameMap[cond];
TR::LabelSymbol * label = instr->getLabelSymbol();
TR_ASSERT(instr->getOpCodeValue() != TR::InstOpCode::LABEL, "assertion failure");
trfprintf(pOutFile, "%-*s", OPCODE_SPACING, instr->getOpCode().getMnemonicName());
trfprintf(pOutFile, "%s(0x%1x), ", brCondName, mask );
if (instr->getCallSnippet())
{
print(pOutFile, instr->getCallSnippet()->getSnippetLabel());
intptr_t labelLoc = (intptr_t) instr->getCallSnippet()->getSnippetLabel()->getCodeLocation();
if (labelLoc)
{
trfprintf(pOutFile, ", labelTargetAddr=0x%p", labelLoc);
}
}
else
{
print(pOutFile, instr->getLabelSymbol());
intptr_t labelLoc = (intptr_t) instr->getLabelSymbol()->getCodeLocation();
if (labelLoc)
{
trfprintf(pOutFile, ", labelTargetAddr=0x%p", labelLoc);
}
}
printInstructionComment(pOutFile, 1, instr, true);
trfflush(pOutFile);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390BranchOnCountInstruction * instr)
{
printPrefix(pOutFile, instr);
TR::LabelSymbol * label = instr->getLabelSymbol();
TR_ASSERT(instr->getOpCodeValue() != TR::InstOpCode::LABEL, "assertion failure");
trfprintf(pOutFile, "%-*s", OPCODE_SPACING, instr->getOpCode().getMnemonicName());
print(pOutFile, instr->getRegisterOperand(1));
trfprintf(pOutFile, ",");
print(pOutFile, instr->getLabelSymbol());
intptr_t labelLoc = (intptr_t) instr->getLabelSymbol()->getCodeLocation();
if (labelLoc)
{
trfprintf(pOutFile, ", labelTargetAddr=0x%p", labelLoc);
}
printInstructionComment(pOutFile, 1, instr, true);
trfflush(pOutFile);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390BranchOnIndexInstruction * instr)
{
printPrefix(pOutFile, instr);
TR::LabelSymbol * label = instr->getLabelSymbol();
TR_ASSERT(instr->getOpCodeValue() != TR::InstOpCode::LABEL, "assertion failure");
trfprintf(pOutFile, "%-*s", OPCODE_SPACING, instr->getOpCode().getMnemonicName());
print(pOutFile, instr->getRegisterOperand(1));
trfprintf(pOutFile, ",");
TR::Register * sourceRegister = instr->getRegisterOperand(2);
TR::RegisterPair * regPair = sourceRegister->getRegisterPair();
if (regPair)
{
trfprintf(pOutFile, "(");
print(pOutFile, sourceRegister->getHighOrder());
trfprintf(pOutFile, ",");
print(pOutFile, sourceRegister->getLowOrder());
trfprintf(pOutFile, ")");
}
else
{
print(pOutFile, sourceRegister);
}
trfprintf(pOutFile, ",");
print(pOutFile, instr->getLabelSymbol());
intptr_t labelLoc = (intptr_t) instr->getLabelSymbol()->getCodeLocation();
if (labelLoc)
{
trfprintf(pOutFile, ", labelTargetAddr=0x%p", labelLoc);
}
printInstructionComment(pOutFile, 1, instr, true);
trfflush(pOutFile);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390AnnotationInstruction * instr)
{
if (pOutFile == NULL)
{
return;
}
trfprintf(pOutFile, instr->getAnnotation());
trfflush(pOutFile);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390PseudoInstruction * instr)
{
if (pOutFile == NULL)
{
return;
}
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%-*s", OPCODE_SPACING, instr->getOpCode().getMnemonicName());
if (instr->getOpCodeValue() == TR::InstOpCode::DCB)
{
if (static_cast<TR::S390DebugCounterBumpInstruction*>(instr)->getAssignableReg())
{
print(pOutFile, static_cast<TR::S390DebugCounterBumpInstruction*>(instr)->getAssignableReg());
}
else
{
trfprintf(pOutFile, "Spill Reg");
}
trfprintf(pOutFile, ", Debug Counter Bump");
}
if (instr->getOpCodeValue() == TR::InstOpCode::FENCE)
{
if (instr->getFenceNode() != NULL)
{
if (instr->getFenceNode()->getRelocationType() == TR_AbsoluteAddress)
{
trfprintf(pOutFile, "Absolute [");
}
else if (instr->getFenceNode()->getRelocationType() == TR_ExternalAbsoluteAddress)
{
trfprintf(pOutFile, "External Absolute [");
}
else
{
trfprintf(pOutFile, "Relative [");
}
for (int32_t i = 0; i < instr->getFenceNode()->getNumRelocations(); ++i)
{
if (!_comp->getOption(TR_MaskAddresses))
trfprintf(pOutFile, " %p", instr->getFenceNode()->getRelocationDestination(i));
}
trfprintf(pOutFile, " ]");
printBlockInfo(pOutFile, instr->getNode());
}
else
{
if (instr->getNode()->getOpCodeValue() == TR::loadFence)
{
trfprintf(pOutFile, "Load Fence");
}
else if (instr->getNode()->getOpCodeValue() == TR::storeFence)
{
trfprintf(pOutFile, "Store Fence");
}
}
}
#if TODO
dumpDependencies(pOutFile, instr);
#endif
printInstructionComment(pOutFile, 1, instr, true);
trfflush(pOutFile);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390ImmInstruction * instr)
{
if (pOutFile == NULL)
{
return;
}
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%-*s0x%08x", OPCODE_SPACING, instr->getOpCode().getMnemonicName(), instr->getSourceImmediate());
printInstructionComment(pOutFile, 1, instr, true);
trfflush(pOutFile);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390Imm2Instruction * instr)
{
if (pOutFile == NULL)
{
return;
}
printPrefix(pOutFile, instr);
// DC looks better in the tracefile than DC2 does....
trfprintf(pOutFile, "%-*s0x%04x", OPCODE_SPACING, "DC", instr->getSourceImmediate());
printInstructionComment(pOutFile, 1, instr, true);
trfflush(pOutFile);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390ImmSnippetInstruction * instr)
{
if (pOutFile == NULL)
{
return;
}
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%-*s0x%08x", OPCODE_SPACING, instr->getOpCode().getMnemonicName(), instr->getSourceImmediate());
trfflush(pOutFile);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390ImmSymInstruction * instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%-*s0x%08x", OPCODE_SPACING, instr->getOpCode().getMnemonicName(), instr->getSourceImmediate());
trfflush(pOutFile);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::S390RegInstruction * instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%-*s", OPCODE_SPACING, instr->getOpCode().getMnemonicName());
if (instr->getOpCodeValue() == TR::InstOpCode::BCR)
{
TR::InstOpCode::S390BranchCondition cond = instr->getBranchCondition();
uint8_t mask = instr->getMask(); mask >>= 4;
const char * brCondName;
brCondName = BranchConditionToNameMap[cond];
trfprintf(pOutFile, "%s(mask=0x%1x), ", brCondName, mask );
}
TR::Register * targetRegister = instr->getRegisterOperand(1);
TR::RegisterPair * regPair = targetRegister->getRegisterPair();
if (regPair)
{
print(pOutFile, targetRegister->getHighOrder());
}
else