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OMRInstOpCode.enum.temp.defines
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OMRInstOpCode.enum.temp.defines
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/*******************************************************************************
* Copyright (c) 2021, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
/*
* This file will be included within an enum. Only comments and enumerator
* definitions are permitted.
*/
#define BADIA32Op OMR::InstOpCode::BADIA32Op
#define ADC1AccImm1 OMR::InstOpCode::ADC1AccImm1
#define ADC2AccImm2 OMR::InstOpCode::ADC2AccImm2
#define ADC4AccImm4 OMR::InstOpCode::ADC4AccImm4
#define ADC8AccImm4 OMR::InstOpCode::ADC8AccImm4
#define ADC1RegImm1 OMR::InstOpCode::ADC1RegImm1
#define ADC2RegImm2 OMR::InstOpCode::ADC2RegImm2
#define ADC2RegImms OMR::InstOpCode::ADC2RegImms
#define ADC4RegImm4 OMR::InstOpCode::ADC4RegImm4
#define ADC8RegImm4 OMR::InstOpCode::ADC8RegImm4
#define ADC4RegImms OMR::InstOpCode::ADC4RegImms
#define ADC8RegImms OMR::InstOpCode::ADC8RegImms
#define ADC1MemImm1 OMR::InstOpCode::ADC1MemImm1
#define ADC2MemImm2 OMR::InstOpCode::ADC2MemImm2
#define ADC2MemImms OMR::InstOpCode::ADC2MemImms
#define ADC4MemImm4 OMR::InstOpCode::ADC4MemImm4
#define ADC8MemImm4 OMR::InstOpCode::ADC8MemImm4
#define ADC4MemImms OMR::InstOpCode::ADC4MemImms
#define ADC8MemImms OMR::InstOpCode::ADC8MemImms
#define ADC1RegReg OMR::InstOpCode::ADC1RegReg
#define ADC2RegReg OMR::InstOpCode::ADC2RegReg
#define ADC4RegReg OMR::InstOpCode::ADC4RegReg
#define ADC8RegReg OMR::InstOpCode::ADC8RegReg
#define ADC1RegMem OMR::InstOpCode::ADC1RegMem
#define ADC2RegMem OMR::InstOpCode::ADC2RegMem
#define ADC4RegMem OMR::InstOpCode::ADC4RegMem
#define ADC8RegMem OMR::InstOpCode::ADC8RegMem
#define ADC1MemReg OMR::InstOpCode::ADC1MemReg
#define ADC2MemReg OMR::InstOpCode::ADC2MemReg
#define ADC4MemReg OMR::InstOpCode::ADC4MemReg
#define ADC8MemReg OMR::InstOpCode::ADC8MemReg
#define ADD1AccImm1 OMR::InstOpCode::ADD1AccImm1
#define ADD2AccImm2 OMR::InstOpCode::ADD2AccImm2
#define ADD4AccImm4 OMR::InstOpCode::ADD4AccImm4
#define ADD8AccImm4 OMR::InstOpCode::ADD8AccImm4
#define ADD1RegImm1 OMR::InstOpCode::ADD1RegImm1
#define ADD2RegImm2 OMR::InstOpCode::ADD2RegImm2
#define ADD2RegImms OMR::InstOpCode::ADD2RegImms
#define ADD4RegImm4 OMR::InstOpCode::ADD4RegImm4
#define ADD8RegImm4 OMR::InstOpCode::ADD8RegImm4
#define ADD4RegImms OMR::InstOpCode::ADD4RegImms
#define ADD8RegImms OMR::InstOpCode::ADD8RegImms
#define ADD1MemImm1 OMR::InstOpCode::ADD1MemImm1
#define ADD2MemImm2 OMR::InstOpCode::ADD2MemImm2
#define ADD2MemImms OMR::InstOpCode::ADD2MemImms
#define ADD4MemImm4 OMR::InstOpCode::ADD4MemImm4
#define ADD8MemImm4 OMR::InstOpCode::ADD8MemImm4
#define ADD4MemImms OMR::InstOpCode::ADD4MemImms
#define ADD8MemImms OMR::InstOpCode::ADD8MemImms
#define ADD1RegReg OMR::InstOpCode::ADD1RegReg
#define ADD2RegReg OMR::InstOpCode::ADD2RegReg
#define ADD4RegReg OMR::InstOpCode::ADD4RegReg
#define ADD8RegReg OMR::InstOpCode::ADD8RegReg
#define ADD1RegMem OMR::InstOpCode::ADD1RegMem
#define ADD2RegMem OMR::InstOpCode::ADD2RegMem
#define ADD4RegMem OMR::InstOpCode::ADD4RegMem
#define ADD8RegMem OMR::InstOpCode::ADD8RegMem
#define ADD1MemReg OMR::InstOpCode::ADD1MemReg
#define ADD2MemReg OMR::InstOpCode::ADD2MemReg
#define ADD4MemReg OMR::InstOpCode::ADD4MemReg
#define ADD8MemReg OMR::InstOpCode::ADD8MemReg
#define ADDSSRegReg OMR::InstOpCode::ADDSSRegReg
#define ADDSSRegMem OMR::InstOpCode::ADDSSRegMem
#define ADDPSRegReg OMR::InstOpCode::ADDPSRegReg
#define ADDPSRegMem OMR::InstOpCode::ADDPSRegMem
#define ADDSDRegReg OMR::InstOpCode::ADDSDRegReg
#define ADDSDRegMem OMR::InstOpCode::ADDSDRegMem
#define ADDPDRegReg OMR::InstOpCode::ADDPDRegReg
#define ADDPDRegMem OMR::InstOpCode::ADDPDRegMem
#define LADD1MemReg OMR::InstOpCode::LADD1MemReg
#define LADD2MemReg OMR::InstOpCode::LADD2MemReg
#define LADD4MemReg OMR::InstOpCode::LADD4MemReg
#define LADD8MemReg OMR::InstOpCode::LADD8MemReg
#define LXADD1MemReg OMR::InstOpCode::LXADD1MemReg
#define LXADD2MemReg OMR::InstOpCode::LXADD2MemReg
#define LXADD4MemReg OMR::InstOpCode::LXADD4MemReg
#define LXADD8MemReg OMR::InstOpCode::LXADD8MemReg
#define AND1AccImm1 OMR::InstOpCode::AND1AccImm1
#define AND2AccImm2 OMR::InstOpCode::AND2AccImm2
#define AND4AccImm4 OMR::InstOpCode::AND4AccImm4
#define AND8AccImm4 OMR::InstOpCode::AND8AccImm4
#define AND1RegImm1 OMR::InstOpCode::AND1RegImm1
#define AND2RegImm2 OMR::InstOpCode::AND2RegImm2
#define AND2RegImms OMR::InstOpCode::AND2RegImms
#define AND4RegImm4 OMR::InstOpCode::AND4RegImm4
#define AND8RegImm4 OMR::InstOpCode::AND8RegImm4
#define AND4RegImms OMR::InstOpCode::AND4RegImms
#define AND8RegImms OMR::InstOpCode::AND8RegImms
#define AND1MemImm1 OMR::InstOpCode::AND1MemImm1
#define AND2MemImm2 OMR::InstOpCode::AND2MemImm2
#define AND2MemImms OMR::InstOpCode::AND2MemImms
#define AND4MemImm4 OMR::InstOpCode::AND4MemImm4
#define AND8MemImm4 OMR::InstOpCode::AND8MemImm4
#define AND4MemImms OMR::InstOpCode::AND4MemImms
#define AND8MemImms OMR::InstOpCode::AND8MemImms
#define AND1RegReg OMR::InstOpCode::AND1RegReg
#define AND2RegReg OMR::InstOpCode::AND2RegReg
#define AND4RegReg OMR::InstOpCode::AND4RegReg
#define AND8RegReg OMR::InstOpCode::AND8RegReg
#define AND1RegMem OMR::InstOpCode::AND1RegMem
#define AND2RegMem OMR::InstOpCode::AND2RegMem
#define AND4RegMem OMR::InstOpCode::AND4RegMem
#define AND8RegMem OMR::InstOpCode::AND8RegMem
#define AND1MemReg OMR::InstOpCode::AND1MemReg
#define AND2MemReg OMR::InstOpCode::AND2MemReg
#define AND4MemReg OMR::InstOpCode::AND4MemReg
#define AND8MemReg OMR::InstOpCode::AND8MemReg
#define BSF2RegReg OMR::InstOpCode::BSF2RegReg
#define BSF4RegReg OMR::InstOpCode::BSF4RegReg
#define BSF8RegReg OMR::InstOpCode::BSF8RegReg
#define BSR4RegReg OMR::InstOpCode::BSR4RegReg
#define BSR8RegReg OMR::InstOpCode::BSR8RegReg
#define BSWAP4Reg OMR::InstOpCode::BSWAP4Reg
#define BSWAP8Reg OMR::InstOpCode::BSWAP8Reg
#define BTR4RegImm1 OMR::InstOpCode::BTR4RegImm1
#define BTR8RegImm1 OMR::InstOpCode::BTR8RegImm1
#define BTS4RegReg OMR::InstOpCode::BTS4RegReg
#define BTS4MemReg OMR::InstOpCode::BTS4MemReg
#define BT4RegReg OMR::InstOpCode::BT4RegReg
#define BT8RegReg OMR::InstOpCode::BT8RegReg
#define CALLImm4 OMR::InstOpCode::CALLImm4
#define CALLREXImm4 OMR::InstOpCode::CALLREXImm4
#define CALLReg OMR::InstOpCode::CALLReg
#define CALLREXReg OMR::InstOpCode::CALLREXReg
#define CALLMem OMR::InstOpCode::CALLMem
#define CALLREXMem OMR::InstOpCode::CALLREXMem
#define CBWAcc OMR::InstOpCode::CBWAcc
#define CBWEAcc OMR::InstOpCode::CBWEAcc
#define CLC OMR::InstOpCode::CLC
#define CLD OMR::InstOpCode::CLD
#define CMOVA4RegMem OMR::InstOpCode::CMOVA4RegMem
#define CMOVA8RegMem OMR::InstOpCode::CMOVA8RegMem
#define CMOVB4RegMem OMR::InstOpCode::CMOVB4RegMem
#define CMOVE4RegMem OMR::InstOpCode::CMOVE4RegMem
#define CMOVE8RegMem OMR::InstOpCode::CMOVE8RegMem
#define CMOVG4RegMem OMR::InstOpCode::CMOVG4RegMem
#define CMOVGE4RegMem OMR::InstOpCode::CMOVGE4RegMem
#define CMOVGE8RegMem OMR::InstOpCode::CMOVGE8RegMem
#define CMOVL4RegMem OMR::InstOpCode::CMOVL4RegMem
#define CMOVNE4RegMem OMR::InstOpCode::CMOVNE4RegMem
#define CMOVNE8RegMem OMR::InstOpCode::CMOVNE8RegMem
#define CMOVNO4RegMem OMR::InstOpCode::CMOVNO4RegMem
#define CMOVNS4RegMem OMR::InstOpCode::CMOVNS4RegMem
#define CMOVO4RegMem OMR::InstOpCode::CMOVO4RegMem
#define CMOVP4RegMem OMR::InstOpCode::CMOVP4RegMem
#define CMOVP8RegMem OMR::InstOpCode::CMOVP8RegMem
#define CMOVS4RegMem OMR::InstOpCode::CMOVS4RegMem
#define CMP1AccImm1 OMR::InstOpCode::CMP1AccImm1
#define CMP2AccImm2 OMR::InstOpCode::CMP2AccImm2
#define CMP4AccImm4 OMR::InstOpCode::CMP4AccImm4
#define CMP8AccImm4 OMR::InstOpCode::CMP8AccImm4
#define CMP1RegImm1 OMR::InstOpCode::CMP1RegImm1
#define CMP2RegImm2 OMR::InstOpCode::CMP2RegImm2
#define CMP2RegImms OMR::InstOpCode::CMP2RegImms
#define CMP4RegImm4 OMR::InstOpCode::CMP4RegImm4
#define CMP8RegImm4 OMR::InstOpCode::CMP8RegImm4
#define CMP4RegImms OMR::InstOpCode::CMP4RegImms
#define CMP8RegImms OMR::InstOpCode::CMP8RegImms
#define CMP1MemImm1 OMR::InstOpCode::CMP1MemImm1
#define CMP2MemImm2 OMR::InstOpCode::CMP2MemImm2
#define CMP2MemImms OMR::InstOpCode::CMP2MemImms
#define CMP4MemImm4 OMR::InstOpCode::CMP4MemImm4
#define CMP8MemImm4 OMR::InstOpCode::CMP8MemImm4
#define CMP4MemImms OMR::InstOpCode::CMP4MemImms
#define CMP8MemImms OMR::InstOpCode::CMP8MemImms
#define CMP1RegReg OMR::InstOpCode::CMP1RegReg
#define CMP2RegReg OMR::InstOpCode::CMP2RegReg
#define CMP4RegReg OMR::InstOpCode::CMP4RegReg
#define CMP8RegReg OMR::InstOpCode::CMP8RegReg
#define CMP1RegMem OMR::InstOpCode::CMP1RegMem
#define CMP2RegMem OMR::InstOpCode::CMP2RegMem
#define CMP4RegMem OMR::InstOpCode::CMP4RegMem
#define CMP8RegMem OMR::InstOpCode::CMP8RegMem
#define CMP1MemReg OMR::InstOpCode::CMP1MemReg
#define CMP2MemReg OMR::InstOpCode::CMP2MemReg
#define CMP4MemReg OMR::InstOpCode::CMP4MemReg
#define CMP8MemReg OMR::InstOpCode::CMP8MemReg
#define CMPXCHG1MemReg OMR::InstOpCode::CMPXCHG1MemReg
#define CMPXCHG2MemReg OMR::InstOpCode::CMPXCHG2MemReg
#define CMPXCHG4MemReg OMR::InstOpCode::CMPXCHG4MemReg
#define CMPXCHG8MemReg OMR::InstOpCode::CMPXCHG8MemReg
#define CMPXCHG8BMem OMR::InstOpCode::CMPXCHG8BMem
#define CMPXCHG16BMem OMR::InstOpCode::CMPXCHG16BMem
#define LCMPXCHG1MemReg OMR::InstOpCode::LCMPXCHG1MemReg
#define LCMPXCHG2MemReg OMR::InstOpCode::LCMPXCHG2MemReg
#define LCMPXCHG4MemReg OMR::InstOpCode::LCMPXCHG4MemReg
#define LCMPXCHG8MemReg OMR::InstOpCode::LCMPXCHG8MemReg
#define LCMPXCHG8BMem OMR::InstOpCode::LCMPXCHG8BMem
#define LCMPXCHG16BMem OMR::InstOpCode::LCMPXCHG16BMem
#define XALCMPXCHG8MemReg OMR::InstOpCode::XALCMPXCHG8MemReg
#define XACMPXCHG8MemReg OMR::InstOpCode::XACMPXCHG8MemReg
#define XALCMPXCHG4MemReg OMR::InstOpCode::XALCMPXCHG4MemReg
#define XACMPXCHG4MemReg OMR::InstOpCode::XACMPXCHG4MemReg
#define CMPSB OMR::InstOpCode::CMPSB
#define CMPSW OMR::InstOpCode::CMPSW
#define CMPSD OMR::InstOpCode::CMPSD
#define CMPSQ OMR::InstOpCode::CMPSQ
#define CVTSI2SSRegReg4 OMR::InstOpCode::CVTSI2SSRegReg4
#define CVTSI2SSRegReg8 OMR::InstOpCode::CVTSI2SSRegReg8
#define CVTSI2SSRegMem OMR::InstOpCode::CVTSI2SSRegMem
#define CVTSI2SSRegMem8 OMR::InstOpCode::CVTSI2SSRegMem8
#define CVTSI2SDRegReg4 OMR::InstOpCode::CVTSI2SDRegReg4
#define CVTSI2SDRegReg8 OMR::InstOpCode::CVTSI2SDRegReg8
#define CVTSI2SDRegMem OMR::InstOpCode::CVTSI2SDRegMem
#define CVTSI2SDRegMem8 OMR::InstOpCode::CVTSI2SDRegMem8
#define CVTTSS2SIReg4Reg OMR::InstOpCode::CVTTSS2SIReg4Reg
#define CVTTSS2SIReg8Reg OMR::InstOpCode::CVTTSS2SIReg8Reg
#define CVTTSS2SIReg4Mem OMR::InstOpCode::CVTTSS2SIReg4Mem
#define CVTTSS2SIReg8Mem OMR::InstOpCode::CVTTSS2SIReg8Mem
#define CVTTSD2SIReg4Reg OMR::InstOpCode::CVTTSD2SIReg4Reg
#define CVTTSD2SIReg8Reg OMR::InstOpCode::CVTTSD2SIReg8Reg
#define CVTTSD2SIReg4Mem OMR::InstOpCode::CVTTSD2SIReg4Mem
#define CVTTSD2SIReg8Mem OMR::InstOpCode::CVTTSD2SIReg8Mem
#define CVTSS2SDRegReg OMR::InstOpCode::CVTSS2SDRegReg
#define CVTSS2SDRegMem OMR::InstOpCode::CVTSS2SDRegMem
#define CVTSD2SSRegReg OMR::InstOpCode::CVTSD2SSRegReg
#define CVTSD2SSRegMem OMR::InstOpCode::CVTSD2SSRegMem
#define CWDAcc OMR::InstOpCode::CWDAcc
#define CDQAcc OMR::InstOpCode::CDQAcc
#define CQOAcc OMR::InstOpCode::CQOAcc
#define DEC1Reg OMR::InstOpCode::DEC1Reg
#define DEC2Reg OMR::InstOpCode::DEC2Reg
#define DEC4Reg OMR::InstOpCode::DEC4Reg
#define DEC8Reg OMR::InstOpCode::DEC8Reg
#define DEC1Mem OMR::InstOpCode::DEC1Mem
#define DEC2Mem OMR::InstOpCode::DEC2Mem
#define DEC4Mem OMR::InstOpCode::DEC4Mem
#define DEC8Mem OMR::InstOpCode::DEC8Mem
#define FABSReg OMR::InstOpCode::FABSReg
#define DABSReg OMR::InstOpCode::DABSReg
#define FSQRTReg OMR::InstOpCode::FSQRTReg
#define DSQRTReg OMR::InstOpCode::DSQRTReg
#define FADDRegReg OMR::InstOpCode::FADDRegReg
#define DADDRegReg OMR::InstOpCode::DADDRegReg
#define FADDPReg OMR::InstOpCode::FADDPReg
#define FADDRegMem OMR::InstOpCode::FADDRegMem
#define DADDRegMem OMR::InstOpCode::DADDRegMem
#define FIADDRegMem OMR::InstOpCode::FIADDRegMem
#define DIADDRegMem OMR::InstOpCode::DIADDRegMem
#define FSADDRegMem OMR::InstOpCode::FSADDRegMem
#define DSADDRegMem OMR::InstOpCode::DSADDRegMem
#define FCHSReg OMR::InstOpCode::FCHSReg
#define DCHSReg OMR::InstOpCode::DCHSReg
#define FDIVRegReg OMR::InstOpCode::FDIVRegReg
#define DDIVRegReg OMR::InstOpCode::DDIVRegReg
#define FDIVRegMem OMR::InstOpCode::FDIVRegMem
#define DDIVRegMem OMR::InstOpCode::DDIVRegMem
#define FDIVPReg OMR::InstOpCode::FDIVPReg
#define FIDIVRegMem OMR::InstOpCode::FIDIVRegMem
#define DIDIVRegMem OMR::InstOpCode::DIDIVRegMem
#define FSDIVRegMem OMR::InstOpCode::FSDIVRegMem
#define DSDIVRegMem OMR::InstOpCode::DSDIVRegMem
#define FDIVRRegReg OMR::InstOpCode::FDIVRRegReg
#define DDIVRRegReg OMR::InstOpCode::DDIVRRegReg
#define FDIVRRegMem OMR::InstOpCode::FDIVRRegMem
#define DDIVRRegMem OMR::InstOpCode::DDIVRRegMem
#define FDIVRPReg OMR::InstOpCode::FDIVRPReg
#define FIDIVRRegMem OMR::InstOpCode::FIDIVRRegMem
#define DIDIVRRegMem OMR::InstOpCode::DIDIVRRegMem
#define FSDIVRRegMem OMR::InstOpCode::FSDIVRRegMem
#define DSDIVRRegMem OMR::InstOpCode::DSDIVRRegMem
#define FILDRegMem OMR::InstOpCode::FILDRegMem
#define DILDRegMem OMR::InstOpCode::DILDRegMem
#define FLLDRegMem OMR::InstOpCode::FLLDRegMem
#define DLLDRegMem OMR::InstOpCode::DLLDRegMem
#define FSLDRegMem OMR::InstOpCode::FSLDRegMem
#define DSLDRegMem OMR::InstOpCode::DSLDRegMem
#define FISTMemReg OMR::InstOpCode::FISTMemReg
#define DISTMemReg OMR::InstOpCode::DISTMemReg
#define FISTPMem OMR::InstOpCode::FISTPMem
#define DISTPMem OMR::InstOpCode::DISTPMem
#define FLSTPMem OMR::InstOpCode::FLSTPMem
#define FLSTTPMem OMR::InstOpCode::FLSTTPMem
#define DLSTPMem OMR::InstOpCode::DLSTPMem
#define FSSTMemReg OMR::InstOpCode::FSSTMemReg
#define DSSTMemReg OMR::InstOpCode::DSSTMemReg
#define FSSTPMem OMR::InstOpCode::FSSTPMem
#define DSSTPMem OMR::InstOpCode::DSSTPMem
#define FLDLN2 OMR::InstOpCode::FLDLN2
#define FLDRegReg OMR::InstOpCode::FLDRegReg
#define FLDDUP OMR::InstOpCode::FLDDUP
#define DLDRegReg OMR::InstOpCode::DLDRegReg
#define FLDRegMem OMR::InstOpCode::FLDRegMem
#define DLDRegMem OMR::InstOpCode::DLDRegMem
#define FLD0Reg OMR::InstOpCode::FLD0Reg
#define DLD0Reg OMR::InstOpCode::DLD0Reg
#define FLD1Reg OMR::InstOpCode::FLD1Reg
#define DLD1Reg OMR::InstOpCode::DLD1Reg
#define FLDMem OMR::InstOpCode::FLDMem
#define DLDMem OMR::InstOpCode::DLDMem
#define LDCWMem OMR::InstOpCode::LDCWMem
#define FMULRegReg OMR::InstOpCode::FMULRegReg
#define DMULRegReg OMR::InstOpCode::DMULRegReg
#define FMULPReg OMR::InstOpCode::FMULPReg
#define FMULRegMem OMR::InstOpCode::FMULRegMem
#define DMULRegMem OMR::InstOpCode::DMULRegMem
#define FIMULRegMem OMR::InstOpCode::FIMULRegMem
#define DIMULRegMem OMR::InstOpCode::DIMULRegMem
#define FSMULRegMem OMR::InstOpCode::FSMULRegMem
#define DSMULRegMem OMR::InstOpCode::DSMULRegMem
#define FNCLEX OMR::InstOpCode::FNCLEX
#define FPREMRegReg OMR::InstOpCode::FPREMRegReg
#define FSCALERegReg OMR::InstOpCode::FSCALERegReg
#define FSTMemReg OMR::InstOpCode::FSTMemReg
#define DSTMemReg OMR::InstOpCode::DSTMemReg
#define FSTRegReg OMR::InstOpCode::FSTRegReg
#define DSTRegReg OMR::InstOpCode::DSTRegReg
#define FSTPMemReg OMR::InstOpCode::FSTPMemReg
#define DSTPMemReg OMR::InstOpCode::DSTPMemReg
#define FSTPReg OMR::InstOpCode::FSTPReg
#define FSTPST0 OMR::InstOpCode::FSTPST0
#define DSTPReg OMR::InstOpCode::DSTPReg
#define STCWMem OMR::InstOpCode::STCWMem
#define STSWMem OMR::InstOpCode::STSWMem
#define STSWAcc OMR::InstOpCode::STSWAcc
#define FSUBRegReg OMR::InstOpCode::FSUBRegReg
#define DSUBRegReg OMR::InstOpCode::DSUBRegReg
#define FSUBRegMem OMR::InstOpCode::FSUBRegMem
#define DSUBRegMem OMR::InstOpCode::DSUBRegMem
#define FSUBPReg OMR::InstOpCode::FSUBPReg
#define FISUBRegMem OMR::InstOpCode::FISUBRegMem
#define DISUBRegMem OMR::InstOpCode::DISUBRegMem
#define FSSUBRegMem OMR::InstOpCode::FSSUBRegMem
#define DSSUBRegMem OMR::InstOpCode::DSSUBRegMem
#define FSUBRRegReg OMR::InstOpCode::FSUBRRegReg
#define DSUBRRegReg OMR::InstOpCode::DSUBRRegReg
#define FSUBRRegMem OMR::InstOpCode::FSUBRRegMem
#define DSUBRRegMem OMR::InstOpCode::DSUBRRegMem
#define FSUBRPReg OMR::InstOpCode::FSUBRPReg
#define FISUBRRegMem OMR::InstOpCode::FISUBRRegMem
#define DISUBRRegMem OMR::InstOpCode::DISUBRRegMem
#define FSSUBRRegMem OMR::InstOpCode::FSSUBRRegMem
#define DSSUBRRegMem OMR::InstOpCode::DSSUBRRegMem
#define FTSTReg OMR::InstOpCode::FTSTReg
#define FCOMRegReg OMR::InstOpCode::FCOMRegReg
#define DCOMRegReg OMR::InstOpCode::DCOMRegReg
#define FCOMRegMem OMR::InstOpCode::FCOMRegMem
#define DCOMRegMem OMR::InstOpCode::DCOMRegMem
#define FCOMPReg OMR::InstOpCode::FCOMPReg
#define FCOMPMem OMR::InstOpCode::FCOMPMem
#define DCOMPMem OMR::InstOpCode::DCOMPMem
#define FCOMPP OMR::InstOpCode::FCOMPP
#define FCOMIRegReg OMR::InstOpCode::FCOMIRegReg
#define DCOMIRegReg OMR::InstOpCode::DCOMIRegReg
#define FCOMIPReg OMR::InstOpCode::FCOMIPReg
#define FYL2X OMR::InstOpCode::FYL2X
#define UCOMISSRegReg OMR::InstOpCode::UCOMISSRegReg
#define UCOMISSRegMem OMR::InstOpCode::UCOMISSRegMem
#define UCOMISDRegReg OMR::InstOpCode::UCOMISDRegReg
#define UCOMISDRegMem OMR::InstOpCode::UCOMISDRegMem
#define FXCHReg OMR::InstOpCode::FXCHReg
#define IDIV1AccReg OMR::InstOpCode::IDIV1AccReg
#define IDIV2AccReg OMR::InstOpCode::IDIV2AccReg
#define IDIV4AccReg OMR::InstOpCode::IDIV4AccReg
#define IDIV8AccReg OMR::InstOpCode::IDIV8AccReg
#define DIV4AccReg OMR::InstOpCode::DIV4AccReg
#define DIV8AccReg OMR::InstOpCode::DIV8AccReg
#define IDIV1AccMem OMR::InstOpCode::IDIV1AccMem
#define IDIV2AccMem OMR::InstOpCode::IDIV2AccMem
#define IDIV4AccMem OMR::InstOpCode::IDIV4AccMem
#define IDIV8AccMem OMR::InstOpCode::IDIV8AccMem
#define DIV4AccMem OMR::InstOpCode::DIV4AccMem
#define DIV8AccMem OMR::InstOpCode::DIV8AccMem
#define DIVSSRegReg OMR::InstOpCode::DIVSSRegReg
#define DIVSSRegMem OMR::InstOpCode::DIVSSRegMem
#define DIVPSRegReg OMR::InstOpCode::DIVPSRegReg
#define DIVPSRegMem OMR::InstOpCode::DIVPSRegMem
#define DIVSDRegReg OMR::InstOpCode::DIVSDRegReg
#define DIVSDRegMem OMR::InstOpCode::DIVSDRegMem
#define DIVPDRegReg OMR::InstOpCode::DIVPDRegReg
#define DIVPDRegMem OMR::InstOpCode::DIVPDRegMem
#define IMUL1AccReg OMR::InstOpCode::IMUL1AccReg
#define IMUL2AccReg OMR::InstOpCode::IMUL2AccReg
#define IMUL4AccReg OMR::InstOpCode::IMUL4AccReg
#define IMUL8AccReg OMR::InstOpCode::IMUL8AccReg
#define IMUL1AccMem OMR::InstOpCode::IMUL1AccMem
#define IMUL2AccMem OMR::InstOpCode::IMUL2AccMem
#define IMUL4AccMem OMR::InstOpCode::IMUL4AccMem
#define IMUL8AccMem OMR::InstOpCode::IMUL8AccMem
#define IMUL2RegReg OMR::InstOpCode::IMUL2RegReg
#define IMUL4RegReg OMR::InstOpCode::IMUL4RegReg
#define IMUL8RegReg OMR::InstOpCode::IMUL8RegReg
#define IMUL2RegMem OMR::InstOpCode::IMUL2RegMem
#define IMUL4RegMem OMR::InstOpCode::IMUL4RegMem
#define IMUL8RegMem OMR::InstOpCode::IMUL8RegMem
#define IMUL2RegRegImm2 OMR::InstOpCode::IMUL2RegRegImm2
#define IMUL2RegRegImms OMR::InstOpCode::IMUL2RegRegImms
#define IMUL4RegRegImm4 OMR::InstOpCode::IMUL4RegRegImm4
#define IMUL8RegRegImm4 OMR::InstOpCode::IMUL8RegRegImm4
#define IMUL4RegRegImms OMR::InstOpCode::IMUL4RegRegImms
#define IMUL8RegRegImms OMR::InstOpCode::IMUL8RegRegImms
#define IMUL2RegMemImm2 OMR::InstOpCode::IMUL2RegMemImm2
#define IMUL2RegMemImms OMR::InstOpCode::IMUL2RegMemImms
#define IMUL4RegMemImm4 OMR::InstOpCode::IMUL4RegMemImm4
#define IMUL8RegMemImm4 OMR::InstOpCode::IMUL8RegMemImm4
#define IMUL4RegMemImms OMR::InstOpCode::IMUL4RegMemImms
#define IMUL8RegMemImms OMR::InstOpCode::IMUL8RegMemImms
#define MUL1AccReg OMR::InstOpCode::MUL1AccReg
#define MUL2AccReg OMR::InstOpCode::MUL2AccReg
#define MUL4AccReg OMR::InstOpCode::MUL4AccReg
#define MUL8AccReg OMR::InstOpCode::MUL8AccReg
#define MUL1AccMem OMR::InstOpCode::MUL1AccMem
#define MUL2AccMem OMR::InstOpCode::MUL2AccMem
#define MUL4AccMem OMR::InstOpCode::MUL4AccMem
#define MUL8AccMem OMR::InstOpCode::MUL8AccMem
#define MULSSRegReg OMR::InstOpCode::MULSSRegReg
#define MULSSRegMem OMR::InstOpCode::MULSSRegMem
#define MULPSRegReg OMR::InstOpCode::MULPSRegReg
#define MULPSRegMem OMR::InstOpCode::MULPSRegMem
#define MULSDRegReg OMR::InstOpCode::MULSDRegReg
#define MULSDRegMem OMR::InstOpCode::MULSDRegMem
#define MULPDRegReg OMR::InstOpCode::MULPDRegReg
#define MULPDRegMem OMR::InstOpCode::MULPDRegMem
#define INC1Reg OMR::InstOpCode::INC1Reg
#define INC2Reg OMR::InstOpCode::INC2Reg
#define INC4Reg OMR::InstOpCode::INC4Reg
#define INC8Reg OMR::InstOpCode::INC8Reg
#define INC1Mem OMR::InstOpCode::INC1Mem
#define INC2Mem OMR::InstOpCode::INC2Mem
#define INC4Mem OMR::InstOpCode::INC4Mem
#define INC8Mem OMR::InstOpCode::INC8Mem
#define JA1 OMR::InstOpCode::JA1
#define JAE1 OMR::InstOpCode::JAE1
#define JB1 OMR::InstOpCode::JB1
#define JBE1 OMR::InstOpCode::JBE1
#define JE1 OMR::InstOpCode::JE1
#define JNE1 OMR::InstOpCode::JNE1
#define JG1 OMR::InstOpCode::JG1
#define JGE1 OMR::InstOpCode::JGE1
#define JL1 OMR::InstOpCode::JL1
#define JLE1 OMR::InstOpCode::JLE1
#define JO1 OMR::InstOpCode::JO1
#define JNO1 OMR::InstOpCode::JNO1
#define JS1 OMR::InstOpCode::JS1
#define JNS1 OMR::InstOpCode::JNS1
#define JPO1 OMR::InstOpCode::JPO1
#define JPE1 OMR::InstOpCode::JPE1
#define JMP1 OMR::InstOpCode::JMP1
#define JA4 OMR::InstOpCode::JA4
#define JAE4 OMR::InstOpCode::JAE4
#define JB4 OMR::InstOpCode::JB4
#define JBE4 OMR::InstOpCode::JBE4
#define JE4 OMR::InstOpCode::JE4
#define JNE4 OMR::InstOpCode::JNE4
#define JG4 OMR::InstOpCode::JG4
#define JGE4 OMR::InstOpCode::JGE4
#define JL4 OMR::InstOpCode::JL4
#define JLE4 OMR::InstOpCode::JLE4
#define JO4 OMR::InstOpCode::JO4
#define JNO4 OMR::InstOpCode::JNO4
#define JS4 OMR::InstOpCode::JS4
#define JNS4 OMR::InstOpCode::JNS4
#define JPO4 OMR::InstOpCode::JPO4
#define JPE4 OMR::InstOpCode::JPE4
#define JMP4 OMR::InstOpCode::JMP4
#define JMPReg OMR::InstOpCode::JMPReg
#define JMPMem OMR::InstOpCode::JMPMem
#define JRCXZ1 OMR::InstOpCode::JRCXZ1
#define LOOP1 OMR::InstOpCode::LOOP1
#define LAHF OMR::InstOpCode::LAHF
#define LDDQU OMR::InstOpCode::LDDQU
#define LEA2RegMem OMR::InstOpCode::LEA2RegMem
#define LEA4RegMem OMR::InstOpCode::LEA4RegMem
#define LEA8RegMem OMR::InstOpCode::LEA8RegMem
#define S1MemReg OMR::InstOpCode::S1MemReg
#define S2MemReg OMR::InstOpCode::S2MemReg
#define S4MemReg OMR::InstOpCode::S4MemReg
#define S8MemReg OMR::InstOpCode::S8MemReg
#define S1MemImm1 OMR::InstOpCode::S1MemImm1
#define S2MemImm2 OMR::InstOpCode::S2MemImm2
#define S4MemImm4 OMR::InstOpCode::S4MemImm4
#define XRS4MemImm4 OMR::InstOpCode::XRS4MemImm4
#define S8MemImm4 OMR::InstOpCode::S8MemImm4
#define XRS8MemImm4 OMR::InstOpCode::XRS8MemImm4
#define L1RegMem OMR::InstOpCode::L1RegMem
#define L2RegMem OMR::InstOpCode::L2RegMem
#define L4RegMem OMR::InstOpCode::L4RegMem
#define L8RegMem OMR::InstOpCode::L8RegMem
#define MOVAPSRegReg OMR::InstOpCode::MOVAPSRegReg
#define MOVAPSRegMem OMR::InstOpCode::MOVAPSRegMem
#define MOVAPSMemReg OMR::InstOpCode::MOVAPSMemReg
#define MOVAPDRegReg OMR::InstOpCode::MOVAPDRegReg
#define MOVAPDRegMem OMR::InstOpCode::MOVAPDRegMem
#define MOVAPDMemReg OMR::InstOpCode::MOVAPDMemReg
#define MOVUPSRegReg OMR::InstOpCode::MOVUPSRegReg
#define MOVUPSRegMem OMR::InstOpCode::MOVUPSRegMem
#define MOVUPSMemReg OMR::InstOpCode::MOVUPSMemReg
#define MOVUPDRegReg OMR::InstOpCode::MOVUPDRegReg
#define MOVUPDRegMem OMR::InstOpCode::MOVUPDRegMem
#define MOVUPDMemReg OMR::InstOpCode::MOVUPDMemReg
#define MOVSSRegReg OMR::InstOpCode::MOVSSRegReg
#define MOVSSRegMem OMR::InstOpCode::MOVSSRegMem
#define MOVSSMemReg OMR::InstOpCode::MOVSSMemReg
#define MOVSDRegReg OMR::InstOpCode::MOVSDRegReg
#define MOVSDRegMem OMR::InstOpCode::MOVSDRegMem
#define MOVSDMemReg OMR::InstOpCode::MOVSDMemReg
#define SQRTSSRegReg OMR::InstOpCode::SQRTSSRegReg
#define SQRTSDRegReg OMR::InstOpCode::SQRTSDRegReg
#define MOVDRegReg4 OMR::InstOpCode::MOVDRegReg4
#define MOVQRegReg8 OMR::InstOpCode::MOVQRegReg8
#define MOVDReg4Reg OMR::InstOpCode::MOVDReg4Reg
#define MOVQReg8Reg OMR::InstOpCode::MOVQReg8Reg
#define MOVDQURegReg OMR::InstOpCode::MOVDQURegReg
#define MOVDQURegMem OMR::InstOpCode::MOVDQURegMem
#define VMOVDQURegReg OMR::InstOpCode::VMOVDQURegReg
#define VMOVDQURegMem OMR::InstOpCode::VMOVDQURegMem
#define MOVDQUMemReg OMR::InstOpCode::MOVDQUMemReg
#define MOV1RegReg OMR::InstOpCode::MOV1RegReg
#define MOV2RegReg OMR::InstOpCode::MOV2RegReg
#define MOV4RegReg OMR::InstOpCode::MOV4RegReg
#define MOV8RegReg OMR::InstOpCode::MOV8RegReg
#define CMOVB4RegReg OMR::InstOpCode::CMOVB4RegReg
#define CMOVB8RegReg OMR::InstOpCode::CMOVB8RegReg
#define CMOVG4RegReg OMR::InstOpCode::CMOVG4RegReg
#define CMOVG8RegReg OMR::InstOpCode::CMOVG8RegReg
#define CMOVGE4RegReg OMR::InstOpCode::CMOVGE4RegReg
#define CMOVGE8RegReg OMR::InstOpCode::CMOVGE8RegReg
#define CMOVL4RegReg OMR::InstOpCode::CMOVL4RegReg
#define CMOVL8RegReg OMR::InstOpCode::CMOVL8RegReg
#define CMOVLE4RegReg OMR::InstOpCode::CMOVLE4RegReg
#define CMOVLE8RegReg OMR::InstOpCode::CMOVLE8RegReg
#define CMOVE4RegReg OMR::InstOpCode::CMOVE4RegReg
#define CMOVE8RegReg OMR::InstOpCode::CMOVE8RegReg
#define CMOVNE4RegReg OMR::InstOpCode::CMOVNE4RegReg
#define CMOVNE8RegReg OMR::InstOpCode::CMOVNE8RegReg
#define CMOVS4RegReg OMR::InstOpCode::CMOVS4RegReg
#define CMOVS8RegReg OMR::InstOpCode::CMOVS8RegReg
#define MOV1RegImm1 OMR::InstOpCode::MOV1RegImm1
#define MOV2RegImm2 OMR::InstOpCode::MOV2RegImm2
#define MOV4RegImm4 OMR::InstOpCode::MOV4RegImm4
#define MOV8RegImm4 OMR::InstOpCode::MOV8RegImm4
#define MOV8RegImm64 OMR::InstOpCode::MOV8RegImm64
#define MOVLPDRegMem OMR::InstOpCode::MOVLPDRegMem
#define MOVLPDMemReg OMR::InstOpCode::MOVLPDMemReg
#define MOVDRegMem OMR::InstOpCode::MOVDRegMem
#define MOVDMemReg OMR::InstOpCode::MOVDMemReg
#define MOVQRegMem OMR::InstOpCode::MOVQRegMem
#define MOVQMemReg OMR::InstOpCode::MOVQMemReg
#define MOVSB OMR::InstOpCode::MOVSB
#define MOVSW OMR::InstOpCode::MOVSW
#define MOVSD OMR::InstOpCode::MOVSD
#define MOVSQ OMR::InstOpCode::MOVSQ
#define MOVSXReg2Reg1 OMR::InstOpCode::MOVSXReg2Reg1
#define MOVSXReg4Reg1 OMR::InstOpCode::MOVSXReg4Reg1
#define MOVSXReg8Reg1 OMR::InstOpCode::MOVSXReg8Reg1
#define MOVSXReg4Reg2 OMR::InstOpCode::MOVSXReg4Reg2
#define MOVSXReg8Reg2 OMR::InstOpCode::MOVSXReg8Reg2
#define MOVSXReg8Reg4 OMR::InstOpCode::MOVSXReg8Reg4
#define MOVSXReg2Mem1 OMR::InstOpCode::MOVSXReg2Mem1
#define MOVSXReg4Mem1 OMR::InstOpCode::MOVSXReg4Mem1
#define MOVSXReg8Mem1 OMR::InstOpCode::MOVSXReg8Mem1
#define MOVSXReg4Mem2 OMR::InstOpCode::MOVSXReg4Mem2
#define MOVSXReg8Mem2 OMR::InstOpCode::MOVSXReg8Mem2
#define MOVSXReg8Mem4 OMR::InstOpCode::MOVSXReg8Mem4
#define MOVZXReg2Reg1 OMR::InstOpCode::MOVZXReg2Reg1
#define MOVZXReg4Reg1 OMR::InstOpCode::MOVZXReg4Reg1
#define MOVZXReg8Reg1 OMR::InstOpCode::MOVZXReg8Reg1
#define MOVZXReg4Reg2 OMR::InstOpCode::MOVZXReg4Reg2
#define MOVZXReg8Reg2 OMR::InstOpCode::MOVZXReg8Reg2
#define MOVZXReg8Reg4 OMR::InstOpCode::MOVZXReg8Reg4
#define MOVZXReg2Mem1 OMR::InstOpCode::MOVZXReg2Mem1
#define MOVZXReg4Mem1 OMR::InstOpCode::MOVZXReg4Mem1
#define MOVZXReg8Mem1 OMR::InstOpCode::MOVZXReg8Mem1
#define MOVZXReg4Mem2 OMR::InstOpCode::MOVZXReg4Mem2
#define MOVZXReg8Mem2 OMR::InstOpCode::MOVZXReg8Mem2
#define NEG1Reg OMR::InstOpCode::NEG1Reg
#define NEG2Reg OMR::InstOpCode::NEG2Reg
#define NEG4Reg OMR::InstOpCode::NEG4Reg
#define NEG8Reg OMR::InstOpCode::NEG8Reg
#define NEG1Mem OMR::InstOpCode::NEG1Mem
#define NEG2Mem OMR::InstOpCode::NEG2Mem
#define NEG4Mem OMR::InstOpCode::NEG4Mem
#define NEG8Mem OMR::InstOpCode::NEG8Mem
#define NOT1Reg OMR::InstOpCode::NOT1Reg
#define NOT2Reg OMR::InstOpCode::NOT2Reg
#define NOT4Reg OMR::InstOpCode::NOT4Reg
#define NOT8Reg OMR::InstOpCode::NOT8Reg
#define NOT1Mem OMR::InstOpCode::NOT1Mem
#define NOT2Mem OMR::InstOpCode::NOT2Mem
#define NOT4Mem OMR::InstOpCode::NOT4Mem
#define NOT8Mem OMR::InstOpCode::NOT8Mem
#define OR1AccImm1 OMR::InstOpCode::OR1AccImm1
#define OR2AccImm2 OMR::InstOpCode::OR2AccImm2
#define OR4AccImm4 OMR::InstOpCode::OR4AccImm4
#define OR8AccImm4 OMR::InstOpCode::OR8AccImm4
#define OR1RegImm1 OMR::InstOpCode::OR1RegImm1
#define OR2RegImm2 OMR::InstOpCode::OR2RegImm2
#define OR2RegImms OMR::InstOpCode::OR2RegImms
#define OR4RegImm4 OMR::InstOpCode::OR4RegImm4
#define OR8RegImm4 OMR::InstOpCode::OR8RegImm4
#define OR4RegImms OMR::InstOpCode::OR4RegImms
#define OR8RegImms OMR::InstOpCode::OR8RegImms
#define OR1MemImm1 OMR::InstOpCode::OR1MemImm1
#define OR2MemImm2 OMR::InstOpCode::OR2MemImm2
#define OR2MemImms OMR::InstOpCode::OR2MemImms
#define OR4MemImm4 OMR::InstOpCode::OR4MemImm4
#define OR8MemImm4 OMR::InstOpCode::OR8MemImm4
#define OR4MemImms OMR::InstOpCode::OR4MemImms
#define LOR4MemImms OMR::InstOpCode::LOR4MemImms
#define LOR4MemReg OMR::InstOpCode::LOR4MemReg
#define LOR8MemReg OMR::InstOpCode::LOR8MemReg
#define OR8MemImms OMR::InstOpCode::OR8MemImms
#define OR1RegReg OMR::InstOpCode::OR1RegReg
#define OR2RegReg OMR::InstOpCode::OR2RegReg
#define OR4RegReg OMR::InstOpCode::OR4RegReg
#define OR8RegReg OMR::InstOpCode::OR8RegReg
#define OR1RegMem OMR::InstOpCode::OR1RegMem
#define OR2RegMem OMR::InstOpCode::OR2RegMem
#define OR4RegMem OMR::InstOpCode::OR4RegMem
#define OR8RegMem OMR::InstOpCode::OR8RegMem
#define OR1MemReg OMR::InstOpCode::OR1MemReg
#define OR2MemReg OMR::InstOpCode::OR2MemReg
#define OR4MemReg OMR::InstOpCode::OR4MemReg
#define OR8MemReg OMR::InstOpCode::OR8MemReg
#define PAUSE OMR::InstOpCode::PAUSE
#define PACKUSWBRegReg OMR::InstOpCode::PACKUSWBRegReg
#define PUNPCKHBWRegReg OMR::InstOpCode::PUNPCKHBWRegReg
#define PUNPCKLBWRegReg OMR::InstOpCode::PUNPCKLBWRegReg
#define PCMPEQBRegReg OMR::InstOpCode::PCMPEQBRegReg
#define VPCMPEQBRegReg OMR::InstOpCode::VPCMPEQBRegReg
#define VPCMPEQBRegMem OMR::InstOpCode::VPCMPEQBRegMem
#define PCMPEQWRegReg OMR::InstOpCode::PCMPEQWRegReg
#define VPCMPEQWRegReg OMR::InstOpCode::VPCMPEQWRegReg
#define VPCMPEQWRegMem OMR::InstOpCode::VPCMPEQWRegMem
#define PCMPGTBRegReg OMR::InstOpCode::PCMPGTBRegReg
#define PCMPGTWRegReg OMR::InstOpCode::PCMPGTWRegReg
#define PMOVMSKB4RegReg OMR::InstOpCode::PMOVMSKB4RegReg
#define VPMOVMSKB4RegReg OMR::InstOpCode::VPMOVMSKB4RegReg
#define PMOVZXBDRegReg OMR::InstOpCode::PMOVZXBDRegReg
#define PMOVZXBDRegMem OMR::InstOpCode::PMOVZXBDRegMem
#define PMOVZXWDRegReg OMR::InstOpCode::PMOVZXWDRegReg
#define PMOVZXWDRegMem OMR::InstOpCode::PMOVZXWDRegMem
#define PMULLWRegReg OMR::InstOpCode::PMULLWRegReg
#define PMULLWRegMem OMR::InstOpCode::PMULLWRegMem
#define PMULLDRegReg OMR::InstOpCode::PMULLDRegReg
#define PMULLDRegMem OMR::InstOpCode::PMULLDRegMem
#define PADDBRegReg OMR::InstOpCode::PADDBRegReg
#define PADDBRegMem OMR::InstOpCode::PADDBRegMem
#define PADDWRegReg OMR::InstOpCode::PADDWRegReg
#define PADDWRegMem OMR::InstOpCode::PADDWRegMem
#define PADDDRegReg OMR::InstOpCode::PADDDRegReg
#define PADDDRegMem OMR::InstOpCode::PADDDRegMem
#define PADDQRegReg OMR::InstOpCode::PADDQRegReg
#define PADDQRegMem OMR::InstOpCode::PADDQRegMem
#define PSUBBRegReg OMR::InstOpCode::PSUBBRegReg
#define PSUBBRegMem OMR::InstOpCode::PSUBBRegMem
#define PSUBWRegReg OMR::InstOpCode::PSUBWRegReg
#define PSUBWRegMem OMR::InstOpCode::PSUBWRegMem
#define PSUBDRegReg OMR::InstOpCode::PSUBDRegReg
#define PSUBDRegMem OMR::InstOpCode::PSUBDRegMem
#define PSUBQRegReg OMR::InstOpCode::PSUBQRegReg
#define PSUBQRegMem OMR::InstOpCode::PSUBQRegMem
#define PANDRegReg OMR::InstOpCode::PANDRegReg
#define PANDRegMem OMR::InstOpCode::PANDRegMem
#define PORRegReg OMR::InstOpCode::PORRegReg
#define PORRegMem OMR::InstOpCode::PORRegMem
#define PXORRegReg OMR::InstOpCode::PXORRegReg
#define PXORRegMem OMR::InstOpCode::PXORRegMem
#define PTESTRegReg OMR::InstOpCode::PTESTRegReg
#define PANDNRegReg OMR::InstOpCode::PANDNRegReg
#define PEXTRDRegReg OMR::InstOpCode::PEXTRDRegReg
#define PEXTRQRegReg OMR::InstOpCode::PEXTRQRegReg
#define PSHUFBRegReg OMR::InstOpCode::PSHUFBRegReg
#define PSHUFBRegMem OMR::InstOpCode::PSHUFBRegMem
#define PSHUFDRegRegImm1 OMR::InstOpCode::PSHUFDRegRegImm1
#define PSHUFDRegMemImm1 OMR::InstOpCode::PSHUFDRegMemImm1
#define PSRLDQRegImm1 OMR::InstOpCode::PSRLDQRegImm1
#define PMOVZXxmm18Reg OMR::InstOpCode::PMOVZXxmm18Reg
#define POPCNT4RegReg OMR::InstOpCode::POPCNT4RegReg
#define POPCNT8RegReg OMR::InstOpCode::POPCNT8RegReg
#define PUSHFD OMR::InstOpCode::PUSHFD
#define POPFD OMR::InstOpCode::POPFD
#define POPReg OMR::InstOpCode::POPReg
#define POPMem OMR::InstOpCode::POPMem
#define PUSHImms OMR::InstOpCode::PUSHImms
#define PUSHImm4 OMR::InstOpCode::PUSHImm4
#define PUSHReg OMR::InstOpCode::PUSHReg
#define PUSHRegLong OMR::InstOpCode::PUSHRegLong
#define PUSHMem OMR::InstOpCode::PUSHMem
#define RCL1RegImm1 OMR::InstOpCode::RCL1RegImm1
#define RCL4RegImm1 OMR::InstOpCode::RCL4RegImm1
#define RCR1RegImm1 OMR::InstOpCode::RCR1RegImm1
#define RCR4RegImm1 OMR::InstOpCode::RCR4RegImm1
#define REPMOVSB OMR::InstOpCode::REPMOVSB
#define REPMOVSW OMR::InstOpCode::REPMOVSW
#define REPMOVSD OMR::InstOpCode::REPMOVSD
#define REPMOVSQ OMR::InstOpCode::REPMOVSQ
#define REPECMPSB OMR::InstOpCode::REPECMPSB
#define REPECMPSW OMR::InstOpCode::REPECMPSW
#define REPECMPSD OMR::InstOpCode::REPECMPSD
#define REPECMPSQ OMR::InstOpCode::REPECMPSQ
#define REPSTOSB OMR::InstOpCode::REPSTOSB
#define REPSTOSW OMR::InstOpCode::REPSTOSW
#define REPSTOSD OMR::InstOpCode::REPSTOSD
#define REPSTOSQ OMR::InstOpCode::REPSTOSQ
#define RET OMR::InstOpCode::RET
#define RETImm2 OMR::InstOpCode::RETImm2
#define ROL8Reg1 OMR::InstOpCode::ROL8Reg1
#define ROL1RegImm1 OMR::InstOpCode::ROL1RegImm1
#define ROL2RegImm1 OMR::InstOpCode::ROL2RegImm1
#define ROL4RegImm1 OMR::InstOpCode::ROL4RegImm1
#define ROL8RegImm1 OMR::InstOpCode::ROL8RegImm1
#define ROL4RegCL OMR::InstOpCode::ROL4RegCL
#define ROL8RegCL OMR::InstOpCode::ROL8RegCL
#define ROR8Reg1 OMR::InstOpCode::ROR8Reg1
#define ROR1RegImm1 OMR::InstOpCode::ROR1RegImm1
#define ROR2RegImm1 OMR::InstOpCode::ROR2RegImm1
#define ROR4RegImm1 OMR::InstOpCode::ROR4RegImm1
#define ROR8RegImm1 OMR::InstOpCode::ROR8RegImm1
#define SAHF OMR::InstOpCode::SAHF
#define SHL1RegImm1 OMR::InstOpCode::SHL1RegImm1
#define SHL1RegCL OMR::InstOpCode::SHL1RegCL
#define SHL2RegImm1 OMR::InstOpCode::SHL2RegImm1
#define SHL2RegCL OMR::InstOpCode::SHL2RegCL
#define SHL4RegImm1 OMR::InstOpCode::SHL4RegImm1
#define SHL8RegImm1 OMR::InstOpCode::SHL8RegImm1
#define SHL4RegCL OMR::InstOpCode::SHL4RegCL
#define SHL8RegCL OMR::InstOpCode::SHL8RegCL
#define SHL1MemImm1 OMR::InstOpCode::SHL1MemImm1
#define SHL1MemCL OMR::InstOpCode::SHL1MemCL
#define SHL2MemImm1 OMR::InstOpCode::SHL2MemImm1
#define SHL2MemCL OMR::InstOpCode::SHL2MemCL
#define SHL4MemImm1 OMR::InstOpCode::SHL4MemImm1
#define SHL8MemImm1 OMR::InstOpCode::SHL8MemImm1
#define SHL4MemCL OMR::InstOpCode::SHL4MemCL
#define SHL8MemCL OMR::InstOpCode::SHL8MemCL
#define SHR1RegImm1 OMR::InstOpCode::SHR1RegImm1
#define SHR1RegCL OMR::InstOpCode::SHR1RegCL
#define SHR2RegImm1 OMR::InstOpCode::SHR2RegImm1
#define SHR2RegCL OMR::InstOpCode::SHR2RegCL
#define SHR4Reg1 OMR::InstOpCode::SHR4Reg1
#define SHR8Reg1 OMR::InstOpCode::SHR8Reg1
#define SHR4RegImm1 OMR::InstOpCode::SHR4RegImm1
#define SHR8RegImm1 OMR::InstOpCode::SHR8RegImm1
#define SHR4RegCL OMR::InstOpCode::SHR4RegCL
#define SHR8RegCL OMR::InstOpCode::SHR8RegCL
#define SHR1MemImm1 OMR::InstOpCode::SHR1MemImm1
#define SHR1MemCL OMR::InstOpCode::SHR1MemCL
#define SHR2MemImm1 OMR::InstOpCode::SHR2MemImm1
#define SHR2MemCL OMR::InstOpCode::SHR2MemCL
#define SHR4MemImm1 OMR::InstOpCode::SHR4MemImm1
#define SHR8MemImm1 OMR::InstOpCode::SHR8MemImm1
#define SHR4MemCL OMR::InstOpCode::SHR4MemCL
#define SHR8MemCL OMR::InstOpCode::SHR8MemCL
#define SAR1RegImm1 OMR::InstOpCode::SAR1RegImm1
#define SAR1RegCL OMR::InstOpCode::SAR1RegCL
#define SAR2RegImm1 OMR::InstOpCode::SAR2RegImm1
#define SAR2RegCL OMR::InstOpCode::SAR2RegCL
#define SAR4RegImm1 OMR::InstOpCode::SAR4RegImm1
#define SAR8RegImm1 OMR::InstOpCode::SAR8RegImm1
#define SAR4RegCL OMR::InstOpCode::SAR4RegCL
#define SAR8RegCL OMR::InstOpCode::SAR8RegCL
#define SAR1MemImm1 OMR::InstOpCode::SAR1MemImm1
#define SAR1MemCL OMR::InstOpCode::SAR1MemCL
#define SAR2MemImm1 OMR::InstOpCode::SAR2MemImm1
#define SAR2MemCL OMR::InstOpCode::SAR2MemCL
#define SAR4MemImm1 OMR::InstOpCode::SAR4MemImm1
#define SAR8MemImm1 OMR::InstOpCode::SAR8MemImm1
#define SAR4MemCL OMR::InstOpCode::SAR4MemCL
#define SAR8MemCL OMR::InstOpCode::SAR8MemCL
#define SBB1AccImm1 OMR::InstOpCode::SBB1AccImm1
#define SBB2AccImm2 OMR::InstOpCode::SBB2AccImm2
#define SBB4AccImm4 OMR::InstOpCode::SBB4AccImm4
#define SBB8AccImm4 OMR::InstOpCode::SBB8AccImm4
#define SBB1RegImm1 OMR::InstOpCode::SBB1RegImm1
#define SBB2RegImm2 OMR::InstOpCode::SBB2RegImm2
#define SBB2RegImms OMR::InstOpCode::SBB2RegImms
#define SBB4RegImm4 OMR::InstOpCode::SBB4RegImm4
#define SBB8RegImm4 OMR::InstOpCode::SBB8RegImm4
#define SBB4RegImms OMR::InstOpCode::SBB4RegImms
#define SBB8RegImms OMR::InstOpCode::SBB8RegImms
#define SBB1MemImm1 OMR::InstOpCode::SBB1MemImm1
#define SBB2MemImm2 OMR::InstOpCode::SBB2MemImm2
#define SBB2MemImms OMR::InstOpCode::SBB2MemImms
#define SBB4MemImm4 OMR::InstOpCode::SBB4MemImm4
#define SBB8MemImm4 OMR::InstOpCode::SBB8MemImm4
#define SBB4MemImms OMR::InstOpCode::SBB4MemImms
#define SBB8MemImms OMR::InstOpCode::SBB8MemImms
#define SBB1RegReg OMR::InstOpCode::SBB1RegReg
#define SBB2RegReg OMR::InstOpCode::SBB2RegReg
#define SBB4RegReg OMR::InstOpCode::SBB4RegReg
#define SBB8RegReg OMR::InstOpCode::SBB8RegReg
#define SBB1RegMem OMR::InstOpCode::SBB1RegMem
#define SBB2RegMem OMR::InstOpCode::SBB2RegMem
#define SBB4RegMem OMR::InstOpCode::SBB4RegMem
#define SBB8RegMem OMR::InstOpCode::SBB8RegMem
#define SBB1MemReg OMR::InstOpCode::SBB1MemReg
#define SBB2MemReg OMR::InstOpCode::SBB2MemReg
#define SBB4MemReg OMR::InstOpCode::SBB4MemReg
#define SBB8MemReg OMR::InstOpCode::SBB8MemReg
#define SETA1Reg OMR::InstOpCode::SETA1Reg
#define SETAE1Reg OMR::InstOpCode::SETAE1Reg
#define SETB1Reg OMR::InstOpCode::SETB1Reg
#define SETBE1Reg OMR::InstOpCode::SETBE1Reg
#define SETE1Reg OMR::InstOpCode::SETE1Reg
#define SETNE1Reg OMR::InstOpCode::SETNE1Reg
#define SETG1Reg OMR::InstOpCode::SETG1Reg
#define SETGE1Reg OMR::InstOpCode::SETGE1Reg
#define SETL1Reg OMR::InstOpCode::SETL1Reg
#define SETLE1Reg OMR::InstOpCode::SETLE1Reg
#define SETS1Reg OMR::InstOpCode::SETS1Reg
#define SETNS1Reg OMR::InstOpCode::SETNS1Reg
#define SETPO1Reg OMR::InstOpCode::SETPO1Reg
#define SETPE1Reg OMR::InstOpCode::SETPE1Reg
#define SETA1Mem OMR::InstOpCode::SETA1Mem
#define SETAE1Mem OMR::InstOpCode::SETAE1Mem
#define SETB1Mem OMR::InstOpCode::SETB1Mem
#define SETBE1Mem OMR::InstOpCode::SETBE1Mem
#define SETE1Mem OMR::InstOpCode::SETE1Mem
#define SETNE1Mem OMR::InstOpCode::SETNE1Mem
#define SETG1Mem OMR::InstOpCode::SETG1Mem
#define SETGE1Mem OMR::InstOpCode::SETGE1Mem
#define SETL1Mem OMR::InstOpCode::SETL1Mem
#define SETLE1Mem OMR::InstOpCode::SETLE1Mem
#define SETS1Mem OMR::InstOpCode::SETS1Mem
#define SETNS1Mem OMR::InstOpCode::SETNS1Mem
#define SHLD4RegRegImm1 OMR::InstOpCode::SHLD4RegRegImm1
#define SHLD4RegRegCL OMR::InstOpCode::SHLD4RegRegCL
#define SHLD4MemRegImm1 OMR::InstOpCode::SHLD4MemRegImm1
#define SHLD4MemRegCL OMR::InstOpCode::SHLD4MemRegCL
#define SHRD4RegRegImm1 OMR::InstOpCode::SHRD4RegRegImm1
#define SHRD4RegRegCL OMR::InstOpCode::SHRD4RegRegCL
#define SHRD4MemRegImm1 OMR::InstOpCode::SHRD4MemRegImm1
#define SHRD4MemRegCL OMR::InstOpCode::SHRD4MemRegCL
#define STC OMR::InstOpCode::STC
#define STD OMR::InstOpCode::STD
#define STOSB OMR::InstOpCode::STOSB
#define STOSW OMR::InstOpCode::STOSW
#define STOSD OMR::InstOpCode::STOSD
#define STOSQ OMR::InstOpCode::STOSQ
#define SUB1AccImm1 OMR::InstOpCode::SUB1AccImm1
#define SUB2AccImm2 OMR::InstOpCode::SUB2AccImm2
#define SUB4AccImm4 OMR::InstOpCode::SUB4AccImm4
#define SUB8AccImm4 OMR::InstOpCode::SUB8AccImm4
#define SUB1RegImm1 OMR::InstOpCode::SUB1RegImm1
#define SUB2RegImm2 OMR::InstOpCode::SUB2RegImm2
#define SUB2RegImms OMR::InstOpCode::SUB2RegImms
#define SUB4RegImm4 OMR::InstOpCode::SUB4RegImm4
#define SUB8RegImm4 OMR::InstOpCode::SUB8RegImm4
#define SUB4RegImms OMR::InstOpCode::SUB4RegImms
#define SUB8RegImms OMR::InstOpCode::SUB8RegImms
#define SUB1MemImm1 OMR::InstOpCode::SUB1MemImm1
#define SUB2MemImm2 OMR::InstOpCode::SUB2MemImm2
#define SUB2MemImms OMR::InstOpCode::SUB2MemImms
#define SUB4MemImm4 OMR::InstOpCode::SUB4MemImm4
#define SUB8MemImm4 OMR::InstOpCode::SUB8MemImm4
#define SUB4MemImms OMR::InstOpCode::SUB4MemImms
#define SUB8MemImms OMR::InstOpCode::SUB8MemImms
#define SUB1RegReg OMR::InstOpCode::SUB1RegReg
#define SUB2RegReg OMR::InstOpCode::SUB2RegReg
#define SUB4RegReg OMR::InstOpCode::SUB4RegReg
#define SUB8RegReg OMR::InstOpCode::SUB8RegReg
#define SUB1RegMem OMR::InstOpCode::SUB1RegMem
#define SUB2RegMem OMR::InstOpCode::SUB2RegMem
#define SUB4RegMem OMR::InstOpCode::SUB4RegMem
#define SUB8RegMem OMR::InstOpCode::SUB8RegMem
#define SUB1MemReg OMR::InstOpCode::SUB1MemReg
#define SUB2MemReg OMR::InstOpCode::SUB2MemReg
#define SUB4MemReg OMR::InstOpCode::SUB4MemReg
#define SUB8MemReg OMR::InstOpCode::SUB8MemReg
#define SUBSSRegReg OMR::InstOpCode::SUBSSRegReg
#define SUBSSRegMem OMR::InstOpCode::SUBSSRegMem
#define SUBPSRegReg OMR::InstOpCode::SUBPSRegReg
#define SUBPSRegMem OMR::InstOpCode::SUBPSRegMem
#define SUBSDRegReg OMR::InstOpCode::SUBSDRegReg
#define SUBSDRegMem OMR::InstOpCode::SUBSDRegMem
#define SUBPDRegReg OMR::InstOpCode::SUBPDRegReg
#define SUBPDRegMem OMR::InstOpCode::SUBPDRegMem
#define TEST1AccImm1 OMR::InstOpCode::TEST1AccImm1
#define TEST1AccHImm1 OMR::InstOpCode::TEST1AccHImm1
#define TEST2AccImm2 OMR::InstOpCode::TEST2AccImm2
#define TEST4AccImm4 OMR::InstOpCode::TEST4AccImm4
#define TEST8AccImm4 OMR::InstOpCode::TEST8AccImm4
#define TEST1RegImm1 OMR::InstOpCode::TEST1RegImm1
#define TEST2RegImm2 OMR::InstOpCode::TEST2RegImm2
#define TEST4RegImm4 OMR::InstOpCode::TEST4RegImm4
#define TEST8RegImm4 OMR::InstOpCode::TEST8RegImm4
#define TEST1MemImm1 OMR::InstOpCode::TEST1MemImm1
#define TEST2MemImm2 OMR::InstOpCode::TEST2MemImm2
#define TEST4MemImm4 OMR::InstOpCode::TEST4MemImm4
#define TEST8MemImm4 OMR::InstOpCode::TEST8MemImm4
#define TEST1RegReg OMR::InstOpCode::TEST1RegReg
#define TEST2RegReg OMR::InstOpCode::TEST2RegReg
#define TEST4RegReg OMR::InstOpCode::TEST4RegReg
#define TEST8RegReg OMR::InstOpCode::TEST8RegReg
#define TEST1MemReg OMR::InstOpCode::TEST1MemReg
#define TEST2MemReg OMR::InstOpCode::TEST2MemReg
#define TEST4MemReg OMR::InstOpCode::TEST4MemReg
#define TEST8MemReg OMR::InstOpCode::TEST8MemReg
#define XABORT OMR::InstOpCode::XABORT
#define XBEGIN2 OMR::InstOpCode::XBEGIN2
#define XBEGIN4 OMR::InstOpCode::XBEGIN4
#define XCHG2AccReg OMR::InstOpCode::XCHG2AccReg
#define XCHG4AccReg OMR::InstOpCode::XCHG4AccReg
#define XCHG8AccReg OMR::InstOpCode::XCHG8AccReg
#define XCHG1RegReg OMR::InstOpCode::XCHG1RegReg
#define XCHG2RegReg OMR::InstOpCode::XCHG2RegReg
#define XCHG4RegReg OMR::InstOpCode::XCHG4RegReg
#define XCHG8RegReg OMR::InstOpCode::XCHG8RegReg
#define XCHG1RegMem OMR::InstOpCode::XCHG1RegMem
#define XCHG2RegMem OMR::InstOpCode::XCHG2RegMem
#define XCHG4RegMem OMR::InstOpCode::XCHG4RegMem
#define XCHG8RegMem OMR::InstOpCode::XCHG8RegMem
#define XCHG1MemReg OMR::InstOpCode::XCHG1MemReg
#define XCHG2MemReg OMR::InstOpCode::XCHG2MemReg
#define XCHG4MemReg OMR::InstOpCode::XCHG4MemReg
#define XCHG8MemReg OMR::InstOpCode::XCHG8MemReg
#define XEND OMR::InstOpCode::XEND
#define XOR1AccImm1 OMR::InstOpCode::XOR1AccImm1
#define XOR2AccImm2 OMR::InstOpCode::XOR2AccImm2
#define XOR4AccImm4 OMR::InstOpCode::XOR4AccImm4
#define XOR8AccImm4 OMR::InstOpCode::XOR8AccImm4
#define XOR1RegImm1 OMR::InstOpCode::XOR1RegImm1
#define XOR2RegImm2 OMR::InstOpCode::XOR2RegImm2
#define XOR2RegImms OMR::InstOpCode::XOR2RegImms
#define XOR4RegImm4 OMR::InstOpCode::XOR4RegImm4
#define XOR8RegImm4 OMR::InstOpCode::XOR8RegImm4
#define XOR4RegImms OMR::InstOpCode::XOR4RegImms
#define XOR8RegImms OMR::InstOpCode::XOR8RegImms
#define XOR1MemImm1 OMR::InstOpCode::XOR1MemImm1
#define XOR2MemImm2 OMR::InstOpCode::XOR2MemImm2
#define XOR2MemImms OMR::InstOpCode::XOR2MemImms
#define XOR4MemImm4 OMR::InstOpCode::XOR4MemImm4
#define XOR8MemImm4 OMR::InstOpCode::XOR8MemImm4
#define XOR4MemImms OMR::InstOpCode::XOR4MemImms
#define XOR8MemImms OMR::InstOpCode::XOR8MemImms
#define XOR1RegReg OMR::InstOpCode::XOR1RegReg
#define XOR2RegReg OMR::InstOpCode::XOR2RegReg
#define XOR4RegReg OMR::InstOpCode::XOR4RegReg
#define XOR8RegReg OMR::InstOpCode::XOR8RegReg
#define XOR1RegMem OMR::InstOpCode::XOR1RegMem
#define XOR2RegMem OMR::InstOpCode::XOR2RegMem
#define XOR4RegMem OMR::InstOpCode::XOR4RegMem
#define XOR8RegMem OMR::InstOpCode::XOR8RegMem
#define XOR1MemReg OMR::InstOpCode::XOR1MemReg
#define XOR2MemReg OMR::InstOpCode::XOR2MemReg
#define XOR4MemReg OMR::InstOpCode::XOR4MemReg
#define XOR8MemReg OMR::InstOpCode::XOR8MemReg
#define XORPSRegReg OMR::InstOpCode::XORPSRegReg
#define XORPSRegMem OMR::InstOpCode::XORPSRegMem
#define XORPDRegReg OMR::InstOpCode::XORPDRegReg
#define MFENCE OMR::InstOpCode::MFENCE
#define LFENCE OMR::InstOpCode::LFENCE
#define SFENCE OMR::InstOpCode::SFENCE
#define PCMPESTRI OMR::InstOpCode::PCMPESTRI
#define PREFETCHNTA OMR::InstOpCode::PREFETCHNTA
#define PREFETCHT0 OMR::InstOpCode::PREFETCHT0
#define PREFETCHT1 OMR::InstOpCode::PREFETCHT1
#define PREFETCHT2 OMR::InstOpCode::PREFETCHT2
#define ANDNPSRegReg OMR::InstOpCode::ANDNPSRegReg
#define ANDNPDRegReg OMR::InstOpCode::ANDNPDRegReg
#define PSLLQRegImm1 OMR::InstOpCode::PSLLQRegImm1
#define PSRLQRegImm1 OMR::InstOpCode::PSRLQRegImm1
#define VPERM2I128RegRegImm1 OMR::InstOpCode::VPERM2I128RegRegImm1
#define VFMADD132SSRegRegReg OMR::InstOpCode::VFMADD132SSRegRegReg
#define VFMADD132SSRegRegMem OMR::InstOpCode::VFMADD132SSRegRegMem
#define VFMADD213SSRegRegReg OMR::InstOpCode::VFMADD213SSRegRegReg
#define VFMADD213SSRegRegMem OMR::InstOpCode::VFMADD213SSRegRegMem
#define VFMADD231SSRegRegReg OMR::InstOpCode::VFMADD231SSRegRegReg
#define VFMADD231SSRegRegMem OMR::InstOpCode::VFMADD231SSRegRegMem
#define VFMADD132SDRegRegReg OMR::InstOpCode::VFMADD132SDRegRegReg
#define VFMADD132SDRegRegMem OMR::InstOpCode::VFMADD132SDRegRegMem
#define VFMADD213SDRegRegReg OMR::InstOpCode::VFMADD213SDRegRegReg
#define VFMADD213SDRegRegMem OMR::InstOpCode::VFMADD213SDRegRegMem
#define VFMADD231SDRegRegReg OMR::InstOpCode::VFMADD231SDRegRegReg
#define VFMADD231SDRegRegMem OMR::InstOpCode::VFMADD231SDRegRegMem
#define VFMSUB132SSRegRegReg OMR::InstOpCode::VFMSUB132SSRegRegReg
#define VFMSUB132SSRegRegMem OMR::InstOpCode::VFMSUB132SSRegRegMem
#define VFMSUB213SSRegRegReg OMR::InstOpCode::VFMSUB213SSRegRegReg
#define VFMSUB213SSRegRegMem OMR::InstOpCode::VFMSUB213SSRegRegMem
#define VFMSUB231SSRegRegReg OMR::InstOpCode::VFMSUB231SSRegRegReg
#define VFMSUB231SSRegRegMem OMR::InstOpCode::VFMSUB231SSRegRegMem
#define VFMSUB132SDRegRegReg OMR::InstOpCode::VFMSUB132SDRegRegReg
#define VFMSUB132SDRegRegMem OMR::InstOpCode::VFMSUB132SDRegRegMem