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BinaryEvaluator.cpp
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BinaryEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2018, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include "codegen/ARM64Instruction.hpp"
#include "codegen/ARM64ShiftCode.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/CodeGeneratorUtils.hpp"
#include "codegen/GenerateInstructions.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "il/AutomaticSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "infra/Bit.hpp"
/**
* Generic helper that handles a number of similar binary operations.
* @param[in] node : calling node
* @param[in] regOp : the target AArch64 instruction opcode
* @param[in] regOpImm : the matching AArch64 immediate instruction opcode
* regOpImm == regOp indicates that the passed opcode has no immediate form.
* @param[in] cg : codegenerator
* @return target register
*/
static inline TR::Register *
genericBinaryEvaluator(TR::Node *node, TR::InstOpCode::Mnemonic regOp, TR::InstOpCode::Mnemonic regOpImm, bool is64Bit, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = NULL;
TR::Register *trgReg = NULL;
int64_t value = 0;
if (node->getOpCodeValue() != TR::aladd)
{
if(1 == firstChild->getReferenceCount())
{
trgReg = src1Reg;
}
else if(1 == secondChild->getReferenceCount() && secondChild->getRegister() != NULL)
{
trgReg = secondChild->getRegister();
}
else
{
trgReg = cg->allocateRegister();
}
}
else
{
/*
* Because trgReg can contain an internal pointer, we cannot use the same virtual register
* for trgReg and sources for aladd except for the case
* where src1Reg also contains an internal pointer and has the same pinning array as the node.
*/
if ((1 == firstChild->getReferenceCount()) && node->isInternalPointer() && src1Reg->containsInternalPointer() &&
(node->getPinningArrayPointer() == src1Reg->getPinningArrayPointer()))
{
trgReg = src1Reg;
}
else
{
trgReg = cg->allocateRegister();
}
}
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
if(is64Bit)
{
value = secondChild->getLongInt();
}
else
{
value = secondChild->getInt();
}
/* When regOp == regOpImm, an immediate version of the instruction does not exist. */
if(constantIsUnsignedImm12(value) && regOp != regOpImm)
{
generateTrg1Src1ImmInstruction(cg, regOpImm, node, trgReg, src1Reg, value);
}
else if (constantIsUnsignedImm12(-value) &&
(regOpImm == TR::InstOpCode::addimmw || regOpImm == TR::InstOpCode::addimmx ||
regOpImm == TR::InstOpCode::subimmw || regOpImm == TR::InstOpCode::subimmx))
{
TR::InstOpCode::Mnemonic negatedOp;
switch (regOpImm)
{
case TR::InstOpCode::addimmw:
negatedOp = TR::InstOpCode::subimmw;
break;
case TR::InstOpCode::addimmx:
negatedOp = TR::InstOpCode::subimmx;
break;
case TR::InstOpCode::subimmw:
negatedOp = TR::InstOpCode::addimmw;
break;
case TR::InstOpCode::subimmx:
negatedOp = TR::InstOpCode::addimmx;
break;
default:
TR_ASSERT(false, "Unsupported op");
}
generateTrg1Src1ImmInstruction(cg, negatedOp, node, trgReg, src1Reg, -value);
}
else
{
src2Reg = cg->allocateRegister();
if(is64Bit)
{
loadConstant64(cg, node, value, src2Reg);
}
else
{
loadConstant32(cg, node, value, src2Reg);
}
generateTrg1Src2Instruction(cg, regOp, node, trgReg, src1Reg, src2Reg);
cg->stopUsingRegister(src2Reg);
}
}
else
{
src2Reg = cg->evaluate(secondChild);
generateTrg1Src2Instruction(cg, regOp, node, trgReg, src1Reg, src2Reg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
// multiply and add
// multiply and subtract
static TR::Register *
generateMaddOrMsub(TR::Node *node, TR::Node *mulNode, TR::Node *anotherNode, TR::InstOpCode::Mnemonic op, TR::CodeGenerator *cg)
{
if ((mulNode->getOpCodeValue() == TR::imul || mulNode->getOpCodeValue() == TR::lmul) &&
mulNode->getReferenceCount() == 1 &&
mulNode->getRegister() == NULL)
{
TR::Register *trgReg = cg->allocateRegister();
TR::Register *mulSrc1Reg = cg->evaluate(mulNode->getFirstChild());
TR::Register *mulSrc2Reg = cg->evaluate(mulNode->getSecondChild());
TR::Register *src3Reg = cg->evaluate(anotherNode);
generateTrg1Src3Instruction(cg, op, node, trgReg, mulSrc1Reg, mulSrc2Reg, src3Reg);
node->setRegister(trgReg);
cg->decReferenceCount(mulNode->getFirstChild());
cg->decReferenceCount(mulNode->getSecondChild());
cg->decReferenceCount(mulNode);
cg->decReferenceCount(anotherNode);
return trgReg;
}
else
{
return NULL; // not applicable
}
}
/**
* @brief Generates add (shifted register) or sub (shifted register) instruction if possible
*
* @param[in] node: node
* @param[in] op: mnemonic for this node
* @param[in] cg: code generator
*
* @return register which contains the result of the operation. NULL if the operation cannot be encoded in add or sub shifted register instruction.
*/
static TR::Register *
generateAddOrSubShifted(TR::Node *node, TR::InstOpCode::Mnemonic op, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Node *source1Node = NULL;
TR::Node *source2Node = NULL;
TR::Node *shiftNode = NULL;
int32_t shiftValue;
if ((!firstChild->getOpCode().isLoadConst()) &&
(secondChild->getReferenceCount() == 1) &&
(secondChild->getRegister() == NULL) &&
secondChild->getOpCode().isShift() &&
(secondChild->getSecondChild()->getOpCodeValue() == TR::iconst))
{
source1Node = firstChild;
source2Node = secondChild->getFirstChild();
shiftValue = secondChild->getSecondChild()->getInt();
shiftNode = secondChild;
}
else if (node->getOpCode().isAdd() &&
(!secondChild->getOpCode().isLoadConst()) &&
(firstChild->getReferenceCount() == 1) &&
(firstChild->getRegister() == NULL) &&
firstChild->getOpCode().isShift() &&
(firstChild->getSecondChild()->getOpCodeValue() == TR::iconst))
{
source1Node = secondChild;
source2Node = firstChild->getFirstChild();
shiftValue = firstChild->getSecondChild()->getInt();
shiftNode = firstChild;
}
else
{
return NULL;
}
const bool is64bit = node->getDataType().isInt64();
if ((shiftValue <= 0) || (shiftValue > (is64bit ? 63 : 31)))
{
return NULL;
}
TR::Register *treg;
TR::Register *s1reg = cg->evaluate(source1Node);
TR::Register *s2reg = cg->evaluate(source2Node);
if (node->getOpCodeValue() != TR::aladd)
{
if (source1Node->getReferenceCount() == 1)
{
treg = s1reg;
}
else if (source2Node->getReferenceCount() == 1)
{
treg = s2reg;
}
else
{
treg = cg->allocateRegister();
}
}
else
{
/*
* Because treg can contain an internal pointer, we cannot use the same virtual register
* for treg and sources for aladd except for the case
* where s1reg also contains an internal pointer and has the same pinning array as the node.
*/
if ((1 == source1Node->getReferenceCount()) && node->isInternalPointer() && s1reg->containsInternalPointer() &&
(node->getPinningArrayPointer() == s1reg->getPinningArrayPointer()))
{
treg = s1reg;
}
else
{
treg = cg->allocateRegister();
}
}
TR::ARM64ShiftCode code = (shiftNode->getOpCode().isLeftShift() ? TR::SH_LSL : (shiftNode->getOpCode().isShiftLogical() ? TR::SH_LSR : TR::SH_ASR));
generateTrg1Src2ShiftedInstruction(cg, op, node, treg, s1reg, s2reg, code, shiftValue);
node->setRegister(treg);
cg->recursivelyDecReferenceCount(shiftNode);
cg->decReferenceCount(source1Node);
return treg;
}
TR::Register *
OMR::ARM64::TreeEvaluator::iaddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *retReg;
retReg = generateMaddOrMsub(node, firstChild, secondChild, TR::InstOpCode::maddw, cg); // x*y + z
if (retReg)
{
return retReg;
}
retReg = generateMaddOrMsub(node, secondChild, firstChild, TR::InstOpCode::maddw, cg); // x + y*z
if (retReg)
{
return retReg;
}
retReg = generateAddOrSubShifted(node, TR::InstOpCode::addw, cg);
if (retReg)
{
return retReg;
}
return genericBinaryEvaluator(node, TR::InstOpCode::addw, TR::InstOpCode::addimmw, false, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::laddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *retReg;
retReg = generateMaddOrMsub(node, firstChild, secondChild, TR::InstOpCode::maddx, cg); // x*y + z
if (retReg)
{
return retReg;
}
retReg = generateMaddOrMsub(node, secondChild, firstChild, TR::InstOpCode::maddx, cg); // x + y*z
if (retReg)
{
return retReg;
}
retReg = generateAddOrSubShifted(node, TR::InstOpCode::addx, cg);
if (retReg)
{
return retReg;
}
return genericBinaryEvaluator(node, TR::InstOpCode::addx, TR::InstOpCode::addimmx, true, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::isubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *retReg;
retReg = generateMaddOrMsub(node, secondChild, firstChild, TR::InstOpCode::msubw, cg); // x - y*z
if (retReg)
{
return retReg;
}
retReg = generateAddOrSubShifted(node, TR::InstOpCode::subw, cg);
if (retReg)
{
return retReg;
}
return genericBinaryEvaluator(node, TR::InstOpCode::subw, TR::InstOpCode::subimmw, false, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::lsubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *retReg;
retReg = generateMaddOrMsub(node, secondChild, firstChild, TR::InstOpCode::msubx, cg); // x - y*z
if (retReg)
{
return retReg;
}
retReg = generateAddOrSubShifted(node, TR::InstOpCode::subx, cg);
if (retReg)
{
return retReg;
}
return genericBinaryEvaluator(node, TR::InstOpCode::subx, TR::InstOpCode::subimmx, true, cg);
}
// vector add
static TR::Register *
inlineVectorBinaryOp(TR::Node *node, TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *lhsReg = NULL, *rhsReg = NULL;
lhsReg = cg->evaluate(firstChild);
rhsReg = cg->evaluate(secondChild);
TR_ASSERT(lhsReg->getKind() == TR_VRF, "unexpected Register kind");
TR_ASSERT(rhsReg->getKind() == TR_VRF, "unexpected Register kind");
TR::Register *resReg = cg->allocateRegister(TR_VRF);
node->setRegister(resReg);
generateTrg1Src2Instruction(cg, op, node, resReg, lhsReg, rhsReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return resReg;
}
TR::Register *
OMR::ARM64::TreeEvaluator::vaddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::InstOpCode::Mnemonic addOp;
switch(node->getDataType())
{
case TR::VectorInt8:
addOp = TR::InstOpCode::vadd16b;
break;
case TR::VectorInt16:
addOp = TR::InstOpCode::vadd8h;
break;
case TR::VectorInt32:
addOp = TR::InstOpCode::vadd4s;
break;
case TR::VectorInt64:
addOp = TR::InstOpCode::vadd2d;
break;
case TR::VectorFloat:
addOp = TR::InstOpCode::vfadd4s;
break;
case TR::VectorDouble:
addOp = TR::InstOpCode::vfadd2d;
break;
default:
TR_ASSERT(false, "unrecognized vector type %s", node->getDataType().toString());
return NULL;
}
return inlineVectorBinaryOp(node, cg, addOp);
}
TR::Register *
OMR::ARM64::TreeEvaluator::vsubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::InstOpCode::Mnemonic subOp;
switch(node->getDataType())
{
case TR::VectorInt8:
subOp = TR::InstOpCode::vsub16b;
break;
case TR::VectorInt16:
subOp = TR::InstOpCode::vsub8h;
break;
case TR::VectorInt32:
subOp = TR::InstOpCode::vsub4s;
break;
case TR::VectorInt64:
subOp = TR::InstOpCode::vsub2d;
break;
case TR::VectorFloat:
subOp = TR::InstOpCode::vfsub4s;
break;
case TR::VectorDouble:
subOp = TR::InstOpCode::vfsub2d;
break;
default:
TR_ASSERT(false, "unrecognized vector type %s", node->getDataType().toString());
return NULL;
}
return inlineVectorBinaryOp(node, cg, subOp);
}
TR::Register *
OMR::ARM64::TreeEvaluator::vmulEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::InstOpCode::Mnemonic mulOp;
switch(node->getDataType())
{
case TR::VectorInt8:
mulOp = TR::InstOpCode::vmul16b;
break;
case TR::VectorInt16:
mulOp = TR::InstOpCode::vmul8h;
break;
case TR::VectorInt32:
mulOp = TR::InstOpCode::vmul4s;
break;
case TR::VectorFloat:
mulOp = TR::InstOpCode::vfmul4s;
break;
case TR::VectorDouble:
mulOp = TR::InstOpCode::vfmul2d;
break;
default:
TR_ASSERT(false, "unrecognized vector type %s", node->getDataType().toString());
return NULL;
}
return inlineVectorBinaryOp(node, cg, mulOp);
}
TR::Register *
OMR::ARM64::TreeEvaluator::vdivEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::InstOpCode::Mnemonic divOp;
switch(node->getDataType())
{
case TR::VectorFloat:
divOp = TR::InstOpCode::vfdiv4s;
break;
case TR::VectorDouble:
divOp = TR::InstOpCode::vfdiv2d;
break;
default:
TR_ASSERT(false, "unrecognized vector type %s", node->getDataType().toString());
return NULL;
}
return inlineVectorBinaryOp(node, cg, divOp);
}
TR::Register *
OMR::ARM64::TreeEvaluator::vandEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::InstOpCode::Mnemonic andOp;
switch(node->getDataType())
{
case TR::VectorInt8:
andOp = TR::InstOpCode::vand16b;
break;
default:
TR_ASSERT(false, "unrecognized vector type %s", node->getDataType().toString());
return NULL;
}
return inlineVectorBinaryOp(node, cg, andOp);
}
TR::Register *
OMR::ARM64::TreeEvaluator::vorEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::InstOpCode::Mnemonic orrOp;
switch(node->getDataType())
{
case TR::VectorInt8:
orrOp = TR::InstOpCode::vorr16b;
break;
default:
TR_ASSERT(false, "unrecognized vector type %s", node->getDataType().toString());
return NULL;
}
return inlineVectorBinaryOp(node, cg, orrOp);
}
TR::Register *
OMR::ARM64::TreeEvaluator::vxorEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::InstOpCode::Mnemonic xorOp;
switch(node->getDataType())
{
case TR::VectorInt8:
xorOp = TR::InstOpCode::veor16b;
break;
default:
TR_ASSERT(false, "unrecognized vector type %s", node->getDataType().toString());
return NULL;
}
return inlineVectorBinaryOp(node, cg, xorOp);
}
// Multiply a register by a 32-bit constant
static void mulConstant32(TR::Node *node, TR::Register *treg, TR::Register *sreg, int32_t value, TR::CodeGenerator *cg)
{
if (value == 0)
{
loadConstant32(cg, node, 0, treg);
}
else if (value == 1)
{
generateMovInstruction(cg, node, treg, sreg);
}
else if (value == -1)
{
generateNegInstruction(cg, node, treg, sreg);
}
else
{
TR::Register *tmpReg = cg->allocateRegister();
loadConstant32(cg, node, value, tmpReg);
generateMulInstruction(cg, node, treg, sreg, tmpReg);
cg->stopUsingRegister(tmpReg);
}
}
// Multiply a register by a 64-bit constant
static void mulConstant64(TR::Node *node, TR::Register *treg, TR::Register *sreg, int64_t value, TR::CodeGenerator *cg)
{
if (value == 0)
{
loadConstant64(cg, node, 0, treg);
}
else if (value == 1)
{
generateMovInstruction(cg, node, treg, sreg);
}
else if (value == -1)
{
generateNegInstruction(cg, node, treg, sreg);
}
else
{
TR::Register *tmpReg = cg->allocateRegister();
loadConstant64(cg, node, value, tmpReg);
generateMulInstruction(cg, node, treg, sreg, tmpReg);
cg->stopUsingRegister(tmpReg);
}
}
TR::Register *
OMR::ARM64::TreeEvaluator::imulEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = NULL;
TR::Register *trgReg = NULL;
int32_t value = 0;
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
value = secondChild->getInt();
if (value > 0 && cg->convertMultiplyToShift(node))
{
trgReg = cg->evaluate(node);
return trgReg;
}
}
if(1 == firstChild->getReferenceCount())
{
trgReg = src1Reg;
}
else if(1 == secondChild->getReferenceCount() && (src2Reg = secondChild->getRegister()) != NULL)
{
trgReg = src2Reg;
}
else
{
trgReg = cg->allocateRegister();
}
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
mulConstant32(node, trgReg, src1Reg, value, cg);
}
else
{
TR::Register *src2Reg = cg->evaluate(secondChild);
generateMulInstruction(cg, node, trgReg, src1Reg, src2Reg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
TR::Register *
OMR::ARM64::TreeEvaluator::imulhEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Node *secondChild = node->getSecondChild();
TR::Register *src2Reg;
TR::Register *trgReg = cg->allocateRegister();
TR::Register *tmpReg = NULL;
TR::Register *zeroReg = cg->allocateRegister();
TR::RegisterDependencyConditions *cond = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(1, 1, cg->trMemory());
TR::addDependency(cond, zeroReg, TR::RealRegister::xzr, TR_GPR, cg);
// imulh is generated for constant idiv and the second child is the magic number
// assume magic number is usually a large odd number with little optimization opportunity
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
int32_t value = secondChild->getInt();
src2Reg = tmpReg = cg->allocateRegister();
loadConstant32(cg, node, value, src2Reg);
}
else
{
src2Reg = cg->evaluate(secondChild);
}
generateTrg1Src3Instruction(cg, TR::InstOpCode::smaddl, node, trgReg, src1Reg, src2Reg, zeroReg, cond);
cg->stopUsingRegister(zeroReg);
/* logical shift right by 32 bits */
uint32_t imm = 0x183F; // N=1, immr=32, imms=63
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::ubfmx, node, trgReg, trgReg, imm);
if (tmpReg)
{
cg->stopUsingRegister(tmpReg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
TR::Register *
OMR::ARM64::TreeEvaluator::lmulEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = NULL;
TR::Register *trgReg = NULL;
int64_t value = 0;
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
value = secondChild->getLongInt();
if (value > 0 && cg->convertMultiplyToShift(node))
{
trgReg = cg->evaluate(node);
return trgReg;
}
}
if(1 == firstChild->getReferenceCount())
{
trgReg = src1Reg;
}
else if(1 == secondChild->getReferenceCount() && (src2Reg = secondChild->getRegister()) != NULL)
{
trgReg = src2Reg;
}
else
{
trgReg = cg->allocateRegister();
}
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
mulConstant64(node, trgReg, src1Reg, value, cg);
}
else
{
TR::Register *src2Reg = cg->evaluate(secondChild);
generateMulInstruction(cg, node, trgReg, src1Reg, src2Reg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
static TR::Register *idivHelper(TR::Node *node, bool is64bit, TR::CodeGenerator *cg)
{
// TODO: Add checks for special cases
TR::Node *firstChild = node->getFirstChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Node *secondChild = node->getSecondChild();
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::Register *trgReg = cg->allocateRegister();
generateTrg1Src2Instruction(cg, is64bit ? TR::InstOpCode::sdivx : TR::InstOpCode::sdivw, node, trgReg, src1Reg, src2Reg);
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
static TR::Register *iremHelper(TR::Node *node, bool is64bit, TR::CodeGenerator *cg)
{
// TODO: Add checks for special cases
TR::Node *firstChild = node->getFirstChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Node *secondChild = node->getSecondChild();
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::Register *tmpReg = cg->allocateRegister();
TR::Register *trgReg = cg->allocateRegister();
generateTrg1Src2Instruction(cg, is64bit ? TR::InstOpCode::sdivx : TR::InstOpCode::sdivw, node, tmpReg, src1Reg, src2Reg);
generateTrg1Src3Instruction(cg, is64bit ? TR::InstOpCode::msubx : TR::InstOpCode::msubw, node, trgReg, tmpReg, src2Reg, src1Reg);
cg->stopUsingRegister(tmpReg);
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
TR::Register *
OMR::ARM64::TreeEvaluator::lmulhEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Node *secondChild = node->getSecondChild();
TR::Register *src2Reg;
TR::Register *trgReg = cg->allocateRegister();
TR::Register *tmpReg = NULL;
// lmulh is generated for constant ldiv and the second child is the magic number
// assume magic number is usually a large odd number with little optimization opportunity
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
int64_t value = secondChild->getLongInt();
src2Reg = tmpReg = cg->allocateRegister();
loadConstant64(cg, node, value, src2Reg);
}
else
{
src2Reg = cg->evaluate(secondChild);
}
generateTrg1Src2Instruction(cg, TR::InstOpCode::smulh, node, trgReg, src1Reg, src2Reg);
if (tmpReg)
{
cg->stopUsingRegister(tmpReg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
TR::Register *
OMR::ARM64::TreeEvaluator::idivEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return genericBinaryEvaluator(node, TR::InstOpCode::sdivw, TR::InstOpCode::sdivw, false, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::iremEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return iremHelper(node, false, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::ldivEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return genericBinaryEvaluator(node, TR::InstOpCode::sdivx, TR::InstOpCode::sdivx, true, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::lremEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return iremHelper(node, true, cg);
}
static TR::Register *shiftHelper(TR::Node *node, TR::ARM64ShiftCode shiftType, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::ILOpCodes secondOp = secondChild->getOpCodeValue();
TR::Register *srcReg = cg->evaluate(firstChild);
TR::Register *trgReg = cg->allocateRegister();
bool is64bit = node->getDataType().isInt64();
TR::InstOpCode::Mnemonic op;
if (secondOp == TR::iconst)
{
int32_t value = secondChild->getInt();
uint32_t shift = is64bit ? (value & 0x3F) : (value & 0x1F);
switch (shiftType)
{
case TR::SH_LSL:
generateLogicalShiftLeftImmInstruction(cg, node, trgReg, srcReg, shift, is64bit);
break;
case TR::SH_LSR:
generateLogicalShiftRightImmInstruction(cg, node, trgReg, srcReg, shift, is64bit);
break;
case TR::SH_ASR:
generateArithmeticShiftRightImmInstruction(cg, node, trgReg, srcReg, shift, is64bit);
break;
default:
TR_ASSERT(false, "Unsupported shift type.");
}
}
else
{
TR::Register *shiftAmountReg = cg->evaluate(secondChild);
switch (shiftType)
{
case TR::SH_LSL:
op = is64bit ? TR::InstOpCode::lslvx : TR::InstOpCode::lslvw;
break;
case TR::SH_LSR:
op = is64bit ? TR::InstOpCode::lsrvx : TR::InstOpCode::lsrvw;
break;
case TR::SH_ASR:
op = is64bit ? TR::InstOpCode::asrvx : TR::InstOpCode::asrvw;
break;
default:
TR_ASSERT(false, "Unsupported shift type.");
}
generateTrg1Src2Instruction(cg, op, node, trgReg, srcReg, shiftAmountReg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
// also handles lshl
TR::Register *
OMR::ARM64::TreeEvaluator::ishlEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
if (node->getOpCodeValue() == TR::lshl)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
if (firstChild->getOpCodeValue() == TR::i2l &&
firstChild->getRegister() == NULL &&
firstChild->getReferenceCount() == 1 &&
secondChild->getOpCodeValue() == TR::iconst &&
secondChild->getInt() < 32)
{
// Typical IL sequence in array access (sign-extend index value and shift it to left)
TR::Node *indexChild = firstChild->getFirstChild();
TR::Register *srcReg = cg->evaluate(indexChild);
TR::Register *trgReg = (indexChild->getReferenceCount() == 1) ? srcReg : cg->allocateRegister();
int32_t bitsToShift = secondChild->getInt();
int32_t imm = ((64 - bitsToShift) << 6) | 31; // immr = 64 - bitsToShift, imms = 31
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::sbfmx, node, trgReg, srcReg, imm);
node->setRegister(trgReg);
cg->recursivelyDecReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
}
return shiftHelper(node, TR::SH_LSL, cg);
}
// also handles lshr
TR::Register *
OMR::ARM64::TreeEvaluator::ishrEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return shiftHelper(node, TR::SH_ASR, cg);
}
// also handles lushr
TR::Register *
OMR::ARM64::TreeEvaluator::iushrEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return shiftHelper(node, TR::SH_LSR, cg);
}
// also handles lrol
TR::Register *
OMR::ARM64::TreeEvaluator::irolEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *trgReg = cg->gprClobberEvaluate(firstChild);
bool is64bit = node->getDataType().isInt64();
TR::InstOpCode::Mnemonic op;
if (secondChild->getOpCode().isLoadConst())
{
int32_t value = secondChild->getInt();
uint32_t shift = is64bit ? (value & 0x3F) : (value & 0x1F);
if (shift != 0)
{
shift = is64bit ? (64 - shift) : (32 - shift); // change ROL to ROR
op = is64bit ? TR::InstOpCode::extrx : TR::InstOpCode::extrw; // ROR is an alias of EXTR
generateTrg1Src2ShiftedInstruction(cg, op, node, trgReg, trgReg, trgReg, TR::SH_LSL, shift);
}
}
else
{
TR::Register *shiftAmountSrcReg;
TR::Register *shiftAmountReg;
TR::Register *tempReg;
bool useTempReg;
if (secondChild->getOpCode().isNeg() && secondChild->getRegister() == NULL && secondChild->getReferenceCount() == 1)
{
// If the second child is `ineg` and not commoned, cancel out double negation
auto shiftAmountNode = secondChild->getFirstChild();
useTempReg = is64bit && shiftAmountNode->getReferenceCount() > 1;
tempReg = useTempReg ? cg->allocateRegister() : NULL;
shiftAmountSrcReg = cg->evaluate(shiftAmountNode);
shiftAmountReg = useTempReg ? tempReg : shiftAmountSrcReg;
if (is64bit)
{
// 32->64 bit sign extension: SXTW is alias of SBFM
uint32_t imm = 0x1F; // immr=0, imms=31, N bit is pre-encoded in `sbfmx` opcode.
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::sbfmx, node, shiftAmountReg, shiftAmountSrcReg, imm);
}
cg->decReferenceCount(shiftAmountNode);
}
else
{
useTempReg = secondChild->getReferenceCount() > 1;
tempReg = useTempReg ? cg->allocateRegister() : NULL;
shiftAmountSrcReg = cg->evaluate(secondChild);
shiftAmountReg = useTempReg ? tempReg : shiftAmountSrcReg;
generateNegInstruction(cg, node, shiftAmountReg, shiftAmountSrcReg); // change ROL to ROR
if (is64bit)