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ControlFlowEvaluator.cpp
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ControlFlowEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/RecognizedMethods.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "codegen/S390Evaluator.hpp"
#include "compile/Compilation.hpp"
#include "compile/Method.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "compile/VirtualGuard.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "env/CHTable.hpp"
#endif
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/AutomaticSymbol.hpp"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "infra/BitVector.hpp"
#include "infra/List.hpp"
#include "ras/Debug.hpp"
#include "ras/Delimiter.hpp"
#include "z/codegen/BinaryAnalyser.hpp"
#include "z/codegen/BinaryCommutativeAnalyser.hpp"
#include "z/codegen/CompareAnalyser.hpp"
#include "z/codegen/S390GenerateInstructions.hpp"
#include "z/codegen/S390HelperCallSnippet.hpp"
#include "z/codegen/S390Instruction.hpp"
#include "z/codegen/S390OutOfLineCodeSection.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "z/codegen/S390Register.hpp"
#endif
#include "z/codegen/TranslateEvaluator.hpp"
extern TR::Instruction *
generateS390PackedCompareAndBranchOps(TR::Node * node,
TR::CodeGenerator * cg,
TR::InstOpCode::S390BranchCondition fBranchOpCond,
TR::InstOpCode::S390BranchCondition rBranchOpCond,
TR::InstOpCode::S390BranchCondition &retBranchOpCond,
TR::LabelSymbol *branchTarget = NULL);
extern TR::Register *
iDivRemGenericEvaluator(TR::Node * node, TR::CodeGenerator * cg, bool isDivision, TR::MemoryReference * divchkDivisorMR);
TR::InstOpCode::S390BranchCondition generateS390CompareOps(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::S390BranchCondition fBranchOpCond, TR::InstOpCode::S390BranchCondition rBranchOpCond);
TR::Instruction * generateS390CompareOps(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::S390BranchCondition fBranchOpCond, TR::InstOpCode::S390BranchCondition rBranchOpCond, TR::LabelSymbol *branchTarget);
void killRegisterIfNotLocked(TR::CodeGenerator * cg, TR::RealRegister::RegNum reg, TR::Instruction * instr , TR::RegisterDependencyConditions * deps = NULL)
{
TR::Register *dummy = NULL;
if (cg->machine()->getRealRegister(reg)->getState() != TR::RealRegister::Locked)
{
if (deps == NULL)
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
dummy = cg->allocateRegister();
deps->addPostCondition(dummy, TR::RealRegister::GPR4);
dummy->setPlaceholderReg();
instr->setDependencyConditions(deps);
cg->stopUsingRegister(dummy);
}
}
/**
* Helper to generate virtual guard if node is so flagged. In 32 bit mode the NOP instruction,
* a BRC, has only a +ve displacement of 2^12 (4k), and so in some cases it is not safe to use it
* on a G5 platform (no problems with BRCL). At this point, since instructions have not yet
* been generated, there is no good way to guage how far away the label will be, so we cannot
* even determine if it is safe. Will never be enabled for G5 hardware
* Note that some instructions *must* have a virtual guard generated for them.
*/
static bool
virtualGuardHelper(TR::Node * node, TR::CodeGenerator * cg)
{
#ifdef J9_PROJECT_SPECIFIC
if (!cg->willGenerateNOPForVirtualGuard(node))
{
return false;
}
TR::Compilation *comp = cg->comp();
TR_VirtualGuard * virtualGuard = comp->findVirtualGuardInfo(node);
TR_VirtualGuardSite * site = NULL;
if (comp->compileRelocatableCode())
{
site = (TR_VirtualGuardSite *)comp->addAOTNOPSite();
TR_AOTGuardSite *aotSite = (TR_AOTGuardSite *)site;
aotSite->setType(virtualGuard->getKind());
aotSite->setNode(node);
switch (virtualGuard->getKind())
{
case TR_DirectMethodGuard:
case TR_NonoverriddenGuard:
case TR_InterfaceGuard:
case TR_MethodEnterExitGuard:
case TR_HCRGuard:
case TR_AbstractGuard:
case TR_BreakpointGuard:
aotSite->setGuard(virtualGuard);
break;
case TR_ProfiledGuard:
break;
default:
TR_ASSERT_FATAL(0, "got AOT guard in node but virtual guard not one of known guards supported for AOT. Guard: %d", virtualGuard->getKind());
break;
}
}
else if (!node->isSideEffectGuard())
{
TR_VirtualGuard * virtualGuard = comp->findVirtualGuardInfo(node);
site = virtualGuard->addNOPSite();
}
else
{
site = comp->addSideEffectNOPSite();
}
TR::RegisterDependencyConditions * deps;
if (node->getNumChildren() == 3)
{
TR::Node * third = node->getChild(2);
cg->evaluate(third);
deps = generateRegisterDependencyConditions(cg, third, 0);
}
else
{
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions((uint16_t) 0, (uint16_t) 0, cg);
}
if(virtualGuard->shouldGenerateChildrenCode())
cg->evaluateChildrenWithMultipleRefCount(node);
generateVirtualGuardNOPInstruction(cg, node, site, deps, node->getBranchDestination()->getNode()->getLabel());
cg->recursivelyDecReferenceCount(node->getFirstChild());
cg->recursivelyDecReferenceCount(node->getSecondChild());
traceMsg(comp, "virtualGuardHelper for %s %s\n",
comp->getDebug()?comp->getDebug()->getVirtualGuardKindName(virtualGuard->getKind()):"???Guard" , virtualGuard->mergedWithHCRGuard()?"merged with HCRGuard":"");
return true;
#else
return false;
#endif
}
//////////////////////////////////////////////////////////////////////////////////////////////////
// Long Compare Helper code
//
#define CMP4BOOLEAN true
#define CMP4CONTROLFLOW false
static TR::Register *
generateS390lcmpEvaluator64(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic brOp, TR::InstOpCode::S390BranchCondition brCond, bool isBoolean)
{
TR::RegisterDependencyConditions * deps = NULL;
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol(cg);
TR::LabelSymbol * isTrue = generateLabelSymbol(cg);
bool isUnsigned = node->getOpCode().isUnsignedCompare();
TR::Register * targetRegister = cg->allocateRegister();
TR::Node * firstChild = node->getFirstChild();
TR_ASSERT(isBoolean, "Coparison node %p is not boolean\n",node);
// Assume the condition is true.
genLoadLongConstant(cg, node, 1, targetRegister);
TR::Node * secondChild = node->getSecondChild();
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
int64_t long_value = secondChild->getLongInt();
TR::Register * cmpRegister = cg->evaluate(firstChild);
generateS390ImmOp(cg, isUnsigned ? TR::InstOpCode::CLG : TR::InstOpCode::CG, node, cmpRegister, cmpRegister, long_value);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
generateS390BranchInstruction(cg, brOp, brCond, node, isTrue);
}
else
{
// We should use the Binary analyzer here
TR::Node * firstChild = node->getFirstChild();
TR::Register * cmpRegister = cg->evaluate(firstChild);
TR::Register * srcReg = cg->evaluate(secondChild);
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 3, cg);
deps->addPostConditionIfNotAlreadyInserted(cmpRegister,TR::RealRegister::AssignAny);
deps->addPostConditionIfNotAlreadyInserted(srcReg,TR::RealRegister::AssignAny);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
generateS390CompareAndBranchInstruction(cg, isUnsigned ? TR::InstOpCode::CLGR : TR::InstOpCode::CGR, node, cmpRegister, srcReg, brCond, isTrue, false, false);
}
cFlowRegionStart->setStartInternalControlFlow();
deps->addPostConditionIfNotAlreadyInserted(targetRegister,TR::RealRegister::AssignAny);
// FALSE
genLoadLongConstant(cg, node, 0, targetRegister);
// TRUE
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, isTrue, deps);
isTrue->setEndInternalControlFlow();
node->setRegister(targetRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return targetRegister;
}
/**
* Generate code to perform a comparison that returns 1 , -1, or 0
* Handles TR::fcmpl, TR::fcmpg, TR::dcmpl, and TR::dcmpg
*/
TR::Register *
OMR::Z::TreeEvaluator::fcmplEvaluator(TR::Node * node, TR::CodeGenerator * cg)
{
TR::InstOpCode::Mnemonic branchOp;
TR::InstOpCode::S390BranchCondition brCond ;
// Create ICF start label
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol(cg);
// Create a label
TR::LabelSymbol * cFlowRegionEnd = generateLabelSymbol(cg);
// Create a register
TR::Register * targetRegister = cg->allocateRegister();
// Generate compare code, find out if ops were reversed
brCond = generateS390CompareOps(node, cg, TR::InstOpCode::COND_BH, TR::InstOpCode::COND_BL);
branchOp = TR::InstOpCode::BRC;
// Assume A == B, set targetRegister value to 0
// TODO: Can we allow setting the condition code here by moving the load before the compare?
generateLoad32BitConstant(cg, node, 0, targetRegister, false);
// done if A==B
TR::RegisterDependencyConditions *deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
deps->addPostCondition(targetRegister,TR::RealRegister::AssignAny);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BE, node, cFlowRegionEnd);
// Found A != B, assume A > B, set targetRegister value to 1
generateLoad32BitConstant(cg, node, 1, targetRegister, false);
//done if A>B
generateS390BranchInstruction(cg, branchOp, brCond, node, cFlowRegionEnd);
//found either A<B or either of A and B is NaN
//For TR::fcmpg instruction, done if either of A and B is NaN
if (node->getOpCodeValue() == TR::fcmpg || node->getOpCodeValue() == TR::dcmpg)
{
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_MASK1, node, cFlowRegionEnd);
}
//Got here? means either A<B or (TR::fcmpl instruction and (A==NaN || B==NaN))
//set targetRegister value to -1
generateLoad32BitConstant(cg, node, -1, targetRegister, true);
// DONE
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionEnd, deps);
cFlowRegionEnd->setEndInternalControlFlow();
node->setRegister(targetRegister);
return targetRegister;
}
inline TR::InstOpCode::S390BranchCondition
generateS390Compare(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic branchOp, TR::InstOpCode::S390BranchCondition fBranchOpCond, TR::InstOpCode::S390BranchCondition rBranchOpCond)
{
// Generate compare code, find out if ops were reversed
TR::InstOpCode::S390BranchCondition branchOpCond = generateS390CompareOps(node, cg, fBranchOpCond, rBranchOpCond);
return branchOpCond;
}
static TR::Register*
xmaxxminHelper(TR::Node* node, TR::CodeGenerator* cg, TR::InstOpCode::Mnemonic compareRROp, TR::InstOpCode::S390BranchCondition branchCond, TR::InstOpCode::Mnemonic moveRROp)
{
TR::Node* lhsNode = node->getChild(0);
TR::Node* rhsNode = node->getChild(1);
TR::Register* lhsReg = cg->gprClobberEvaluate(lhsNode);
TR::Register* rhsReg = cg->evaluate(rhsNode);
TR::LabelSymbol* cFlowRegionStart = generateLabelSymbol(cg);
TR::LabelSymbol* cFlowRegionEnd = generateLabelSymbol(cg);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateRREInstruction(cg, compareRROp, node, lhsReg, rhsReg);
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, branchCond, node, cFlowRegionEnd);
generateRREInstruction(cg, moveRROp, node, lhsReg, rhsReg);
TR::RegisterDependencyConditions* deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 2, cg);
deps->addPostConditionIfNotAlreadyInserted(lhsReg, TR::RealRegister::AssignAny);
deps->addPostConditionIfNotAlreadyInserted(rhsReg, TR::RealRegister::AssignAny);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionEnd, deps);
cFlowRegionEnd->setEndInternalControlFlow();
node->setRegister(lhsReg);
cg->decReferenceCount(lhsNode);
cg->decReferenceCount(rhsNode);
return lhsReg;
}
static TR::Register*
imaximinHelper(TR::Node* node, TR::CodeGenerator* cg, TR::InstOpCode::Mnemonic compareRROp, TR::InstOpCode::S390BranchCondition branchCond, TR::InstOpCode::Mnemonic moveRROp)
{
if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z15))
{
TR::Node* lhsNode = node->getChild(0);
TR::Node* rhsNode = node->getChild(1);
TR::Register* resultReg = cg->allocateRegister();
TR::Register* lhsReg = cg->evaluate(lhsNode);
TR::Register* rhsReg = cg->evaluate(rhsNode);
generateRRInstruction(cg, TR::InstOpCode::CR, node, lhsReg, rhsReg);
generateRRFInstruction(cg, TR::InstOpCode::SELR, node, resultReg, rhsReg, lhsReg, getMaskForBranchCondition(getReverseBranchCondition(branchCond)));
node->setRegister(resultReg);
cg->decReferenceCount(lhsNode);
cg->decReferenceCount(rhsNode);
return resultReg;
}
else if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z196))
{
TR::Node* lhsNode = node->getChild(0);
TR::Node* rhsNode = node->getChild(1);
TR::Register* lhsReg = cg->gprClobberEvaluate(lhsNode);
TR::Register* rhsReg = cg->evaluate(rhsNode);
generateRRInstruction(cg, TR::InstOpCode::CR, node, lhsReg, rhsReg);
generateRRFInstruction(cg, TR::InstOpCode::LOCR, node, lhsReg, rhsReg, getMaskForBranchCondition(getReverseBranchCondition(branchCond)), true);
node->setRegister(lhsReg);
cg->decReferenceCount(lhsNode);
cg->decReferenceCount(rhsNode);
return lhsReg;
}
else
{
return xmaxxminHelper(node, cg, compareRROp, branchCond, moveRROp);
}
}
static TR::Register*
lmaxlminHelper(TR::Node* node, TR::CodeGenerator* cg, TR::InstOpCode::Mnemonic compareRROp, TR::InstOpCode::S390BranchCondition branchCond, TR::InstOpCode::Mnemonic moveRROp)
{
if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z15))
{
TR::Node* lhsNode = node->getChild(0);
TR::Node* rhsNode = node->getChild(1);
TR::Register* resultReg = cg->allocateRegister();
TR::Register* lhsReg = cg->evaluate(lhsNode);
TR::Register* rhsReg = cg->evaluate(rhsNode);
generateRREInstruction(cg, TR::InstOpCode::CGR, node, lhsReg, rhsReg);
generateRRFInstruction(cg, TR::InstOpCode::SELGR, node, resultReg, rhsReg, lhsReg, getMaskForBranchCondition(getReverseBranchCondition(branchCond)));
node->setRegister(resultReg);
cg->decReferenceCount(lhsNode);
cg->decReferenceCount(rhsNode);
return resultReg;
}
else if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z196))
{
TR::Node* lhsNode = node->getChild(0);
TR::Node* rhsNode = node->getChild(1);
TR::Register* lhsReg = cg->gprClobberEvaluate(lhsNode);
TR::Register* rhsReg = cg->evaluate(rhsNode);
generateRREInstruction(cg, TR::InstOpCode::CGR, node, lhsReg, rhsReg);
generateRRFInstruction(cg, TR::InstOpCode::LOCGR, node, lhsReg, rhsReg, getMaskForBranchCondition(getReverseBranchCondition(branchCond)), true);
node->setRegister(lhsReg);
cg->decReferenceCount(lhsNode);
cg->decReferenceCount(rhsNode);
return lhsReg;
}
else
{
return xmaxxminHelper(node, cg, compareRROp, branchCond, moveRROp);
}
}
TR::Register*
OMR::Z::TreeEvaluator::imaxEvaluator(TR::Node* node, TR::CodeGenerator* cg)
{
return imaximinHelper(node, cg, TR::InstOpCode::CR, TR::InstOpCode::COND_BHR, TR::InstOpCode::LR);
}
TR::Register*
OMR::Z::TreeEvaluator::lmaxEvaluator(TR::Node* node, TR::CodeGenerator* cg)
{
return lmaxlminHelper(node, cg, TR::InstOpCode::CGR, TR::InstOpCode::COND_BHR, TR::InstOpCode::LGR);
}
TR::Register*
OMR::Z::TreeEvaluator::fmaxEvaluator(TR::Node* node, TR::CodeGenerator* cg)
{
return xmaxxminHelper(node, cg, TR::InstOpCode::CEBR, TR::InstOpCode::COND_BHR, TR::InstOpCode::LER);
}
TR::Register*
OMR::Z::TreeEvaluator::dmaxEvaluator(TR::Node* node, TR::CodeGenerator* cg)
{
return xmaxxminHelper(node, cg, TR::InstOpCode::CDBR, TR::InstOpCode::COND_BHR, TR::InstOpCode::LDR);
}
TR::Register *
OMR::Z::TreeEvaluator::iminEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return imaximinHelper(node, cg, TR::InstOpCode::CR, TR::InstOpCode::COND_BLR, TR::InstOpCode::LR);
}
TR::Register *
OMR::Z::TreeEvaluator::lminEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return lmaxlminHelper(node, cg, TR::InstOpCode::CGR, TR::InstOpCode::COND_BLR, TR::InstOpCode::LGR);
}
TR::Register*
OMR::Z::TreeEvaluator::fminEvaluator(TR::Node* node, TR::CodeGenerator* cg)
{
return xmaxxminHelper(node, cg, TR::InstOpCode::CEBR, TR::InstOpCode::COND_BLR, TR::InstOpCode::LER);
}
TR::Register*
OMR::Z::TreeEvaluator::dminEvaluator(TR::Node* node, TR::CodeGenerator* cg)
{
return xmaxxminHelper(node, cg, TR::InstOpCode::CDBR, TR::InstOpCode::COND_BLR, TR::InstOpCode::LDR);
}
/**
* 64bit version lcmpEvaluator Helper: long compare (1 if child1 > child2, 0 if child1 == child2,
* -1 if child1 < child2 or unordered)
*/
TR::Register *
lcmpHelper64(TR::Node * node, TR::CodeGenerator * cg)
{
// TODO:There is probably a better way to implement this. Should re-visit if we get the chance.
// As things stand now, we will to LCR R1,R1 when R1=0 which is useless... But still probably
// cheaper than an extra branch.
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol(cg);
TR::LabelSymbol * labelGT = generateLabelSymbol(cg);
TR::LabelSymbol * labelLT = generateLabelSymbol(cg);
TR::Register * targetRegister = cg->allocateRegister();
TR::Node * firstChild = node->getFirstChild();
TR::Node * secondChild = node->getSecondChild();
TR::Register * src1Reg = NULL;
if (firstChild->getReferenceCount() == 1)
src1Reg = (TR::Register *) cg->evaluate(firstChild);
else
src1Reg = (TR::Register *) cg->gprClobberEvaluate(firstChild);
TR::Register * src2Reg = NULL;
TR::Instruction * cursor = NULL;
if (secondChild->getOpCode().isLoadConst() && secondChild->getLongInt()==0)
{
generateRRInstruction(cg, TR::InstOpCode::LCGR, node, targetRegister, src1Reg);
generateRSInstruction(cg, TR::InstOpCode::SRAG, node, src1Reg, src1Reg, 63);
generateRSInstruction(cg, TR::InstOpCode::SRLG, node, targetRegister, targetRegister, 63);
generateRRInstruction(cg, TR::InstOpCode::OGR, node, targetRegister, src1Reg);
}
else
{
// Assume LT
generateRIInstruction(cg, TR::InstOpCode::LGHI, node, targetRegister, -1);
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
// Set the CC using a comp.
generateS390ImmOp(cg, TR::InstOpCode::CG, node, src1Reg, src1Reg, secondChild->getLongInt());
}
else
{
// Get src2Reg if it isn't a const
src2Reg = cg->evaluate(secondChild);
// Set the CC using a comp.
generateRRInstruction(cg, TR::InstOpCode::CGR, node, src1Reg, src2Reg);
}
// If LT we are done
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BL, node, labelLT);
// If GT, we invert the result register
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BH, node, labelGT);
// High order words were equal
// The two longs are equal
generateRIInstruction(cg, TR::InstOpCode::LGHI, node, targetRegister, 0);
// We can go through this path if GT, or if EQ.
// We use LCR to avoid having to branch over this piece of code.
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, labelGT);
generateRRInstruction(cg, TR::InstOpCode::LCGR, node, targetRegister, targetRegister);
// We branch here when LT (no change to assumed -1 result)
TR::RegisterDependencyConditions * dependencies = NULL;
dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
dependencies->addPostCondition(targetRegister, TR::RealRegister::AssignAny);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, labelLT, dependencies);
labelLT->setEndInternalControlFlow();
}
node->setRegister(targetRegister);
// did we clobberEval earlier?
if (!cg->canClobberNodesRegister(firstChild))
cg->stopUsingRegister(src1Reg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return targetRegister;
}
TR::Register *
OMR::Z::TreeEvaluator::branchEvaluator(TR::Node * node, TR::CodeGenerator *cg)
{
return NULL;
}
TR::Register *
OMR::Z::TreeEvaluator::ibranchEvaluator(TR::Node * node, TR::CodeGenerator *cg)
{
return NULL;
}
TR::Register *
OMR::Z::TreeEvaluator::mbranchEvaluator(TR::Node * node, TR::CodeGenerator *cg)
{
return NULL;
}
/**
* goto label address
*/
TR::Register *
OMR::Z::TreeEvaluator::gotoEvaluator(TR::Node * node, TR::CodeGenerator * cg)
{
TR::Node * temp = node->getBranchDestination()->getNode();
if (node->getNumChildren() > 0)
{
// GRA
TR::Node * child = node->getFirstChild();
cg->evaluate(child);
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BRC, node, temp->getLabel(), generateRegisterDependencyConditions(cg, child, 0));
cg->decReferenceCount(child);
}
else
{
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BRC, node, temp->getLabel());
}
return NULL;
}
/**
* Indirect goto to the address
*/
TR::Register *
OMR::Z::TreeEvaluator::igotoEvaluator(TR::Node * node, TR::CodeGenerator * cg)
{
TR_ASSERT( node->getNumChildren() >= 1, "at least one child expected for igoto");
TR::Node * child = node->getFirstChild();
TR::Register * dest = cg->evaluate(child);
TR::RegisterDependencyConditions * deps = NULL;
if (node->getNumChildren() > 1)
{
TR_ASSERT( node->getNumChildren() == 2 && node->getChild(1)->getOpCodeValue() == TR::GlRegDeps, "igoto has maximum of two children and second one must be global register dependency");
TR::Node *glregdep = node->getChild(1);
cg->evaluate(glregdep);
deps = generateRegisterDependencyConditions(cg, glregdep, 0);
cg->decReferenceCount(glregdep);
}
TR::Instruction* cursor;
if (deps)
cursor = generateS390RegInstruction(cg, TR::InstOpCode::BCR, node, dest, deps);
else
cursor = generateS390RegInstruction(cg, TR::InstOpCode::BCR, node, dest);
((TR::S390RegInstruction *)cursor)->setBranchCondition(TR::InstOpCode::COND_BCR);
cg->decReferenceCount(child);
return NULL;
}
/**
* Handles all types of return opcodes
* (return, areturn, ireturn, lreturn, freturn, dreturn, oreturn)
*/
TR::Register *
OMR::Z::TreeEvaluator::returnEvaluator(TR::Node * node, TR::CodeGenerator * cg)
{
TR::Compilation *comp = cg->comp();
if ((node->getOpCodeValue() == TR::Return) && node->isReturnDummy()) return NULL;
TR::Register * returnAddressReg = cg->allocateRegister();
TR::Register * returnValRegister = NULL;
TR::Register * CAARegister = NULL;
TR::Linkage * linkage = cg->getS390Linkage();
if (node->getOpCodeValue() != TR::Return)
returnValRegister = cg->evaluate(node->getFirstChild());
// add register dependency for the return value register and the return register
TR::RegisterDependencyConditions * dependencies = NULL ;
if (node->getOpCode().isJumpWithMultipleTargets() &&
(node->getNumChildren() > 1
) && node->getChild(node->getNumChildren() - 1)->getOpCodeValue() == TR::GlRegDeps)
{
TR::Node *glregdep = node->getChild(node->getNumChildren() - 1);
cg->evaluate(glregdep);
dependencies = generateRegisterDependencyConditions(cg, glregdep, 3);
cg->decReferenceCount(glregdep);
}
dependencies= new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 3, cg);
#ifdef J9_PROJECT_SPECIFIC
if ( node->getOpCodeValue() == TR::dereturn )
dependencies= new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 4, cg);
#endif
int regDepChildNum = 1;
switch (node->getOpCodeValue())
{
case TR::areturn:
comp->setReturnInfo(TR_ObjectReturn);
dependencies->addPostCondition(returnValRegister, linkage->getIntegerReturnRegister());
break;
case TR::ireturn:
dependencies->addPostCondition(returnValRegister, linkage->getIntegerReturnRegister());
comp->setReturnInfo(TR_IntReturn);
if (linkage->isNeedsWidening())
new (cg->trHeapMemory()) TR::S390RRInstruction(TR::InstOpCode::LGFR, node, returnValRegister, returnValRegister, cg);
break;
case TR::lreturn:
comp->setReturnInfo(TR_LongReturn);
if (cg->comp()->target().is64Bit())
{
dependencies->addPostCondition(returnValRegister, linkage->getLongReturnRegister());
}
else
{
TR::Register * highRegister = cg->allocateRegister();
generateRSInstruction(cg, TR::InstOpCode::SRLG, node, highRegister, returnValRegister, 32);
dependencies->addPostCondition(returnValRegister, linkage->getLongLowReturnRegister());
dependencies->addPostCondition(highRegister, linkage->getLongHighReturnRegister());
cg->stopUsingRegister(highRegister);
}
break;
case TR::freturn:
#ifdef J9_PROJECT_SPECIFIC
case TR::dfreturn:
#endif
comp->setReturnInfo(TR_FloatReturn);
dependencies->addPostCondition(returnValRegister, linkage->getFloatReturnRegister());
break;
case TR::dreturn:
#ifdef J9_PROJECT_SPECIFIC
case TR::ddreturn:
#endif
comp->setReturnInfo(TR_DoubleReturn);
dependencies->addPostCondition(returnValRegister, linkage->getDoubleReturnRegister());
break;
#ifdef J9_PROJECT_SPECIFIC
case TR::dereturn:
comp->setReturnInfo(TR_DoubleReturn);
dependencies->addPostCondition(returnValRegister->getHighOrder(), linkage->getLongDoubleReturnRegister0());
dependencies->addPostCondition(returnValRegister->getLowOrder(), linkage->getLongDoubleReturnRegister2());
break;
#endif
case TR::Return:
comp->setReturnInfo(TR_VoidReturn);
break;
}
TR::Instruction * inst = generateS390PseudoInstruction(cg, TR::InstOpCode::RET, node, dependencies);
if (cg->supportsBranchPreload())
{
int32_t frequency = comp->getCurrentBlock()->getFrequency();
if (frequency >= cg->_hottestReturn._frequency)
{
cg->_hottestReturn._returnInstr = inst;
cg->_hottestReturn._frequency = frequency;
cg->_hottestReturn._returnBlock = comp->getCurrentBlock();
}
}
cg->stopUsingRegister(returnAddressReg);
if (node->getOpCodeValue() != TR::Return)
cg->decReferenceCount(node->getFirstChild());
return NULL;
}
bool OMR::Z::TreeEvaluator::isCandidateForButestEvaluation(TR::Node * node)
{
TR::Node* firstChild = node->getFirstChild();
TR::Node* secondChild = node->getSecondChild();
return node->getOpCode().isIf() &&
firstChild->getOpCodeValue() == TR::butest &&
firstChild->getReferenceCount() == 1 &&
firstChild->getRegister() == NULL &&
secondChild->getOpCode().isLoadConst() &&
secondChild->getType().isInt32();
}
bool OMR::Z::TreeEvaluator::isCandidateForCompareEvaluation(TR::Node * node)
{
return node->getOpCode().isIf() &&
TR::TreeEvaluator::isSingleRefUnevalAndCompareOrBu2iOverCompare(node->getFirstChild()) &&
node->getSecondChild()->getOpCode().isLoadConst() &&
node->getSecondChild()->getType().isInt32();
}
bool OMR::Z::TreeEvaluator::isSingleRefUnevalAndCompareOrBu2iOverCompare(TR::Node * node)
{
if (node->getReferenceCount() != 1 || node->getRegister() != NULL)
return false;
if (node->getOpCodeValue() == TR::bu2i)
return TR::TreeEvaluator::isSingleRefUnevalAndCompareOrBu2iOverCompare(node->getFirstChild());
return false;
}
/**
* This helper is for generating a VGNOP for HCR or OSR guard when the guard it was merged with cannot be NOPed.
* 1. HCR or OSR guard is merged with ProfiledGuard
* 2. Any NOPable guards when node is switched from icmpne to icmpeq (can potentially happen during block reordering)
*
* When the condition is switched on node from eq to ne, HCR or OSR guard has to be patch to go to the fall through path
*/
static inline void generateMergedGuardCodeIfNeeded(TR::Node *node, TR::CodeGenerator *cg)
{
#ifdef J9_PROJECT_SPECIFIC
TR::Compilation *comp = cg->comp();
if (node->isTheVirtualGuardForAGuardedInlinedCall() && cg->getSupportsVirtualGuardNOPing())
{
TR_VirtualGuard *virtualGuard = comp->findVirtualGuardInfo(node);
if (virtualGuard && (virtualGuard->mergedWithOSRGuard() || virtualGuard->mergedWithHCRGuard()))
{
TR::RegisterDependencyConditions *mergedGuardDeps = NULL;
TR::Instruction *instr = cg->getAppendInstruction();
if (instr && instr->getNode() == node && instr->getDependencyConditions())
mergedGuardDeps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(instr->getDependencyConditions(), 1, 0, cg);
TR_VirtualGuardSite *site = virtualGuard->addNOPSite();
if (node->getOpCodeValue() == TR::ificmpeq ||
node->getOpCodeValue() == TR::ifacmpeq ||
node->getOpCodeValue() == TR::iflcmpeq )
{
TR::LabelSymbol *fallThroughLabel = generateLabelSymbol(cg);
TR::RegisterDependencyConditions *deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions((uint16_t) 0, (uint16_t) 0, cg);
TR::Instruction *vgnopInstr = generateVirtualGuardNOPInstruction(cg, node, site, deps, fallThroughLabel, instr ? instr->getPrev() : NULL);
vgnopInstr->setNext(instr);
cg->setAppendInstruction(instr);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, fallThroughLabel, mergedGuardDeps);
}
else
{
TR::LabelSymbol *label = node->getBranchDestination()->getNode()->getLabel();
TR::Instruction *vgnopInstr = generateVirtualGuardNOPInstruction(cg, node, site, mergedGuardDeps, label, instr ? instr->getPrev() : NULL);
vgnopInstr->setNext(instr);
cg->setAppendInstruction(instr);
}
traceMsg(comp, "generateMergedGuardCodeIfNeeded for %s %s\n",
comp->getDebug()?comp->getDebug()->getVirtualGuardKindName(virtualGuard->getKind()):"???Guard" , virtualGuard->mergedWithHCRGuard()?"merged with HCRGuard": virtualGuard->mergedWithOSRGuard() ? "merged with OSRGuard" : "");
}
}
#endif
}
/**
* Integer compare and branch if equal
* - also handles ificmpne
* - handles ifacmpeq ifacmpne in 32bit mode
*/
TR::Register *
OMR::Z::TreeEvaluator::ificmpeqEvaluator(TR::Node * node, TR::CodeGenerator * cg)
{
TR::Compilation *comp = cg->comp();
if (virtualGuardHelper(node, cg))
{
return NULL;
}
if (TR::TreeEvaluator::isCandidateForButestEvaluation(node))
{
TR::Node * cmpNode = node;
TR::Node * butestNode = node->getFirstChild();
TR::Node * valueNode = node->getSecondChild();
return TR::TreeEvaluator::inlineIfButestEvaluator(butestNode, cg, cmpNode, valueNode);
}
if (TR::TreeEvaluator::isCandidateForCompareEvaluation(node))
{
TR::Node *ifNode = node;
TR::Node *cmpNode = node->getFirstChild();
if (cmpNode->getOpCodeValue() == TR::bu2i)
cmpNode = cmpNode->getFirstChild();
TR::Node *valueNode = node->getSecondChild();
return TR::TreeEvaluator::inlineIfBifEvaluator(ifNode, cg, cmpNode, valueNode);
}
TR::Node * firstChild = node-> getFirstChild(), * secondChild = node->getSecondChild();
#ifdef J9_PROJECT_SPECIFIC
if ((firstChild->getOpCodeValue() == TR::instanceof) &&
!(comp->getOption(TR_OptimizeForSpace) || debug("noInlineIfInstanceOf")) &&
(firstChild->getRegister() == NULL) &&
(node->getReferenceCount() <= 1) &&
secondChild->getOpCode().isLoadConst() &&
(((secondChild->getInt() == 0 || secondChild->getInt() == 1))
))
{
if (TR::TreeEvaluator::VMifInstanceOfEvaluator(node, cg) == NULL)
{
cg->decReferenceCount(secondChild);
return NULL;
}
}
#endif
bool inlined = false;
TR::Register *reg;
reg = TR::TreeEvaluator::inlineIfArraycmpEvaluator(node, cg, inlined);
if (inlined)
{
generateMergedGuardCodeIfNeeded(node, cg);
return reg;
}
reg = TR::TreeEvaluator::inlineIfTestDataClassHelper(node, cg, inlined);
if(inlined)
{
generateMergedGuardCodeIfNeeded(node, cg);
return reg;
}
#ifdef J9_PROJECT_SPECIFIC
if (cg->profiledPointersRequireRelocation() &&
node->isProfiledGuard() && secondChild->getOpCodeValue() == TR::aconst &&
(secondChild->isClassPointerConstant() || secondChild->isMethodPointerConstant()))
{
TR_VirtualGuard *virtualGuard = comp->findVirtualGuardInfo(node);
TR_AOTGuardSite *site = comp->addAOTNOPSite();
site->setType(virtualGuard->getKind());
site->setGuard(virtualGuard);
site->setNode(node);
site->setAconstNode(secondChild);
}
#endif
if (node->getOpCodeValue() == TR::ificmpeq||
node->getOpCodeValue() == TR::ifacmpeq)
{
reg = generateS390CompareBranch(node, cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BE, TR::InstOpCode::COND_BE);
}
else
{
reg = generateS390CompareBranch(node, cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BNE, TR::InstOpCode::COND_BNE);
}
generateMergedGuardCodeIfNeeded(node, cg);
return reg;
}
/**
* Helper for ificmp(ge, gt, lt, le)
* this code was taken from ificmpeqEvaluator,
* but since ificmpeqEvaluator has more folding going on,
* it doesn't make sense to call this function from ificmpeqEvaluator
*/
TR::Register* OMR::Z::TreeEvaluator::ifFoldingHelper(TR::Node *node, TR::CodeGenerator *cg, bool &handledBIF)
{
handledBIF = true;
TR::Node * firstChild = node->getFirstChild(), * secondChild = node->getSecondChild();
bool inlined = false;
TR::Register *reg = TR::TreeEvaluator::inlineIfTestDataClassHelper(node, cg, inlined);
if(inlined)
return reg;
handledBIF = false;
return NULL;
}
/**
* Integer compare and branch if less than
*/
TR::Register *
OMR::Z::TreeEvaluator::ificmpltEvaluator(TR::Node * node, TR::CodeGenerator * cg)
{
bool inlined = false;
TR::Register *reg;