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OMRInstOpCode.enum
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OMRInstOpCode.enum
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/*******************************************************************************
* Copyright (c) 2021, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
/*
* This file will be included within an enum. Only comments and enumerator
* definitions are permitted.
*/
#include "compiler/codegen/OMRInstOpCode.enum"
BADIA32Op,
ADC1AccImm1,
ADC2AccImm2,
ADC4AccImm4,
ADC8AccImm4,
ADC1RegImm1,
ADC2RegImm2,
ADC2RegImms,
ADC4RegImm4,
ADC8RegImm4,
ADC4RegImms,
ADC8RegImms,
ADC1MemImm1,
ADC2MemImm2,
ADC2MemImms,
ADC4MemImm4,
ADC8MemImm4,
ADC4MemImms,
ADC8MemImms,
ADC1RegReg,
ADC2RegReg,
ADC4RegReg,
ADC8RegReg,
ADC1RegMem,
ADC2RegMem,
ADC4RegMem,
ADC8RegMem,
ADC1MemReg,
ADC2MemReg,
ADC4MemReg,
ADC8MemReg,
ADD1AccImm1,
ADD2AccImm2,
ADD4AccImm4,
ADD8AccImm4,
ADD1RegImm1,
ADD2RegImm2,
ADD2RegImms,
ADD4RegImm4,
ADD8RegImm4,
ADD4RegImms,
ADD8RegImms,
ADD1MemImm1,
ADD2MemImm2,
ADD2MemImms,
ADD4MemImm4,
ADD8MemImm4,
ADD4MemImms,
ADD8MemImms,
ADD1RegReg,
ADD2RegReg,
ADD4RegReg,
ADD8RegReg,
ADD1RegMem,
ADD2RegMem,
ADD4RegMem,
ADD8RegMem,
ADD1MemReg,
ADD2MemReg,
ADD4MemReg,
ADD8MemReg,
ADDSSRegReg,
ADDSSRegMem,
ADDPSRegReg,
ADDPSRegMem,
ADDSDRegReg,
ADDSDRegMem,
ADDPDRegReg,
ADDPDRegMem,
LADD1MemReg,
LADD2MemReg,
LADD4MemReg,
LADD8MemReg,
LXADD1MemReg,
LXADD2MemReg,
LXADD4MemReg,
LXADD8MemReg,
AND1AccImm1,
AND2AccImm2,
AND4AccImm4,
AND8AccImm4,
AND1RegImm1,
AND2RegImm2,
AND2RegImms,
AND4RegImm4,
AND8RegImm4,
AND4RegImms,
AND8RegImms,
AND1MemImm1,
AND2MemImm2,
AND2MemImms,
AND4MemImm4,
AND8MemImm4,
AND4MemImms,
AND8MemImms,
AND1RegReg,
AND2RegReg,
AND4RegReg,
AND8RegReg,
AND1RegMem,
AND2RegMem,
AND4RegMem,
AND8RegMem,
AND1MemReg,
AND2MemReg,
AND4MemReg,
AND8MemReg,
BSF2RegReg,
BSF4RegReg,
BSF8RegReg,
BSR4RegReg,
BSR8RegReg,
BSWAP4Reg,
BSWAP8Reg,
BTR4RegImm1,
BTR8RegImm1,
BTS4RegReg,
BTS4MemReg,
BT4RegReg,
BT8RegReg,
CALLImm4,
CALLREXImm4,
CALLReg,
CALLREXReg,
CALLMem,
CALLREXMem,
CBWAcc,
CBWEAcc,
CLC,
CLD,
CMOVA4RegMem,
CMOVA8RegMem,
CMOVB4RegMem,
CMOVE4RegMem,
CMOVE8RegMem,
CMOVG4RegMem,
CMOVGE4RegMem,
CMOVGE8RegMem,
CMOVL4RegMem,
CMOVNE4RegMem,
CMOVNE8RegMem,
CMOVNO4RegMem,
CMOVNS4RegMem,
CMOVO4RegMem,
CMOVP4RegMem,
CMOVP8RegMem,
CMOVS4RegMem,
CMP1AccImm1,
CMP2AccImm2,
CMP4AccImm4,
CMP8AccImm4,
CMP1RegImm1,
CMP2RegImm2,
CMP2RegImms,
CMP4RegImm4,
CMP8RegImm4,
CMP4RegImms,
CMP8RegImms,
CMP1MemImm1,
CMP2MemImm2,
CMP2MemImms,
CMP4MemImm4,
CMP8MemImm4,
CMP4MemImms,
CMP8MemImms,
CMP1RegReg,
CMP2RegReg,
CMP4RegReg,
CMP8RegReg,
CMP1RegMem,
CMP2RegMem,
CMP4RegMem,
CMP8RegMem,
CMP1MemReg,
CMP2MemReg,
CMP4MemReg,
CMP8MemReg,
CMPXCHG1MemReg,
CMPXCHG2MemReg,
CMPXCHG4MemReg,
CMPXCHG8MemReg,
CMPXCHG8BMem,
CMPXCHG16BMem,
LCMPXCHG1MemReg,
LCMPXCHG2MemReg,
LCMPXCHG4MemReg,
LCMPXCHG8MemReg,
LCMPXCHG8BMem,
LCMPXCHG16BMem,
XALCMPXCHG8MemReg,
XACMPXCHG8MemReg,
XALCMPXCHG4MemReg,
XACMPXCHG4MemReg,
CMPSB,
CMPSW,
CMPSD,
CMPSQ,
CVTSI2SSRegReg4,
CVTSI2SSRegReg8,
CVTSI2SSRegMem,
CVTSI2SSRegMem8,
CVTSI2SDRegReg4,
CVTSI2SDRegReg8,
CVTSI2SDRegMem,
CVTSI2SDRegMem8,
CVTTSS2SIReg4Reg,
CVTTSS2SIReg8Reg,
CVTTSS2SIReg4Mem,
CVTTSS2SIReg8Mem,
CVTTSD2SIReg4Reg,
CVTTSD2SIReg8Reg,
CVTTSD2SIReg4Mem,
CVTTSD2SIReg8Mem,
CVTSS2SDRegReg,
CVTSS2SDRegMem,
CVTSD2SSRegReg,
CVTSD2SSRegMem,
CWDAcc,
CDQAcc,
CQOAcc,
DEC1Reg,
#ifdef TR_TARGET_64BIT
DEC2Reg,
DEC4Reg,
#else
DEC2Reg,
DEC4Reg,
#endif
DEC8Reg,
DEC1Mem,
DEC2Mem,
DEC4Mem,
DEC8Mem,
FABSReg,
DABSReg,
FSQRTReg,
DSQRTReg,
FADDRegReg,
DADDRegReg,
FADDPReg,
FADDRegMem,
DADDRegMem,
FIADDRegMem,
DIADDRegMem,
FSADDRegMem,
DSADDRegMem,
FCHSReg,
DCHSReg,
FDIVRegReg,
DDIVRegReg,
FDIVRegMem,
DDIVRegMem,
FDIVPReg,
FIDIVRegMem,
DIDIVRegMem,
FSDIVRegMem,
DSDIVRegMem,
FDIVRRegReg,
DDIVRRegReg,
FDIVRRegMem,
DDIVRRegMem,
FDIVRPReg,
FIDIVRRegMem,
DIDIVRRegMem,
FSDIVRRegMem,
DSDIVRRegMem,
FILDRegMem,
DILDRegMem,
FLLDRegMem,
DLLDRegMem,
FSLDRegMem,
DSLDRegMem,
FISTMemReg,
DISTMemReg,
FISTPMem,
DISTPMem,
FLSTPMem,
DLSTPMem,
FSSTMemReg,
DSSTMemReg,
FSSTPMem,
DSSTPMem,
FLDLN2,
FLDRegReg,
DLDRegReg,
FLDRegMem,
DLDRegMem,
FLD0Reg,
DLD0Reg,
FLD1Reg,
DLD1Reg,
FLDMem,
DLDMem,
LDCWMem,
FMULRegReg,
DMULRegReg,
FMULPReg,
FMULRegMem,
DMULRegMem,
FIMULRegMem,
DIMULRegMem,
FSMULRegMem,
DSMULRegMem,
FNCLEX,
FPREMRegReg,
FSCALERegReg,
FSTMemReg,
DSTMemReg,
FSTRegReg,
DSTRegReg,
FSTPMemReg,
DSTPMemReg,
FSTPReg,
DSTPReg,
STCWMem,
STSWMem,
STSWAcc,
FSUBRegReg,
DSUBRegReg,
FSUBRegMem,
DSUBRegMem,
FSUBPReg,
FISUBRegMem,
DISUBRegMem,
FSSUBRegMem,
DSSUBRegMem,
FSUBRRegReg,
DSUBRRegReg,
FSUBRRegMem,
DSUBRRegMem,
FSUBRPReg,
FISUBRRegMem,
DISUBRRegMem,
FSSUBRRegMem,
DSSUBRRegMem,
FTSTReg,
FCOMRegReg,
DCOMRegReg,
FCOMRegMem,
DCOMRegMem,
FCOMPReg,
FCOMPMem,
DCOMPMem,
FCOMPP,
FCOMIRegReg,
DCOMIRegReg,
FCOMIPReg,
FYL2X,
UCOMISSRegReg,
UCOMISSRegMem,
UCOMISDRegReg,
UCOMISDRegMem,
FXCHReg,
IDIV1AccReg,
IDIV2AccReg,
IDIV4AccReg,
IDIV8AccReg,
DIV4AccReg,
DIV8AccReg,
IDIV1AccMem,
IDIV2AccMem,
IDIV4AccMem,
IDIV8AccMem,
DIV4AccMem,
DIV8AccMem,
DIVSSRegReg,
DIVSSRegMem,
DIVPSRegReg,
DIVPSRegMem,
DIVSDRegReg,
DIVSDRegMem,
DIVPDRegReg,
DIVPDRegMem,
IMUL1AccReg,
IMUL2AccReg,
IMUL4AccReg,
IMUL8AccReg,
IMUL1AccMem,
IMUL2AccMem,
IMUL4AccMem,
IMUL8AccMem,
IMUL2RegReg,
IMUL4RegReg,
IMUL8RegReg,
IMUL2RegMem,
IMUL4RegMem,
IMUL8RegMem,
IMUL2RegRegImm2,
IMUL2RegRegImms,
IMUL4RegRegImm4,
IMUL8RegRegImm4,
IMUL4RegRegImms,
IMUL8RegRegImms,
IMUL2RegMemImm2,
IMUL2RegMemImms,
IMUL4RegMemImm4,
IMUL8RegMemImm4,
IMUL4RegMemImms,
IMUL8RegMemImms,
MUL1AccReg,
MUL2AccReg,
MUL4AccReg,
MUL8AccReg,
MUL1AccMem,
MUL2AccMem,
MUL4AccMem,
MUL8AccMem,
MULSSRegReg,
MULSSRegMem,
MULPSRegReg,
MULPSRegMem,
MULSDRegReg,
MULSDRegMem,
MULPDRegReg,
MULPDRegMem,
INC1Reg,
#ifdef TR_TARGET_64BIT
INC2Reg,
INC4Reg,
#else
INC2Reg,
INC4Reg,
#endif
INC8Reg,
INC1Mem,
INC2Mem,
INC4Mem,
INC8Mem,
JA1,
JAE1,
JB1,
JBE1,
JE1,
JNE1,
JG1,
JGE1,
JL1,
JLE1,
JO1,
JNO1,
JS1,
JNS1,
JPO1,
JPE1,
JMP1,
JA4,
JAE4,
JB4,
JBE4,
JE4,
JNE4,
JG4,
JGE4,
JL4,
JLE4,
JO4,
JNO4,
JS4,
JNS4,
JPO4,
JPE4,
JMP4,
JMPReg,
JMPMem,
JRCXZ1,
LOOP1,
LAHF,
LDDQU,
LEA2RegMem,
LEA4RegMem,
LEA8RegMem,
S1MemReg,
S2MemReg,
S4MemReg,
S8MemReg,
S1MemImm1,
S2MemImm2,
S4MemImm4,
XRS4MemImm4,
S8MemImm4,
XRS8MemImm4,
L1RegMem,
L2RegMem,
L4RegMem,
L8RegMem,
MOVAPSRegReg,
MOVAPSRegMem,
MOVAPSMemReg,
MOVAPDRegReg,
MOVAPDRegMem,
MOVAPDMemReg,
MOVUPSRegReg,
MOVUPSRegMem,
MOVUPSMemReg,
MOVUPDRegReg,
MOVUPDRegMem,
MOVUPDMemReg,
MOVSSRegReg,
MOVSSRegMem,
MOVSSMemReg,
MOVSDRegReg,
MOVSDRegMem,
MOVSDMemReg,
SQRTSSRegReg,
SQRTSDRegReg,
MOVDRegReg4,
MOVQRegReg8,
MOVDReg4Reg,
MOVQReg8Reg,
MOVDQURegReg,
MOVDQURegMem,
VMOVDQURegReg,
VMOVDQURegMem,
MOVDQUMemReg,
MOV1RegReg,
MOV2RegReg,
MOV4RegReg,
MOV8RegReg,
CMOVB4RegReg,
CMOVB8RegReg,
CMOVG4RegReg,
CMOVG8RegReg,
CMOVGE4RegReg,
CMOVGE8RegReg,
CMOVL4RegReg,
CMOVL8RegReg,
CMOVLE4RegReg,
CMOVLE8RegReg,
CMOVE4RegReg,
CMOVE8RegReg,
CMOVNE4RegReg,
CMOVNE8RegReg,
CMOVS4RegReg,
CMOVS8RegReg,
MOV1RegImm1,
MOV2RegImm2,
MOV4RegImm4,
MOV8RegImm4,
MOV8RegImm64,
MOVLPDRegMem,
MOVLPDMemReg,
MOVDRegMem,
MOVDMemReg,
MOVQRegMem,
MOVQMemReg,
MOVSB,
MOVSW,
MOVSD,
MOVSQ,
MOVSXReg2Reg1,
MOVSXReg4Reg1,
MOVSXReg8Reg1,
MOVSXReg4Reg2,
MOVSXReg8Reg2,
MOVSXReg8Reg4,
MOVSXReg2Mem1,
MOVSXReg4Mem1,
MOVSXReg8Mem1,
MOVSXReg4Mem2,
MOVSXReg8Mem2,
MOVSXReg8Mem4,
MOVZXReg2Reg1,
MOVZXReg4Reg1,
MOVZXReg8Reg1,
MOVZXReg4Reg2,
MOVZXReg8Reg2,
MOVZXReg8Reg4,
MOVZXReg2Mem1,
MOVZXReg4Mem1,
MOVZXReg8Mem1,
MOVZXReg4Mem2,
MOVZXReg8Mem2,
NEG1Reg,
NEG2Reg,
NEG4Reg,
NEG8Reg,
NEG1Mem,
NEG2Mem,
NEG4Mem,
NEG8Mem,
NOT1Reg,
NOT2Reg,
NOT4Reg,
NOT8Reg,
NOT1Mem,
NOT2Mem,
NOT4Mem,
NOT8Mem,
OR1AccImm1,
OR2AccImm2,
OR4AccImm4,
OR8AccImm4,
OR1RegImm1,
OR2RegImm2,
OR2RegImms,
OR4RegImm4,
OR8RegImm4,
OR4RegImms,
OR8RegImms,
OR1MemImm1,
OR2MemImm2,
OR2MemImms,
OR4MemImm4,
OR8MemImm4,
OR4MemImms,
LOR4MemImms,
LOR4MemReg,
LOR8MemReg,
OR8MemImms,
OR1RegReg,
OR2RegReg,
OR4RegReg,
OR8RegReg,
OR1RegMem,
OR2RegMem,
OR4RegMem,
OR8RegMem,
OR1MemReg,
OR2MemReg,
OR4MemReg,
OR8MemReg,
PAUSE,
PACKUSWBRegReg,
PUNPCKHBWRegReg,
PUNPCKLBWRegReg,
PCMPEQBRegReg,
VPCMPEQBRegReg,
VPCMPEQBRegMem,
PCMPEQWRegReg,
VPCMPEQWRegReg,
VPCMPEQWRegMem,
PCMPGTBRegReg,
PCMPGTWRegReg,
PMOVMSKB4RegReg,
VPMOVMSKB4RegReg,
PMOVZXBDRegReg,
PMOVZXBDRegMem,
PMOVZXWDRegReg,
PMOVZXWDRegMem,
PMULLWRegReg,
PMULLWRegMem,
PMULLDRegReg,
PMULLDRegMem,
PADDBRegReg,
PADDBRegMem,
PADDWRegReg,
PADDWRegMem,
PADDDRegReg,
PADDDRegMem,
PADDQRegReg,
PADDQRegMem,
PSUBBRegReg,
PSUBBRegMem,
PSUBWRegReg,
PSUBWRegMem,
PSUBDRegReg,
PSUBDRegMem,
PSUBQRegReg,
PSUBQRegMem,
PANDRegReg,
PANDRegMem,
PORRegReg,
PORRegMem,
PXORRegReg,
PXORRegMem,
PTESTRegReg,
PANDNRegReg,
PEXTRDRegReg,
PEXTRQRegReg,
PSHUFBRegReg,
PSHUFBRegMem,
PSHUFDRegRegImm1,
PSHUFDRegMemImm1,
PSRLDQRegImm1,
PMOVZXxmm18Reg,
POPCNT4RegReg,
POPCNT8RegReg,
PUSHFD,
POPFD,
POPReg,
POPMem,
PUSHImms,
PUSHImm4,
PUSHReg,
PUSHRegLong,
PUSHMem,
RCL1RegImm1,
RCL4RegImm1,
RCR1RegImm1,
RCR4RegImm1,
REPMOVSB,
REPMOVSW,
REPMOVSD,
REPMOVSQ,
REPECMPSB,
REPECMPSW,
REPECMPSD,
REPECMPSQ,
REPSTOSB,
REPSTOSW,
REPSTOSD,
REPSTOSQ,
RET,
RETImm2,
ROL8Reg1,
ROL1RegImm1,
ROL2RegImm1,
ROL4RegImm1,
ROL8RegImm1,
ROL4RegCL,
ROL8RegCL,
ROR8Reg1,
ROR1RegImm1,
ROR2RegImm1,
ROR4RegImm1,
ROR8RegImm1,
SAHF,
SHL1RegImm1,
SHL1RegCL,
SHL2RegImm1,
SHL2RegCL,
SHL4RegImm1,
SHL8RegImm1,
SHL4RegCL,
SHL8RegCL,
SHL1MemImm1,
SHL1MemCL,
SHL2MemImm1,
SHL2MemCL,
SHL4MemImm1,
SHL8MemImm1,
SHL4MemCL,
SHL8MemCL,
SHR1RegImm1,
SHR1RegCL,
SHR2RegImm1,
SHR2RegCL,
SHR4Reg1,
SHR8Reg1,
SHR4RegImm1,
SHR8RegImm1,
SHR4RegCL,
SHR8RegCL,
SHR1MemImm1,
SHR1MemCL,
SHR2MemImm1,
SHR2MemCL,
SHR4MemImm1,
SHR8MemImm1,
SHR4MemCL,
SHR8MemCL,
SAR1RegImm1,
SAR1RegCL,
SAR2RegImm1,
SAR2RegCL,
SAR4RegImm1,
SAR8RegImm1,
SAR4RegCL,
SAR8RegCL,
SAR1MemImm1,
SAR1MemCL,
SAR2MemImm1,
SAR2MemCL,
SAR4MemImm1,
SAR8MemImm1,
SAR4MemCL,
SAR8MemCL,
SBB1AccImm1,
SBB2AccImm2,
SBB4AccImm4,
SBB8AccImm4,
SBB1RegImm1,
SBB2RegImm2,
SBB2RegImms,
SBB4RegImm4,
SBB8RegImm4,
SBB4RegImms,
SBB8RegImms,
SBB1MemImm1,
SBB2MemImm2,
SBB2MemImms,
SBB4MemImm4,
SBB8MemImm4,
SBB4MemImms,
SBB8MemImms,
SBB1RegReg,
SBB2RegReg,
SBB4RegReg,
SBB8RegReg,
SBB1RegMem,
SBB2RegMem,
SBB4RegMem,
SBB8RegMem,
SBB1MemReg,
SBB2MemReg,
SBB4MemReg,
SBB8MemReg,
SETA1Reg,
SETAE1Reg,
SETB1Reg,
SETBE1Reg,
SETE1Reg,
SETNE1Reg,
SETG1Reg,
SETGE1Reg,
SETL1Reg,
SETLE1Reg,
SETS1Reg,
SETNS1Reg,
SETPO1Reg,
SETPE1Reg,
SETA1Mem,
SETAE1Mem,
SETB1Mem,
SETBE1Mem,
SETE1Mem,
SETNE1Mem,
SETG1Mem,
SETGE1Mem,
SETL1Mem,
SETLE1Mem,
SETS1Mem,
SETNS1Mem,
SHLD4RegRegImm1,
SHLD4RegRegCL,
SHLD4MemRegImm1,
SHLD4MemRegCL,
SHRD4RegRegImm1,
SHRD4RegRegCL,
SHRD4MemRegImm1,
SHRD4MemRegCL,
STC,
STD,
STOSB,
STOSW,
STOSD,
STOSQ,
SUB1AccImm1,
SUB2AccImm2,
SUB4AccImm4,
SUB8AccImm4,
SUB1RegImm1,
SUB2RegImm2,
SUB2RegImms,
SUB4RegImm4,
SUB8RegImm4,
SUB4RegImms,
SUB8RegImms,
SUB1MemImm1,
SUB2MemImm2,
SUB2MemImms,
SUB4MemImm4,
SUB8MemImm4,
SUB4MemImms,
SUB8MemImms,
SUB1RegReg,
SUB2RegReg,
SUB4RegReg,
SUB8RegReg,
SUB1RegMem,
SUB2RegMem,
SUB4RegMem,
SUB8RegMem,
SUB1MemReg,
SUB2MemReg,
SUB4MemReg,
SUB8MemReg,
SUBSSRegReg,
SUBSSRegMem,
SUBPSRegReg,
SUBPSRegMem,
SUBSDRegReg,
SUBSDRegMem,
SUBPDRegReg,
SUBPDRegMem,
TEST1AccImm1,
TEST1AccHImm1,
TEST2AccImm2,
TEST4AccImm4,
TEST8AccImm4,
TEST1RegImm1,
TEST2RegImm2,
TEST4RegImm4,
TEST8RegImm4,
TEST1MemImm1,
TEST2MemImm2,
TEST4MemImm4,
TEST8MemImm4,
TEST1RegReg,
TEST2RegReg,
TEST4RegReg,
TEST8RegReg,
TEST1MemReg,
TEST2MemReg,
TEST4MemReg,
TEST8MemReg,
XABORT,
XBEGIN2,
XBEGIN4,
XCHG2AccReg,
XCHG4AccReg,
XCHG8AccReg,
XCHG1RegReg,
XCHG2RegReg,
XCHG4RegReg,
XCHG8RegReg,
XCHG1RegMem,
XCHG2RegMem,
XCHG4RegMem,
XCHG8RegMem,
XCHG1MemReg,
XCHG2MemReg,
XCHG4MemReg,
XCHG8MemReg,
XEND,
XOR1AccImm1,
XOR2AccImm2,
XOR4AccImm4,
XOR8AccImm4,
XOR1RegImm1,
XOR2RegImm2,
XOR2RegImms,
XOR4RegImm4,
XOR8RegImm4,
XOR4RegImms,
XOR8RegImms,
XOR1MemImm1,
XOR2MemImm2,
XOR2MemImms,
XOR4MemImm4,
XOR8MemImm4,
XOR4MemImms,
XOR8MemImms,
XOR1RegReg,
XOR2RegReg,
XOR4RegReg,
XOR8RegReg,
XOR1RegMem,
XOR2RegMem,
XOR4RegMem,
XOR8RegMem,
XOR1MemReg,
XOR2MemReg,
XOR4MemReg,
XOR8MemReg,
XORPSRegReg,
XORPSRegMem,
XORPDRegReg,
MFENCE,
LFENCE,
SFENCE,
PCMPESTRI,
PREFETCHNTA,
PREFETCHT0,
PREFETCHT1,
PREFETCHT2,
ANDNPSRegReg,
ANDNPDRegReg,
PSLLQRegImm1,
PSRLQRegImm1,
VPERM2I128RegRegImm1,
VFMADD132SSRegRegReg,
VFMADD132SSRegRegMem,
VFMADD213SSRegRegReg,
VFMADD213SSRegRegMem,
VFMADD231SSRegRegReg,
VFMADD231SSRegRegMem,
VFMADD132SDRegRegReg,
VFMADD132SDRegRegMem,
VFMADD213SDRegRegReg,
VFMADD213SDRegRegMem,
VFMADD231SDRegRegReg,