/
OMRRegisterDependency.cpp
1856 lines (1644 loc) · 72 KB
/
OMRRegisterDependency.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2019 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
//On zOS XLC linker can't handle files with same name at link time
//This workaround with pragma is needed. What this does is essentially
//give a different name to the codesection (csect) for this file. So it
//doesn't conflict with another file with same name.
#pragma csect(CODE,"OMRZRegisterDependency#C")
#pragma csect(STATIC,"OMRZRegisterDependency#S")
#pragma csect(TEST,"OMRZRegisterDependency#T")
#include <stddef.h>
#include <stdint.h>
#include "codegen/BackingStore.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/RegisterPair.hpp"
#include "compile/Compilation.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "cs2/hashtab.h"
#include "env/CompilerEnv.hpp"
#include "env/ObjectModel.hpp"
#include "env/TRMemory.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/symbol/AutomaticSymbol.hpp"
#include "il/symbol/LabelSymbol.hpp"
#include "infra/Assert.hpp"
#include "infra/List.hpp"
#include "ras/Debug.hpp"
#include "z/codegen/S390GenerateInstructions.hpp"
#include "z/codegen/S390Instruction.hpp"
#include "env/IO.hpp"
OMR::Z::RegisterDependencyConditions::RegisterDependencyConditions(TR::CodeGenerator * cg, TR::Node * node,
uint32_t extranum, TR::Instruction ** cursorPtr)
{
TR::Compilation *comp = cg->comp();
_cg = cg;
List<TR::Register> regList(cg->trMemory());
TR::Instruction * iCursor = (cursorPtr == NULL) ? NULL : *cursorPtr;
int32_t totalNum = node->getNumChildren() + extranum;
int32_t i;
comp->incVisitCount();
int32_t numLongs = 0;
int32_t numLongDoubles = 0;
//
// Pre-compute how many longs are global register candidates
//
for (i = 0; i < node->getNumChildren(); ++i)
{
TR::Node * child = node->getChild(i);
TR::Register * reg = child->getRegister();
if (reg->getKind() == TR_GPR)
{
if (child->getHighGlobalRegisterNumber() > -1)
{
numLongs++;
}
}
}
totalNum = totalNum + numLongs + numLongDoubles;
_preConditions = new (totalNum, cg->trMemory()) TR_S390RegisterDependencyGroup;
_postConditions = new (totalNum, cg->trMemory()) TR_S390RegisterDependencyGroup;
_numPreConditions = totalNum;
_addCursorForPre = 0;
_numPostConditions = totalNum;
_addCursorForPost = 0;
_isUsed = false;
_isHint = false;
_conflictsResolved = false;
for (i = 0; i < totalNum; i++)
{
_preConditions->clearDependencyInfo(i);
_postConditions->clearDependencyInfo(i);
}
for (i = 0; i < node->getNumChildren(); i++)
{
TR::Node * child = node->getChild(i);
TR::Register * reg = child->getRegister();
TR::Register * highReg = NULL;
TR::Register * copyReg = NULL;
TR::Register * highCopyReg = NULL;
TR::RealRegister::RegNum regNum = (TR::RealRegister::RegNum)
cg->getGlobalRegister(child->getGlobalRegisterNumber());
TR::RealRegister::RegNum highRegNum;
if (child->getHighGlobalRegisterNumber() > -1)
{
highRegNum = (TR::RealRegister::RegNum) cg->getGlobalRegister(child->getHighGlobalRegisterNumber());
}
TR::RegisterPair * regPair = reg->getRegisterPair();
resolveSplitDependencies(cg, node, child, regPair, regList, reg, highReg, copyReg, highCopyReg, iCursor, regNum);
reg->setAssociation(regNum);
cg->setRealRegisterAssociation(reg, regNum);
addPreCondition(reg, regNum);
addPostCondition(reg, regNum);
if (copyReg != NULL)
{
cg->stopUsingRegister(copyReg);
}
if (highReg)
{
highReg->setAssociation(highRegNum);
cg->setRealRegisterAssociation(highReg, highRegNum);
addPreCondition(highReg, highRegNum);
addPostCondition(highReg, highRegNum);
if (highCopyReg != NULL)
{
cg->stopUsingRegister(highCopyReg);
}
}
}
if (iCursor != NULL && cursorPtr != NULL)
{
*cursorPtr = iCursor;
}
}
OMR::Z::RegisterDependencyConditions::RegisterDependencyConditions(TR::RegisterDependencyConditions* iConds, uint16_t numNewPreConds, uint16_t numNewPostConds, TR::CodeGenerator * cg)
: _preConditions(TR_S390RegisterDependencyGroup::create((iConds?iConds->getNumPreConditions():0)+numNewPreConds, cg->trMemory())),
_postConditions(TR_S390RegisterDependencyGroup::create((iConds?iConds->getNumPostConditions():0)+numNewPostConds, cg->trMemory())),
_numPreConditions((iConds?iConds->getNumPreConditions():0)+numNewPreConds),
_addCursorForPre(0),
_numPostConditions((iConds?iConds->getNumPostConditions():0)+numNewPostConds),
_addCursorForPost(0),
_isHint(false),
_isUsed(false),
_conflictsResolved(false),
_cg(cg)
{
int32_t i;
TR_S390RegisterDependencyGroup* depGroup;
uint16_t numPreConds = (iConds?iConds->getNumPreConditions():0)+numNewPreConds;
uint16_t numPostConds = (iConds?iConds->getNumPostConditions():0)+numNewPostConds;
uint32_t flag;
TR::RealRegister::RegNum rr;
TR::Register* vr;
for(i=0;i<numPreConds;i++)
{
_preConditions->clearDependencyInfo(i);
}
for(int32_t j=0;j<numPostConds;j++)
{
_postConditions->clearDependencyInfo(j);
}
if (iConds != NULL)
{
depGroup = iConds->getPreConditions();
// depGroup->printDeps(stdout, iConds->getNumPreConditions());
for(i=0;i<iConds->getAddCursorForPre();i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
flag = dep->getFlags();
vr = dep->getRegister();
rr = dep->getRealRegister();
_preConditions->setDependencyInfo(_addCursorForPre++, vr, rr, flag);
}
depGroup = iConds->getPostConditions();
// depGroup->printDeps(stdout, iConds->getNumPostConditions());
for(i=0;i<iConds->getAddCursorForPost();i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
flag = dep->getFlags();
vr = dep->getRegister();
rr = dep->getRealRegister();
_postConditions->setDependencyInfo(_addCursorForPost++, vr, rr, flag);
}
}
}
OMR::Z::RegisterDependencyConditions::RegisterDependencyConditions(TR::RegisterDependencyConditions * conds_1,
TR::RegisterDependencyConditions * conds_2,
TR::CodeGenerator * cg)
: _preConditions(TR_S390RegisterDependencyGroup::create(conds_1->getNumPreConditions()+conds_2->getNumPreConditions(), cg->trMemory())),
_postConditions(TR_S390RegisterDependencyGroup::create(conds_1->getNumPostConditions()+conds_2->getNumPostConditions(), cg->trMemory())),
_numPreConditions(conds_1->getNumPreConditions()+conds_2->getNumPreConditions()),
_addCursorForPre(0),
_numPostConditions(conds_1->getNumPostConditions()+conds_2->getNumPostConditions()),
_addCursorForPost(0),
_isUsed(false),
_isHint(false),
_conflictsResolved(false),
_cg(cg)
{
int32_t i;
TR_S390RegisterDependencyGroup* depGroup;
uint32_t flag;
TR::RealRegister::RegNum rr;
TR::Register* vr;
for( i = 0; i < _numPreConditions; i++)
{
_preConditions->clearDependencyInfo(i);
}
for( i = 0; i < _numPostConditions; i++)
{
_postConditions->clearDependencyInfo(i);
}
// Merge pre conditions
depGroup = conds_1->getPreConditions();
for( i = 0; i < conds_1->getAddCursorForPre(); i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
flag = dep->getFlags();
vr = dep->getRegister();
rr = dep->getRealRegister();
if( doesPreConditionExist( vr, rr, flag, true ) )
{
_numPreConditions--;
}
else if( !addPreConditionIfNotAlreadyInserted( vr, rr, flag ) )
{
_numPreConditions--;
}
}
depGroup = conds_2->getPreConditions();
for( i = 0; i < conds_2->getAddCursorForPre(); i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
flag = dep->getFlags();
vr = dep->getRegister();
rr = dep->getRealRegister();
if( doesPreConditionExist( vr, rr, flag, true ) )
{
_numPreConditions--;
}
else if( !addPreConditionIfNotAlreadyInserted( vr, rr, flag ) )
{
_numPreConditions--;
}
}
// Merge post conditions
depGroup = conds_1->getPostConditions();
for( i = 0; i < conds_1->getAddCursorForPost(); i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
flag = dep->getFlags();
vr = dep->getRegister();
rr = dep->getRealRegister();
if( doesPostConditionExist( vr, rr, flag, true ) )
{
_numPostConditions--;
}
else if( !addPostConditionIfNotAlreadyInserted( vr, rr, flag ) )
{
_numPostConditions--;
}
}
depGroup = conds_2->getPostConditions();
for( i = 0; i < conds_2->getAddCursorForPost(); i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
flag = dep->getFlags();
vr = dep->getRegister();
rr = dep->getRealRegister();
if( doesPostConditionExist( vr, rr, flag, true ) )
{
_numPostConditions--;
}
else if( !addPostConditionIfNotAlreadyInserted( vr, rr, flag ) )
{
_numPostConditions--;
}
}
}
void OMR::Z::RegisterDependencyConditions::resolveSplitDependencies(
TR::CodeGenerator* cg,
TR::Node* node, TR::Node* child,
TR::RegisterPair* regPair, List<TR::Register>& regList,
TR::Register*& reg, TR::Register*& highReg,
TR::Register*& copyReg, TR::Register*& highCopyReg,
TR::Instruction*& iCursor,
TR::RealRegister::RegNum& regNum)
{
TR::Compilation *comp = cg->comp();
TR_Debug * debugObj = cg->getDebug();
bool foundLow = false;
bool foundHigh = false;
if (regPair)
{
foundLow = regList.find(regPair->getLowOrder());
foundHigh = regList.find(regPair->getHighOrder());
}
else
{
foundLow = regList.find(reg);
}
if (foundLow || foundHigh)
{
TR::InstOpCode::Mnemonic opCode;
TR_RegisterKinds kind = reg->getKind();
bool isVector = kind == TR_VRF ? true : false;
if (kind == TR_GPR || kind == TR_FPR)
{
if (regPair)
{
highReg = regPair->getHighOrder();
reg = regPair->getLowOrder();
}
else if (child->getHighGlobalRegisterNumber() > -1)
{
TR_ASSERT( 0,"Long child does not have a register pair\n");
}
}
bool containsInternalPointer = false;
if (reg->getPinningArrayPointer())
{
containsInternalPointer = true;
}
copyReg = (reg->containsCollectedReference() && !containsInternalPointer) ?
cg->allocateCollectedReferenceRegister() :
cg->allocateRegister(kind);
if (containsInternalPointer)
{
copyReg->setContainsInternalPointer();
copyReg->setPinningArrayPointer(reg->getPinningArrayPointer());
}
switch (kind)
{
case TR_GPR:
if (reg->is64BitReg())
{
opCode = TR::InstOpCode::LGR;
}
else
{
opCode = TR::InstOpCode::LR;
}
break;
case TR_FPR:
opCode = TR::InstOpCode::LDR;
break;
case TR_VRF:
opCode = TR::InstOpCode::VLR;
break;
default:
TR_ASSERT( 0, "Invalid register kind.");
}
iCursor = isVector ? generateVRRaInstruction(cg, opCode, node, copyReg, reg, iCursor):
generateRRInstruction (cg, opCode, node, copyReg, reg, iCursor);
reg = copyReg;
if (debugObj)
{
if (isVector)
debugObj->addInstructionComment( toS390VRRaInstruction(iCursor), "VLR=Reg_deps2");
else
debugObj->addInstructionComment( toS390RRInstruction(iCursor), "LR=Reg_deps2");
}
if (highReg)
{
if(kind == TR_GPR)
{
containsInternalPointer = false;
if (highReg->getPinningArrayPointer())
{
containsInternalPointer = true;
}
highCopyReg = (highReg->containsCollectedReference() && !containsInternalPointer) ?
cg->allocateCollectedReferenceRegister() :
cg->allocateRegister(kind);
if (containsInternalPointer)
{
highCopyReg->setContainsInternalPointer();
highCopyReg->setPinningArrayPointer(highReg->getPinningArrayPointer());
}
iCursor = generateRRInstruction(cg, opCode, node, highCopyReg, highReg, iCursor);
highReg = highCopyReg;
}
else // kind == FPR
{
highCopyReg = cg->allocateRegister(kind);
iCursor = generateRRInstruction (cg, opCode, node, highCopyReg, highReg, iCursor);
debugObj->addInstructionComment( toS390RRInstruction(iCursor), "LR=Reg_deps2");
highReg = highCopyReg;
}
}
}
else
{
if (regPair)
{
regList.add(regPair->getHighOrder());
regList.add(regPair->getLowOrder());
}
else
{
regList.add(reg);
}
if (regPair)
{
highReg = regPair->getHighOrder();
reg = regPair->getLowOrder();
}
else if ((child->getHighGlobalRegisterNumber() > -1))
{
TR_ASSERT( 0, "Long child does not have a register pair\n");
}
}
}
TR::RegisterDependencyConditions *OMR::Z::RegisterDependencyConditions::clone(TR::CodeGenerator *cg, int32_t additionalRegDeps)
{
TR::RegisterDependencyConditions *other =
new (cg->trHeapMemory()) TR::RegisterDependencyConditions(_numPreConditions + additionalRegDeps,
_numPostConditions + additionalRegDeps, cg);
int32_t i = 0;
for (i = _numPreConditions-1; i >= 0; --i)
{
TR::RegisterDependency *dep = getPreConditions()->getRegisterDependency(i);
other->getPreConditions()->setDependencyInfo(i, dep->getRegister(), dep->getRealRegister(), dep->getFlags());
}
for (i = _numPostConditions-1; i >= 0; --i)
{
TR::RegisterDependency *dep = getPostConditions()->getRegisterDependency(i);
other->getPostConditions()->setDependencyInfo(i, dep->getRegister(), dep->getRealRegister(), dep->getFlags());
}
other->setAddCursorForPre(_addCursorForPre);
other->setAddCursorForPost(_addCursorForPost);
return other;
}
bool
OMR::Z::RegisterDependencyConditions::refsRegister(TR::Register * r)
{
for (int32_t i = 0; i < _numPreConditions; i++)
{
if (_preConditions->getRegisterDependency(i)->getRegister() == r &&
_preConditions->getRegisterDependency(i)->getRefsRegister())
{
return true;
}
}
for (int32_t j = 0; j < _numPostConditions; j++)
{
if (_postConditions->getRegisterDependency(j)->getRegister() == r &&
_postConditions->getRegisterDependency(j)->getRefsRegister())
{
return true;
}
}
return false;
}
bool
OMR::Z::RegisterDependencyConditions::defsRegister(TR::Register * r)
{
for (int32_t i = 0; i < _numPreConditions; i++)
{
if (_preConditions->getRegisterDependency(i)->getRegister() == r &&
_preConditions->getRegisterDependency(i)->getDefsRegister())
{
return true;
}
}
for (int32_t j = 0; j < _numPostConditions; j++)
{
if (_postConditions->getRegisterDependency(j)->getRegister() == r &&
_postConditions->getRegisterDependency(j)->getDefsRegister())
{
return true;
}
}
return false;
}
bool
OMR::Z::RegisterDependencyConditions::mayDefineRegister(TR::Register * r)
{
for (int32_t j = 0; j < _numPostConditions; j++)
{
if (_postConditions->getRegisterDependency(j)->getRegister() == r &&
_postConditions->getRegisterDependency(j)->getRealRegister() == TR::RealRegister::MayDefine)
{
return true;
}
}
return false;
}
bool
OMR::Z::RegisterDependencyConditions::usesRegister(TR::Register * r)
{
for (int32_t i = 0; i < _numPreConditions; i++)
{
if (_preConditions->getRegisterDependency(i)->getRegister() == r &&
(_preConditions->getRegisterDependency(i)->getRefsRegister() || _preConditions->getRegisterDependency(i)->getDefsRegister()))
{
return true;
}
}
for (int32_t j = 0; j < _numPostConditions; j++)
{
if (_postConditions->getRegisterDependency(j)->getRegister() == r &&
(_postConditions->getRegisterDependency(j)->getRefsRegister() || _postConditions->getRegisterDependency(j)->getDefsRegister()))
{
return true;
}
}
return false;
}
/**
* Reason for oldPreCursor/oldPostCursor:
* When the dependencies have been created by merging new registers into an existing list then only call useRegister for the new registers in the list.
* Calling useRegister again on the existing registers will cause the totalUseCount to be too high and the virtual register will remain set to the real register
* for the entire duration of register assignment.
*/
void
OMR::Z::RegisterDependencyConditions::bookKeepingRegisterUses(TR::Instruction * instr, TR::CodeGenerator * cg, int32_t oldPreCursor, int32_t oldPostCursor)
{
if (instr->getOpCodeValue() != TR::InstOpCode::ASSOCREGS)
{
// We create a register association directive for each dependency
if (cg->enableRegisterAssociations() && !cg->isOutOfLineColdPath())
{
createRegisterAssociationDirective(instr, cg);
}
if (_preConditions != NULL)
{
for (int32_t i = oldPreCursor; i < _addCursorForPre; i++)
{
instr->useRegister(_preConditions->getRegisterDependency(i)->getRegister(), true);
}
}
if (_postConditions != NULL)
{
for (int32_t j = oldPostCursor; j < _addCursorForPost; j++)
{
instr->useRegister(_postConditions->getRegisterDependency(j)->getRegister(), true);
}
}
}
}
uint32_t
TR_S390RegisterDependencyGroup::genBitMapOfAssignableGPRs(TR::CodeGenerator * cg,
uint32_t numberOfRegisters)
{
TR::Machine* machine = cg->machine();
uint32_t availRegMap = machine->genBitMapOfAssignableGPRs();
for (uint32_t i = 0; i < numberOfRegisters; i++)
{
TR::RealRegister::RegNum realReg = _dependencies[i].getRealRegister();
if (TR::RealRegister::isGPR(realReg))
{
availRegMap &= ~machine->getRealRegister(realReg)->getRealRegisterMask();
}
}
return availRegMap;
}
/** \brief
* Checks to ensure that we have enough register pairs available to satisfy all register
* dependencies in the current dependency group and aborts the
* compilation if not enough register pairs are available.
*
* Also, if highword facility is supported, this function checks the type of each register
* dependency condition and sets HPR related flags for future register assignment steps.
*
* \param cg
* The code generator used to query various machine state.
*
* \param currentInstruction
* The instruction on which the register dependency group is attached.
*
* \param availableGPRMap
* The bitmask of available GRP registers.
*
* \param numOfDependencies
* The number of pre or post dependencies in the register dependency group.
**/
void
TR_S390RegisterDependencyGroup::checkRegisterPairSufficiencyAndHPRAssignment(TR::CodeGenerator *cg,
TR::Instruction* currentInstruction,
const uint32_t availableGPRMap,
uint32_t numOfDependencies)
{
TR::Machine* machine = cg->machine();
uint32_t numReqPairs = 0, numAvailPairs = 0;
// Count the number of required pairs to be assigned in reg deps
for (int32_t i = 0; i < numOfDependencies; i++)
{
TR::RealRegister::RegNum realRegI = _dependencies[i].getRealRegister();
TR::Register* virtRegI = _dependencies[i].getRegister();
if (realRegI == TR::RealRegister::EvenOddPair)
numReqPairs++;
if (virtRegI &&
virtRegI->getKind() != TR_FPR &&
virtRegI->getKind() != TR_VRF)
{
// on 64-bit conservatively assume rEP and rRA are going to clobber highword
if (TR::Compiler->target.is64Bit() &&
!(currentInstruction->isLabel() &&
toS390LabelInstruction(currentInstruction)->getLabelSymbol()->isStartOfColdInstructionStream()) &&
(realRegI == cg->getReturnAddressRegister() ||
realRegI == cg->getEntryPointRegister()))
{
virtRegI->setIs64BitReg(true);
}
if (TR::RealRegister::isHPR(realRegI))
{
cg->maskAvailableHPRSpillMask(~(machine->getRealRegister(realRegI)->getRealRegisterMask()));
}
else if (TR::RealRegister::isGPR(realRegI) && virtRegI->is64BitReg())
{
cg->maskAvailableHPRSpillMask(~(machine->getRealRegister(realRegI)->getRealRegisterMask() << 16));
}
}
}
// Count the number of even-odd GPR pairs remaining after deps are filled and breaks early if the
// number of register pairs in available is sufficient.
bool isRegPairSufficient = false;
if (numReqPairs > 0)
{
for (int32_t i = 0; i < NUM_S390_GPR; i += 2)
{
if ((availableGPRMap >> i) & 0x3 == 0x3)
{
numAvailPairs++;
if (numAvailPairs >= numReqPairs)
{
isRegPairSufficient = true;
break;
}
}
}
}
else
{
isRegPairSufficient = true;
}
if (!isRegPairSufficient)
{
TR::Compilation *comp = cg->comp();
if (cg->getDebug())
{
trfprintf(comp->getOutFile(), "\nNum AVAIL PAIRS %d, Num REQ PAIRS %d\n", numAvailPairs, numReqPairs);
trfprintf(comp->getOutFile(), "AVAIL REG MAP %x\n", availableGPRMap);
cg->getDebug()->printRegisterDependencies(comp->getOutFile(), this, numOfDependencies);
}
TR_ASSERT( 0, "checkDependencyGroup::Insufficient available pairs to satisfy all reg deps.\n");
comp->failCompilation<TR::CompilationException>("checkDependencyGroup::Insufficient available pairs to satisfy all reg deps, abort compilation\n");
}
}
/**
*
* \brief
* Performs pairwise checks in dependencies to find duplicates
*
* 1. If the duplicated registers are virtual registers or real registers, assert fail.
* 2. If the duplicated registers are GPR/HPR dependencies, remove the duplicates.
*
* \param cg
* The CodeGenerator object used to query machine states
*
* \param numOfDependencies
* The number of register dependency conditions to examine.
*/
void
TR_S390RegisterDependencyGroup::checkRegisterDependencyDuplicates(TR::CodeGenerator* cg,
const uint32_t numOfDependencies)
{
TR::Compilation *comp = cg->comp();
if (numOfDependencies <= 1)
return;
for (uint32_t i = 0; i < numOfDependencies - 1; ++i)
{
TR::Register* virtRegI = _dependencies[i].getRegister();
TR::Register* virtRegJ;
TR::RealRegister::RegNum realRegI = _dependencies[i].getRealRegister();
TR::RealRegister::RegNum realRegJ;
for (uint32_t j = i + 1; j < numOfDependencies; ++j)
{
virtRegJ = _dependencies[j].getRegister();
realRegJ = _dependencies[j].getRealRegister();
if (virtRegI == virtRegJ
&& realRegI != TR::RealRegister::SpilledReg
&& realRegJ != TR::RealRegister::SpilledReg)
{
TR_ASSERT(false, "Virtual register duplicate found in a register dependency\n");
}
if (realRegI == realRegJ &&
TR::RealRegister::isRealReg(realRegI))
{
TR_ASSERT(false, "Real register duplicate found in a register dependency\n");
}
if (realRegI == realRegJ + (TR::RealRegister::FirstHPR - TR::RealRegister::FirstGPR) &&
virtRegI->isPlaceholderReg() &&
virtRegJ->is64BitReg() &&
virtRegJ->getKind() != TR_FPR &&
virtRegJ->getKind() != TR_VRF)
{
traceMsg(comp, "Remove duplicate GPR (%s) / HPR (%s) register dependency\n", virtRegJ->getRegisterName(comp), virtRegI->getRegisterName(comp));
_dependencies[i].setRealRegister(TR::RealRegister::NoReg);
}
if (realRegJ == realRegI + (TR::RealRegister::FirstHPR - TR::RealRegister::FirstGPR) &&
virtRegJ->isPlaceholderReg() &&
virtRegI->is64BitReg() &&
virtRegI->getKind() != TR_FPR &&
virtRegI->getKind() != TR_VRF)
{
traceMsg(comp, "Remove duplicate GPR (%s) / HPR (%s) register dependency\n", virtRegI->getRegisterName(comp), virtRegJ->getRegisterName(comp));
_dependencies[j].setRealRegister(TR::RealRegister::NoReg);
}
}
}
}
/**
*
* \brief
* Generates a uint32_t bit map for available GPR registers.
* This function also checks to make sure that there are enough register pairs
* for assignment, and that there are no duplicates in real, virtual, and
* HPR registers.
*
* \param cg
* The CodeGenerator object used to query machine states
*
* \param currentInstruction
* The current instruction on which the register dependency group is attached.
*
* \param numOfDependencies
* The number of register dependency conditions to examine.
*
* \return
* a bit mask of available GPR map.
* Bit is set to 1 if the GPR is available, and 0 otherwise.
*/
uint32_t
TR_S390RegisterDependencyGroup::checkDependencyGroup(TR::CodeGenerator * cg,
TR::Instruction * currentInstruction,
uint32_t numOfDependencies)
{
// availableGPRMap is a bitmap of all available (not locked) GPRs on the machine
// excluding the real registers already specified in the _dependencies.
uint32_t availableGPRMap = genBitMapOfAssignableGPRs(cg, numOfDependencies);
cg->setAvailableHPRSpillMask(0xFFFF0000);
///// Check the number of register pairs. The compilation may fail due to insufficient register pairs
checkRegisterPairSufficiencyAndHPRAssignment(cg, currentInstruction, availableGPRMap,
numOfDependencies);
///// Check and remove duplicates
checkRegisterDependencyDuplicates(cg, numOfDependencies);
return availableGPRMap;
}
void
TR_S390RegisterDependencyGroup::assignRegisters(TR::Instruction *currentInstruction,
TR_RegisterKinds kindToBeAssigned,
uint32_t numOfDependencies,
TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR::Machine *machine = cg->machine();
TR::Register * virtReg;
TR::RealRegister::RegNum dependentRegNum;
TR::RealRegister * dependentRealReg, * assignedRegister;
int32_t i, j;
bool changed;
uint32_t availRegMask = checkDependencyGroup(cg, currentInstruction, numOfDependencies);
bool highRegSpill = false;
if (!comp->getOption(TR_DisableOOL))
{
for (i = 0; i< numOfDependencies; i++)
{
virtReg = _dependencies[i].getRegister();
dependentRegNum = _dependencies[i].getRealRegister();
if (dependentRegNum == TR::RealRegister::SpilledReg && !_dependencies[i].getRegister()->getRealRegister())
{
TR_ASSERT_FATAL(virtReg->getBackingStorage() != NULL, "Spilled virtual register on dependency list does not have backing storage");
TR::RealRegister * spilledHPR = NULL;
if (virtReg->getKind() != TR_FPR && virtReg->getKind() != TR_VRF && virtReg->getAssignedRealRegister() == NULL)
{
spilledHPR = cg->machine()->findVirtRegInHighWordRegister(virtReg);
cg->traceRegisterAssignment (" \nOOL: found %R spilled to %R", virtReg, spilledHPR);
}
if (virtReg->getAssignedRealRegister() || spilledHPR)
{
// this happens when the register was first spilled in main line path then was reverse spilled
// and assigned to a real register in OOL path. We protected the backing store when doing
// the reverse spill so we could re-spill to the same slot now
TR::Node *currentNode = currentInstruction->getNode();
TR::RealRegister *assignedReg;
if (spilledHPR)
assignedReg = spilledHPR;
else
assignedReg = toRealRegister(virtReg->getAssignedRegister());
cg->traceRegisterAssignment ("\nOOL: Found %R spilled in main line and reused inside OOL", virtReg);
TR::MemoryReference * tempMR = generateS390MemoryReference(currentNode, virtReg->getBackingStorage()->getSymbolReference(), cg);
TR::InstOpCode::Mnemonic opCode;
TR_RegisterKinds rk = virtReg->getKind();
switch (rk)
{
case TR_GPR:
if (virtReg->is64BitReg())
{
opCode = TR::InstOpCode::LG;
}
else
{
opCode = TR::InstOpCode::L;
}
break;
case TR_FPR:
opCode = TR::InstOpCode::LD;
break;
case TR_VRF:
opCode = TR::InstOpCode::VL;
break;
default:
TR_ASSERT( 0, "\nRegister kind not supported in OOL spill\n");
break;
}
if (rk != TR_FPR && rk != TR_VRF)
{
if (assignedReg->isHighWordRegister())
{
// virtReg was spilled to an HPR and now we need it spilled to stack
opCode = TR::InstOpCode::LFH;
if (virtReg->is64BitReg())
{
TR_ASSERT(virtReg->containsCollectedReference(),
"virtReg is assigned to HPR but is not a spilled compress pointer");
// we need to decompress pointer
tempMR = generateS390MemoryReference(*tempMR, 4, cg);
virtReg->setSpilledToHPR(false);
}
}
}
bool isVector = rk == TR_VRF ? true : false;
TR::Instruction *inst = isVector ? generateVRXInstruction(cg, opCode, currentNode, assignedReg, tempMR, 0, currentInstruction) :
generateRXInstruction (cg, opCode, currentNode, assignedReg, tempMR, currentInstruction);
cg->traceRAInstruction(inst);
assignedReg->setAssignedRegister(NULL);
virtReg->setAssignedRegister(NULL);
assignedReg->setState(TR::RealRegister::Free);
if (virtReg->is64BitReg() && rk != TR_FPR && rk != TR_VRF)
{
assignedReg->getHighWordRegister()->setAssignedRegister(NULL);
assignedReg->getHighWordRegister()->setState(TR::RealRegister::Free);
}
}
// now we are leaving the OOL sequence, anything that was previously spilled in OOL hot path or main line
// should be considered as mainline spill for the next OOL sequence.
virtReg->getBackingStorage()->setMaxSpillDepth(1);
}
// we also need to free up all locked backing storage if we are exiting the OOL during backwards RA assignment
else if (currentInstruction->isLabel() && virtReg->getAssignedRealRegister())
{
TR_BackingStore * location = virtReg->getBackingStorage();
TR_RegisterKinds rk = virtReg->getKind();
int32_t dataSize;
if (toS390LabelInstruction(currentInstruction)->getLabelSymbol()->isStartOfColdInstructionStream() &&
location)
{
traceMsg (comp,"\nOOL: Releasing backing storage (%p)\n", location);
if (rk == TR_GPR)
dataSize = TR::Compiler->om.sizeofReferenceAddress();
else if (rk == TR_VRF)
dataSize = 16; // Will change to 32 in a few years..
else
dataSize = 8;
location->setMaxSpillDepth(0);
cg->freeSpill(location,dataSize,0);
virtReg->setBackingStorage(NULL);
}
}
}
}
uint32_t numGPRs = 0;
uint32_t numHPRs = 0;
uint32_t numFPRs = 0;
uint32_t numVRFs = 0;
// Used to do lookups using real register numbers
OMR::RegisterDependencyMap map(_dependencies, numOfDependencies);
for (i = 0; i < numOfDependencies; i++)
{
map.addDependency(_dependencies[i], i);