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OMRTreeEvaluator.cpp
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OMRTreeEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <algorithm>
#include <assert.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/RecognizedMethods.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/RegisterRematerializationInfo.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/IO.hpp"
#include "env/ObjectModel.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/AutomaticSymbol.hpp"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "infra/List.hpp"
#include "infra/CfgEdge.hpp"
#include "ras/Debug.hpp"
#include "ras/DebugCounter.hpp"
#include "runtime/Runtime.hpp"
#include "x/codegen/HelperCallSnippet.hpp"
#include "x/codegen/OutlinedInstructions.hpp"
#include "x/codegen/RegisterRematerialization.hpp"
#include "x/codegen/X86Evaluator.hpp"
#include "x/codegen/X86Instruction.hpp"
#include "x/codegen/X86Ops.hpp"
#include "x/codegen/BinaryCommutativeAnalyser.hpp"
#include "x/codegen/SubtractAnalyser.hpp"
class TR_OpaqueClassBlock;
class TR_OpaqueMethodBlock;
extern bool existsNextInstructionToTestFlags(TR::Instruction *startInstr,
uint8_t testMask);
TR::Register *OMR::X86::TreeEvaluator::ifxcmpoEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::ILOpCodes opCode = node->getOpCodeValue();
TR_ASSERT((opCode == TR::ificmno) || (opCode == TR::ificmnno) ||
(opCode == TR::iflcmno) || (opCode == TR::iflcmnno) ||
(opCode == TR::ificmpo) || (opCode == TR::ificmpno) ||
(opCode == TR::iflcmpo) || (opCode == TR::iflcmpno), "invalid opcode");
bool nodeIs64Bit = TR::TreeEvaluator::getNodeIs64Bit(node->getFirstChild(), cg);
bool reverseBranch = (opCode == TR::ificmnno) || (opCode == TR::iflcmnno) || (opCode == TR::ificmpno) || (opCode == TR::iflcmpno);
TR::Register* rs1 = cg->evaluate(node->getFirstChild());
TR::Register* rs2 = cg->evaluate(node->getSecondChild());
if ((opCode == TR::ificmno) || (opCode == TR::ificmnno) ||
(opCode == TR::iflcmno) || (opCode == TR::iflcmnno))
{
TR::Register* tmp = cg->allocateRegister();
generateRegRegInstruction(MOVRegReg(nodeIs64Bit), node, tmp, rs1, cg);
generateRegRegInstruction(ADDRegReg(nodeIs64Bit), node, tmp, rs2, cg);
cg->stopUsingRegister(tmp);
}
else
generateRegRegInstruction(CMPRegReg(nodeIs64Bit), node, rs1, rs2, cg);
generateConditionalJumpInstruction(reverseBranch ? JNO4 : JO4, node, cg, true);
cg->decReferenceCount(node->getFirstChild());
cg->decReferenceCount(node->getSecondChild());
return NULL;
}
TR::Register *OMR::X86::TreeEvaluator::intOrLongClobberEvaluate(TR::Node *node, bool nodeIs64Bit, TR::CodeGenerator *cg)
{
// TODO:AMD64: This belongs in CodeGenerator. In fact, this whole clobberEvaluate interface needs another look.
if (nodeIs64Bit)
{
TR_ASSERT(TR::TreeEvaluator::getNodeIs64Bit(node, cg), "nodeIs64Bit must be consistent with node size");
return cg->longClobberEvaluate(node);
}
else
{
TR_ASSERT(!TR::TreeEvaluator::getNodeIs64Bit(node, cg), "nodeIs64Bit must be consistent with node size");
return cg->intClobberEvaluate(node);
}
}
TR::Instruction *OMR::X86::TreeEvaluator::compareGPMemoryToImmediate(TR::Node *node,
TR::MemoryReference *mr,
int32_t value,
TR::CodeGenerator *cg)
{
// On IA32, this is called to do half of an 8-byte compare, so even though
// the node is 64 bit, we should do a 32-bit compare
bool is64Bit = cg->comp()->target().is64Bit()? TR::TreeEvaluator::getNodeIs64Bit(node->getFirstChild(), cg) : false;
TR_X86OpCodes cmpOp = (value >= -128 && value <= 127) ? CMPMemImms(is64Bit) : CMPMemImm4(is64Bit);
TR::Instruction *instr = generateMemImmInstruction(cmpOp, node, mr, value, cg);
cg->setImplicitExceptionPoint(instr);
return instr;
}
void OMR::X86::TreeEvaluator::compareGPRegisterToImmediate(TR::Node *node,
TR::Register *cmpRegister,
int32_t value,
TR::CodeGenerator *cg)
{
// On IA32, this is called to do half of an 8-byte compare, so even though
// the node is 64 bit, we should do a 32-bit compare
bool is64Bit = cg->comp()->target().is64Bit()? TR::TreeEvaluator::getNodeIs64Bit(node->getFirstChild(), cg) : false;
TR_X86OpCodes cmpOp = (value >= -128 && value <= 127) ? CMPRegImms(is64Bit) : CMPRegImm4(is64Bit);
generateRegImmInstruction(cmpOp, node, cmpRegister, value, cg);
}
void OMR::X86::TreeEvaluator::compareGPRegisterToImmediateForEquality(TR::Node *node,
TR::Register *cmpRegister,
int32_t value,
TR::CodeGenerator *cg)
{
// On IA32, this is called to do half of an 8-byte compare, so even though
// the node is 64 bit, we should do a 32-bit compare
bool is64Bit = cg->comp()->target().is64Bit()? TR::TreeEvaluator::getNodeIs64Bit(node->getFirstChild(), cg) : false;
TR_X86OpCodes cmpOp = (value >= -128 && value <= 127) ? CMPRegImms(is64Bit) : CMPRegImm4(is64Bit);
if (value==0)
generateRegRegInstruction(TESTRegReg(is64Bit), node, cmpRegister, cmpRegister, cg);
else
generateRegImmInstruction(cmpOp, node, cmpRegister, value, cg);
}
TR::Instruction *OMR::X86::TreeEvaluator::insertLoadConstant(TR::Node *node,
TR::Register *target,
intptr_t value,
TR_RematerializableTypes type,
TR::CodeGenerator *cg,
TR::Instruction *currentInstruction)
{
TR::Compilation *comp = cg->comp();
static const TR_X86OpCodes ops[TR_NumRematerializableTypes+1][3] =
// load 0 load -1 load c
{ { BADIA32Op, BADIA32Op, BADIA32Op }, // LEA; should not seen here
{ XOR4RegReg, OR4RegImms, MOV4RegImm4 }, // Byte constant
{ XOR4RegReg, OR4RegImms, MOV4RegImm4 }, // Short constant
{ XOR4RegReg, OR4RegImms, MOV4RegImm4 }, // Char constant
{ XOR4RegReg, OR4RegImms, MOV4RegImm4 }, // Int constant
{ XOR4RegReg, OR4RegImms, MOV4RegImm4 }, // 32-bit address constant
{ XOR4RegReg, OR8RegImms, BADIA32Op } }; // Long address constant; MOVs handled specially
enum { XOR = 0, OR = 1, MOV = 2 };
bool is64Bit = false;
int opsRow = type;
if (cg->comp()->target().is64Bit())
{
if (type == TR_RematerializableAddress)
{
// Treat 64-bit addresses as longs
opsRow++;
is64Bit = true;
}
else
{
is64Bit = (type == TR_RematerializableLong);
}
}
else
{
TR_ASSERT(type != TR_RematerializableLong, "Longs are rematerialized as pairs of ints on IA32");
}
TR_ExternalRelocationTargetKind reloKind = TR_NoRelocation;
if (cg->profiledPointersRequireRelocation() && node && node->getOpCodeValue() == TR::aconst &&
(node->isClassPointerConstant() || node->isMethodPointerConstant()))
{
if (node->isClassPointerConstant())
reloKind = TR_ClassPointer;
else if (node->isMethodPointerConstant())
reloKind = TR_MethodPointer;
else
TR_ASSERT(0, "Unexpected node, don't know how to relocate");
}
if (currentInstruction)
{
// Optimized loads inserted arbitrarily into the instruction stream must be checked
// to ensure they don't modify any eflags needed by surrounding instructions.
//
if ((value == 0 || value == -1))
{
uint8_t EFlags = TR_X86OpCode::getModifiedEFlags(ops[opsRow][((value == 0) ? XOR : OR)]);
if (existsNextInstructionToTestFlags(currentInstruction, EFlags) || cg->requiresCarry())
{
// Can't alter flags, so must use MOV. Fall through.
}
else if (value == 0)
return generateRegRegInstruction(currentInstruction, ops[opsRow][XOR], target, target, cg);
else if (value == -1)
return generateRegImmInstruction(currentInstruction, ops[opsRow][OR], target, (uint32_t)-1, cg);
}
// No luck optimizing this. Just use a MOV
//
TR::Instruction *movInstruction = NULL;
if (is64Bit)
{
if (cg->constantAddressesCanChangeSize(node) && node && node->getOpCodeValue() == TR::aconst &&
(node->isClassPointerConstant() || node->isMethodPointerConstant()))
{
movInstruction = generateRegImm64Instruction(currentInstruction, MOV8RegImm64, target, value, cg, reloKind);
}
else if (IS_32BIT_UNSIGNED(value))
{
// zero-extended 4-byte MOV
movInstruction = generateRegImmInstruction(currentInstruction, MOV4RegImm4, target, value, cg, reloKind);
}
else if (IS_32BIT_SIGNED(value)) // TODO:AMD64: Is there some way we could get RIP too?
{
movInstruction = generateRegImmInstruction(currentInstruction, MOV8RegImm4, target, value, cg, reloKind);
}
else
{
movInstruction = generateRegImm64Instruction(currentInstruction, MOV8RegImm64, target, value, cg, reloKind);
}
}
else
{
movInstruction = generateRegImmInstruction(currentInstruction, ops[opsRow][MOV], target, value, cg, reloKind);
}
// HCR register PIC site in TR::TreeEvaluator::insertLoadConstant
TR::Symbol *symbol = NULL;
if (node && node->getOpCode().hasSymbolReference())
symbol = node->getSymbol();
bool isPICCandidate = symbol ? target && symbol->isStatic() && symbol->isClassObject() : false;
if (isPICCandidate && cg->wantToPatchClassPointer((TR_OpaqueClassBlock*)value, node))
comp->getStaticHCRPICSites()->push_front(movInstruction);
if (target && node &&
node->getOpCodeValue() == TR::aconst &&
node->isClassPointerConstant() &&
(cg->fe()->isUnloadAssumptionRequired((TR_OpaqueClassBlock *) node->getAddress(),
comp->getCurrentMethod()) ||
cg->profiledPointersRequireRelocation()))
{
comp->getStaticPICSites()->push_front(movInstruction);
}
if (target && node &&
node->getOpCodeValue() == TR::aconst &&
node->isMethodPointerConstant() &&
(cg->fe()->isUnloadAssumptionRequired(cg->fe()->createResolvedMethod(cg->trMemory(), (TR_OpaqueMethodBlock *) node->getAddress(), comp->getCurrentMethod())->classOfMethod(), comp->getCurrentMethod()) ||
cg->profiledPointersRequireRelocation()))
{
traceMsg(comp, "Adding instr %p to MethodPICSites for node %p\n", movInstruction, node);
comp->getStaticMethodPICSites()->push_front(movInstruction);
}
return movInstruction;
}
else
{
// constant loads between a compare and a branch cannot clobber the EFLAGS register
bool canClobberEFLAGS = !(cg->getCurrentEvaluationTreeTop()->getNode()->getOpCode().isIf() || cg->requiresCarry());
if (value == 0 && canClobberEFLAGS)
{
return generateRegRegInstruction(ops[opsRow][XOR], node, target, target, cg);
}
else if (value == -1 && canClobberEFLAGS)
{
return generateRegImmInstruction(ops[opsRow][OR], node, target, (uint32_t)-1, cg);
}
else
{
TR::Instruction *movInstruction = NULL;
if (is64Bit)
{
if (cg->constantAddressesCanChangeSize(node) && node && node->getOpCodeValue() == TR::aconst &&
(node->isClassPointerConstant() || node->isMethodPointerConstant()))
{
movInstruction = generateRegImm64Instruction(MOV8RegImm64, node, target, value, cg, reloKind);
}
else if (IS_32BIT_UNSIGNED(value))
{
// zero-extended 4-byte MOV
movInstruction = generateRegImmInstruction(MOV4RegImm4, node, target, value, cg, reloKind);
}
else if (IS_32BIT_SIGNED(value)) // TODO:AMD64: Is there some way we could get RIP too?
{
movInstruction = generateRegImmInstruction(MOV8RegImm4, node, target, value, cg, reloKind);
}
else
{
movInstruction = generateRegImm64Instruction(MOV8RegImm64, node, target, value, cg, reloKind);
}
}
else
{
movInstruction = generateRegImmInstruction(ops[opsRow][MOV], node, target, value, cg, reloKind);
}
// HCR register PIC site in TR::TreeEvaluator::insertLoadConstant
TR::Symbol *symbol = NULL;
if (node && node->getOpCode().hasSymbolReference())
symbol = node->getSymbol();
bool isPICCandidate = symbol ? target && symbol->isStatic() && symbol->isClassObject() : false;
if (isPICCandidate && comp->getOption(TR_EnableHCR))
{
comp->getStaticHCRPICSites()->push_front(movInstruction);
}
if (target &&
node &&
node->getOpCodeValue() == TR::aconst &&
node->isClassPointerConstant() &&
(cg->fe()->isUnloadAssumptionRequired((TR_OpaqueClassBlock *) node->getAddress(),
comp->getCurrentMethod()) ||
cg->profiledPointersRequireRelocation()))
{
comp->getStaticPICSites()->push_front(movInstruction);
}
if (target && node &&
node->getOpCodeValue() == TR::aconst &&
node->isMethodPointerConstant() &&
(cg->fe()->isUnloadAssumptionRequired(cg->fe()->createResolvedMethod(cg->trMemory(), (TR_OpaqueMethodBlock *) node->getAddress(), comp->getCurrentMethod())->classOfMethod(), comp->getCurrentMethod()) ||
cg->profiledPointersRequireRelocation()))
{
traceMsg(comp, "Adding instr %p to MethodPICSites for node %p\n", movInstruction, node);
comp->getStaticMethodPICSites()->push_front(movInstruction);
}
return movInstruction;
}
}
}
TR::Register *OMR::X86::TreeEvaluator::loadConstant(TR::Node * node, intptr_t value, TR_RematerializableTypes type, TR::CodeGenerator *cg, TR::Register *targetRegister)
{
if (targetRegister == NULL)
{
targetRegister = cg->allocateRegister();
}
TR::Instruction *instr = TR::TreeEvaluator::insertLoadConstant(node, targetRegister, value, type, cg);
if (cg->enableRematerialisation())
{
if (node && node->getOpCode().hasSymbolReference() && node->getSymbol() && node->getSymbol()->isClassObject())
(TR::Compiler->om.generateCompressedObjectHeaders() || cg->comp()->target().is32Bit()) ? type = TR_RematerializableInt : type = TR_RematerializableLong;
setDiscardableIfPossible(type, targetRegister, node, instr, value, cg);
}
return targetRegister;
}
TR::Instruction *
OMR::X86::TreeEvaluator::insertLoadMemory(
TR::Node *node,
TR::Register *target,
TR::MemoryReference *tempMR,
TR_RematerializableTypes type,
TR::CodeGenerator *cg,
TR::Instruction *currentInstruction)
{
TR::Compilation *comp = cg->comp();
static const TR_X86OpCodes ops[TR_NumRematerializableTypes] =
{
LEARegMem(), // Load Effective Address
L1RegMem, // Byte
L2RegMem, // Short
L2RegMem, // Char
L4RegMem, // Int
L4RegMem, // Address (64-bit addresses handled specailly below)
L8RegMem, // Long
};
TR_X86OpCodes opCode = ops[type];
if (cg->comp()->target().is64Bit())
{
if (type == TR_RematerializableAddress)
{
opCode = L8RegMem;
if (node && node->getOpCode().hasSymbolReference() &&
TR::Compiler->om.generateCompressedObjectHeaders())
{
if (node->getSymbol()->isClassObject() ||
(node->getSymbolReference() == comp->getSymRefTab()->findVftSymbolRef()))
opCode = L4RegMem;
}
}
}
else
TR_ASSERT(type != TR_RematerializableLong, "Longs are rematerialized as pairs of ints on IA32");
// If we are trying to rematerialize a byte of mem into a non-byte register,
// use movzx rather than a simple move
//
if (type == TR_RematerializableByte && target->getAssignedRealRegister())
{
TR::RealRegister::RegNum r = toRealRegister(target->getAssignedRealRegister())->getRegisterNumber();
if (r > TR::RealRegister::Last8BitGPR)
opCode = MOVZXReg4Mem1;
}
TR::Instruction *i;
if (currentInstruction)
{
i = generateRegMemInstruction(currentInstruction, opCode, target, tempMR, cg);
}
else
{
i = generateRegMemInstruction(opCode, node, target, tempMR, cg);
}
// HCR in insertLoadMemory to do: handle unresolved data
if (node && node->getSymbol()->isStatic() && node->getSymbol()->isClassObject() && cg->wantToPatchClassPointer(NULL, node))
{
// I think this has no effect; i has no immediate source operand.
comp->getStaticHCRPICSites()->push_front(i);
}
return i;
}
// If an unresolved data reference is followed immediately by an unconditional
// branch instruction then it is possible that the branch displacement could
// change after the unresolved data snippet has been generated (due to a forward
// reference). Insert padding such that the bytes copied from the mainline
// code do not change.
//
// The padding is always inserted for certain classes of unresolved references
// because it is difficult to accurately predict when the following instruction
// will actually be one with a forward reference. This could potentially be
// solved cleaner by running relocation processing after snippet generation.
//
// Also if the unresolved data reference is immediately followed by another patchable
// instruction (such as a virtual guard nop) with a different alignment boundary size
// then there could be an overlap between the two codes being patching, unless
// further padding is inserted.
//
void OMR::X86::TreeEvaluator::padUnresolvedDataReferences(
TR::Node *node,
TR::SymbolReference &symRef,
TR::CodeGenerator *cg)
{
TR_ASSERT(symRef.isUnresolved(), "expecting an unresolved symbol");
TR::Compilation *comp = cg->comp();
uint8_t padBytes = 0;
if (cg->comp()->target().is32Bit())
padBytes = 2; // needs at least 2 bytes as we are patching 8 bytes at a time
else
{
TR::Symbol *symbol = symRef.getSymbol();
if (symbol && symbol->isShadow())
{
padBytes = 2;
}
}
if (padBytes > 0)
{
TR::Instruction *pi = generatePaddingInstruction(padBytes, node, cg);
if (comp->getOption(TR_TraceCG))
traceMsg(comp, "adding %d pad bytes following unresolved data instruction %p\n", padBytes, pi->getPrev());
}
}
TR::Register *
OMR::X86::TreeEvaluator::loadMemory(
TR::Node *node,
TR::MemoryReference *sourceMR,
TR_RematerializableTypes type,
bool markImplicitExceptionPoint,
TR::CodeGenerator *cg)
{
TR::Register *targetRegister = cg->allocateRegister();
TR::Instruction *instr;
instr = TR::TreeEvaluator::insertLoadMemory(node, targetRegister, sourceMR, type, cg);
TR::SymbolReference& symRef = sourceMR->getSymbolReference();
if (symRef.isUnresolved())
{
TR::TreeEvaluator::padUnresolvedDataReferences(node, symRef, cg);
}
if (cg->enableRematerialisation())
{
if (node && node->getOpCode().hasSymbolReference() && node->getSymbol() && node->getSymbol()->isClassObject())
(TR::Compiler->om.generateCompressedObjectHeaders() || cg->comp()->target().is32Bit()) ? type = TR_RematerializableInt : type = TR_RematerializableLong;
setDiscardableIfPossible(type, targetRegister, node, instr, sourceMR, cg);
}
if (markImplicitExceptionPoint)
cg->setImplicitExceptionPoint(instr);
return targetRegister;
}
void OMR::X86::TreeEvaluator::removeLiveDiscardableStatics(TR::CodeGenerator *cg)
{
TR_ASSERT(cg->supportsStaticMemoryRematerialization(),
"should not be called without rematerialisation of statics\n");
TR::Compilation *comp = cg->comp();
for(auto iterator = cg->getLiveDiscardableRegisters().begin(); iterator != cg->getLiveDiscardableRegisters().end(); )
{
if ((*iterator)->getRematerializationInfo()->isRematerializableFromMemory() &&
(*iterator)->getRematerializationInfo()->getSymbolReference()->getSymbol()->isStatic())
{
TR::Register* regCursor = *iterator;
iterator = cg->getLiveDiscardableRegisters().erase(iterator);
regCursor->resetIsDiscardable();
if (debug("dumpRemat"))
{
diagnostic("\n---> Deleting static discardable candidate %s at %s instruction " POINTER_PRINTF_FORMAT,
regCursor->getRegisterName(comp),
cg->getAppendInstruction()->getOpCode().getOpCodeName(cg),
cg->getAppendInstruction());
}
}
else
++iterator;
}
}
TR::Register *OMR::X86::TreeEvaluator::performIload(TR::Node *node, TR::MemoryReference *sourceMR, TR::CodeGenerator *cg)
{
TR::Register *reg = TR::TreeEvaluator::loadMemory(node, sourceMR, TR_RematerializableInt, node->getOpCode().isIndirect(), cg);
node->setRegister(reg);
return reg;
}
// also handles iaload
TR::Register *OMR::X86::TreeEvaluator::aloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::MemoryReference *sourceMR = generateX86MemoryReference(node, cg);
TR::Register *reg = TR::TreeEvaluator::loadMemory(node, sourceMR, TR_RematerializableAddress, node->getOpCode().isIndirect(), cg);
reg->setMemRef(sourceMR);
TR::Compilation *comp = cg->comp();
if (!node->getSymbolReference()->isUnresolved() &&
(node->getSymbolReference()->getSymbol()->getKind() == TR::Symbol::IsShadow) &&
(node->getSymbolReference()->getCPIndex() >= 0) &&
(comp->getMethodHotness()>=scorching))
{
int32_t len;
const char *fieldName = node->getSymbolReference()->getOwningMethod(comp)->fieldSignatureChars(
node->getSymbolReference()->getCPIndex(), len);
if (fieldName && strstr(fieldName, "Ljava/lang/String;"))
{
generateMemInstruction(PREFETCHT0, node, generateX86MemoryReference(reg, 0, cg), cg);
}
}
#ifdef J9_PROJECT_SPECIFIC
if (node->getSymbolReference() == comp->getSymRefTab()->findVftSymbolRef())
TR::TreeEvaluator::generateVFTMaskInstruction(node, reg, cg);
#endif
if (node->getSymbolReference()->getSymbol()->isNotCollected())
{
if (node->getSymbolReference()->getSymbol()->isInternalPointer())
{
reg->setContainsInternalPointer();
reg->setPinningArrayPointer(node->getSymbolReference()->getSymbol()->castToInternalPointerAutoSymbol()->getPinningArrayPointer());
}
}
else
{
if (node->getSymbolReference()->getSymbol()->isInternalPointer())
{
reg->setContainsInternalPointer();
reg->setPinningArrayPointer(node->getSymbolReference()->getSymbol()->castToInternalPointerAutoSymbol()->getPinningArrayPointer());
}
else
{
reg->setContainsCollectedReference();
}
}
node->setRegister(reg);
sourceMR->decNodeReferenceCounts(cg);
return reg;
}
// generate the null test instructions if required
//
bool OMR::X86::TreeEvaluator::genNullTestSequence(TR::Node *node,
TR::Register *opReg,
TR::Register *targetReg,
TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
if (comp->useCompressedPointers() &&
node->containsCompressionSequence())
{
TR::Node *n = node;
bool isNonZero = false;
if (n->isNonZero())
isNonZero = true;
if (n->getOpCodeValue() == TR::ladd)
{
if (n->getFirstChild()->isNonZero())
isNonZero = true;
if (n->getFirstChild()->getOpCodeValue() == TR::iu2l ||
n->getFirstChild()->getOpCode().isShift())
{
if (n->getFirstChild()->getFirstChild()->isNonZero())
isNonZero = true;
}
}
if (!isNonZero)
{
if (opReg != targetReg)
generateRegRegInstruction(MOVRegReg(), node, targetReg, opReg, cg);
TR::Register *tempReg = cg->allocateRegister();
// addition of the negative number should result in 0
//
int64_t value = -(int64_t)TR::Compiler->vm.heapBaseAddress();
generateRegImm64Instruction(MOV8RegImm64, node, tempReg, value, cg);
if (n->getFirstChild()->getOpCode().isShift() && n->getFirstChild()->getFirstChild()->getRegister())
{
TR::Register * r = n->getFirstChild()->getFirstChild()->getRegister();
generateRegRegInstruction(TESTRegReg(), node, r, r, cg);
}
else
{
generateRegRegInstruction(TESTRegReg(), node, opReg, opReg, cg);
}
generateRegRegInstruction(CMOVERegReg(), node, targetReg, tempReg, cg);
cg->stopUsingRegister(tempReg);
return true;
}
}
return false;
}
// also handles iiload
TR::Register *OMR::X86::TreeEvaluator::iloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::MemoryReference *sourceMR = generateX86MemoryReference(node, cg);
TR::Register *reg = TR::TreeEvaluator::performIload(node, sourceMR, cg);
reg->setMemRef(sourceMR);
sourceMR->decNodeReferenceCounts(cg);
TR::Compilation *comp = cg->comp();
if (comp->useCompressedPointers() &&
(node->getOpCode().hasSymbolReference() &&
node->getSymbolReference()->getSymbol()->getDataType() == TR::Address))
{
if (!node->getSymbolReference()->isUnresolved() &&
(node->getSymbolReference()->getSymbol()->getKind() == TR::Symbol::IsShadow) &&
(node->getSymbolReference()->getCPIndex() >= 0) &&
(comp->getMethodHotness()>=scorching))
{
int32_t len;
const char *fieldName = node->getSymbolReference()->getOwningMethod(comp)->fieldSignatureChars(
node->getSymbolReference()->getCPIndex(), len);
if (fieldName && strstr(fieldName, "Ljava/lang/String;"))
{
generateMemInstruction(PREFETCHT0, node, generateX86MemoryReference(reg, 0, cg), cg);
}
}
}
return reg;
}
// also handles ibload
TR::Register *OMR::X86::TreeEvaluator::bloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::MemoryReference *sourceMR = generateX86MemoryReference(node, cg);
TR::Register *reg = TR::TreeEvaluator::loadMemory(node, sourceMR, TR_RematerializableByte, node->getOpCode().isIndirect(), cg);
reg->setMemRef(sourceMR);
node->setRegister(reg);
if (cg->enableRegisterInterferences())
cg->getLiveRegisters(TR_GPR)->setByteRegisterAssociation(reg);
sourceMR->decNodeReferenceCounts(cg);
return reg;
}
// also handles isload and icload
TR::Register *OMR::X86::TreeEvaluator::sloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::MemoryReference *sourceMR = generateX86MemoryReference(node, cg);
TR::Register *reg = TR::TreeEvaluator::loadMemory(node, sourceMR, TR_RematerializableShort, node->getOpCode().isIndirect(), cg);
reg->setMemRef(sourceMR);
node->setRegister(reg);
sourceMR->decNodeReferenceCounts(cg);
return reg;
}
TR::Register *
OMR::X86::TreeEvaluator::fwrtbarEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
// The wrtbar IL op represents a store with side effects.
// Currently we don't use the side effect node. So just evaluate it and decrement the reference count.
TR::Node *sideEffectNode = node->getSecondChild();
cg->evaluate(sideEffectNode);
cg->decReferenceCount(sideEffectNode);
// Delegate the evaluation of the remaining children and the store operation to the storeEvaluator.
return TR::TreeEvaluator::floatingPointStoreEvaluator(node, cg);
}
TR::Register *
OMR::X86::TreeEvaluator::fwrtbariEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
// The wrtbar IL op represents a store with side effects.
// Currently we don't use the side effect node. So just evaluate it and decrement the reference count.
TR::Node *sideEffectNode = node->getThirdChild();
cg->evaluate(sideEffectNode);
cg->decReferenceCount(sideEffectNode);
// Delegate the evaluation of the remaining children and the store operation to the storeEvaluator.
return TR::TreeEvaluator::floatingPointStoreEvaluator(node, cg);
}
// cloadEvaluator handled by sloadEvaluator
// iiload handled by iloadEvaluator
// ilload handled by lloadEvaluator
// ialoadEvaluator handled by iloadEvaluator
// ibloadEvaluator handled by bloadEvaluator
// isloadEvaluator handled by sloadEvaluator
// icloadEvaluator handled by sloadEvaluator
// also used for iistore, astore and iastore
TR::Register *OMR::X86::TreeEvaluator::integerStoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *valueChild;
TR::Register *valueReg = NULL;
bool genLockedOpOutOfline = true;
TR::Compilation *comp = cg->comp();
bool usingCompressedPointers = false;
bool usingLowMemHeap = false;
node->getFirstChild()->oneParentSupportsLazyClobber(comp);
if (node->getOpCode().isIndirect())
{
valueChild = node->getSecondChild();
valueChild->oneParentSupportsLazyClobber(comp);
if (comp->useCompressedPointers() &&
(node->getSymbolReference()->getSymbol()->getDataType() == TR::Address))
{
// pattern match the sequence
// iistore f iistore f <- node
// aload O aload O
// value l2i
// lshr
// lsub <- translatedNode
// a2l
// value <- valueChild
// lconst HB
// iconst shftKonst
//
// -or- if the field is known to be null or usingLowMemHeap
// iistore f
// aload O
// l2i
// a2l
// value <- valueChild
//
TR::Node *translatedNode = valueChild;
bool isSequence = false;
if (translatedNode->getOpCodeValue() == TR::l2i)
{
translatedNode = translatedNode->getFirstChild();
isSequence = true;
}
if (translatedNode->getOpCode().isRightShift())
translatedNode = translatedNode->getFirstChild(); //optional
if (TR::Compiler->vm.heapBaseAddress() == 0 ||
valueChild->isNull())
usingLowMemHeap = true;
if (isSequence && (translatedNode->getOpCode().isSub() || usingLowMemHeap))
usingCompressedPointers = true;
if (usingCompressedPointers)
{
if (!usingLowMemHeap)
{
while ((valueChild->getNumChildren() > 0) &&
(valueChild->getOpCodeValue() != TR::a2l))
valueChild = valueChild->getFirstChild();
if (valueChild->getOpCodeValue() == TR::a2l)
valueChild = valueChild->getFirstChild();
// this is required so that different registers are
// allocated for the actual store and translated values
valueChild->incReferenceCount();
}
}
}
}
else
valueChild = node->getFirstChild();
int32_t size = node->getOpCode().getSize();
TR::MemoryReference *tempMR = NULL;
TR::Instruction *instr = NULL;
TR_X86OpCodes opCode;
TR::Node *originalValueChild = valueChild;
bool childIsConstant = false;
if (valueChild->getOpCode().isLoadConst() &&
valueChild->getRegister() == NULL &&
!usingCompressedPointers)
{
childIsConstant = true;
}
if (childIsConstant && (size <= 4 || IS_32BIT_SIGNED(valueChild->getLongInt())))
{
TR::LabelSymbol * dstStored = NULL;
TR::RegisterDependencyConditions *deps = NULL;
int32_t konst = valueChild->getInt();
// Note that we can use getInt() here for all sizes, since only the
// low order "size" bytes of the int will be used by the instruction,
// and longs only get here if the constant fits in 32 bits.
//
tempMR = generateX86MemoryReference(node, cg);
if (size == 1)
opCode = S1MemImm1;
else if (size == 2)
opCode = S2MemImm2;
else if (size == 4)
opCode = S4MemImm4;
else
opCode = S8MemImm4;
instr = generateMemImmInstruction(opCode, node, tempMR, konst, cg);
}
else
{
// See if this can be a direct memory update operation.
// If so, mark the value child so that when it is evaluated it can generate
// the direct memory update.
//
if (!usingCompressedPointers && cg->isMemoryUpdate(node))
{
if (valueChild->getFirstChild()->getReferenceCount() == 1)
{
// Memory update always a win if the result value is not needed again
//
valueChild->setDirectMemoryUpdate(true);
}
else
{
// Memory update is a win if there is register pressure or if we are
// optimizing for space
//
if (comp->getOption(TR_OptimizeForSpace))
valueChild->setDirectMemoryUpdate(true);
else
{
int32_t numRegs = cg->getLiveRegisters(TR_GPR)->getNumberOfLiveRegisters();
if (numRegs >= TR::RealRegister::LastAssignableGPR - 2) // -1 for VM thread reg, -1 fudge
valueChild->setDirectMemoryUpdate(true);
}
}
}
TR::Register *translatedReg = valueReg;
bool valueRegNeededInFuture = true;
// try to avoid unnecessary sign-extension
if (valueChild->getRegister() == 0 &&
valueChild->getReferenceCount() == 1 &&
(valueChild->getOpCodeValue() == TR::l2i ||
valueChild->getOpCodeValue() == TR::l2s ||
valueChild->getOpCodeValue() == TR::l2b))
{
valueChild = valueChild->getFirstChild();
if (cg->comp()->target().is64Bit())
translatedReg = cg->evaluate(valueChild);
else
translatedReg = cg->evaluate(valueChild)->getLowOrder();
}
else
{
translatedReg = cg->evaluate(valueChild);
}
if (usingCompressedPointers && !usingLowMemHeap)
{
// do the translation and handle stores of nulls
//
valueReg = cg->evaluate(node->getSecondChild());
// check for stored value being null
//
generateRegRegInstruction(TESTRegReg(), node, translatedReg, translatedReg, cg);
generateRegRegInstruction(CMOVERegReg(), node, valueReg, translatedReg, cg);
}
else
{
valueReg = translatedReg;
if (valueChild->getReferenceCount() == 0)
valueRegNeededInFuture = false;
}
// If the evaluation of the child resulted in a NULL register value, the
// store has already been done by the child
//
if (valueReg)
{
if (size == 1)
opCode = S1MemReg;
else if (size == 2)
opCode = S2MemReg;
else if (size == 4)
opCode = S4MemReg;
else
opCode = S8MemReg;
if (TR::Compiler->om.generateCompressedObjectHeaders() &&
(node->getSymbol()->isClassObject() ||
(node->getSymbolReference() == comp->getSymRefTab()->findVftSymbolRef())))
opCode = S4MemReg;
tempMR = generateX86MemoryReference(node, cg);
// in comp->useCompressedPointers we should write 4 bytes
// since the iastore has been changed to an iistore, size will be 4
//
instr = generateMemRegInstruction(opCode, node, tempMR, valueReg, cg);