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OMRTreeEvaluator.cpp
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OMRTreeEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <stdint.h>
#include <stdlib.h>
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LinkageConventionsEnum.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RecognizedMethods.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "codegen/X86Evaluator.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/IO.hpp"
#include "env/TRMemory.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/List.hpp"
#include "ras/Debug.hpp"
#include "runtime/Runtime.hpp"
#include "x/codegen/BinaryCommutativeAnalyser.hpp"
#include "x/codegen/CompareAnalyser.hpp"
#include "x/codegen/ConstantDataSnippet.hpp"
#include "x/codegen/FPTreeEvaluator.hpp"
#include "x/codegen/IntegerMultiplyDecomposer.hpp"
#include "x/codegen/SubtractAnalyser.hpp"
#include "x/codegen/X86Instruction.hpp"
#include "x/codegen/X86Ops.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "codegen/IA32LinkageUtils.hpp"
#include "codegen/IA32PrivateLinkage.hpp"
#endif
class TR_OpaqueMethodBlock;
///////////////////////
//
// Helper functions
//
TR::Register *OMR::X86::I386::TreeEvaluator::longArithmeticCompareRegisterWithImmediate(
TR::Node *node,
TR::Register *cmpRegister,
TR::Node *immedChild,
TR_X86OpCodes firstBranchOpCode,
TR_X86OpCodes secondBranchOpCode,
TR::CodeGenerator *cg)
{
int32_t lowValue = immedChild->getLongIntLow();
int32_t highValue = immedChild->getLongIntHigh();
TR::LabelSymbol *startLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *doneLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *highDoneLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
startLabel->setStartInternalControlFlow();
doneLabel->setEndInternalControlFlow();
TR::Register *targetRegister = cg->allocateRegister();
if (cg->enableRegisterInterferences())
cg->getLiveRegisters(TR_GPR)->setByteRegisterAssociation(targetRegister);
generateLabelInstruction(LABEL, node, startLabel, cg);
compareGPRegisterToImmediate(node, cmpRegister->getHighOrder(), highValue, cg);
generateRegInstruction(SETNE1Reg, node, targetRegister, cg);
generateLabelInstruction(JNE4, node, highDoneLabel, cg);
compareGPRegisterToImmediate(node, cmpRegister->getLowOrder(), lowValue, cg);
generateRegInstruction(SETNE1Reg, node, targetRegister, cg);
generateLabelInstruction(firstBranchOpCode, node, doneLabel, cg);
generateRegInstruction(NEG1Reg, node, targetRegister, cg);
generateLabelInstruction(JMP4, node, doneLabel, cg);
generateLabelInstruction(LABEL, node, highDoneLabel, cg);
generateLabelInstruction(secondBranchOpCode, node, doneLabel, cg);
generateRegInstruction(NEG1Reg, node, targetRegister, cg);
TR::RegisterDependencyConditions *deps = generateRegisterDependencyConditions((uint8_t)0, 3, cg);
deps->addPostCondition(cmpRegister->getLowOrder(), TR::RealRegister::NoReg, cg);
deps->addPostCondition(cmpRegister->getHighOrder(), TR::RealRegister::NoReg, cg);
deps->addPostCondition(targetRegister, TR::RealRegister::ByteReg, cg);
generateLabelInstruction(LABEL, node, doneLabel, deps, cg);
generateRegRegInstruction(MOVSXReg4Reg1, node, targetRegister, targetRegister, cg);
return targetRegister;
}
TR::Register *OMR::X86::I386::TreeEvaluator::compareLongAndSetOrderedBoolean(
TR::Node *node,
TR_X86OpCodes highSetOpCode,
TR_X86OpCodes lowSetOpCode,
TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR::Node *secondChild = node->getSecondChild();
TR::Register *targetRegister;
TR::Register * testRegister = secondChild->getRegister();
if (secondChild->getOpCodeValue() == TR::lconst &&
testRegister == NULL && performTransformation(comp, "O^O compareLongAndSetOrderedBoolean: checking that the second child node does not have an assigned register: %d\n", testRegister))
{
int32_t lowValue = secondChild->getLongIntLow();
int32_t highValue = secondChild->getLongIntHigh();
TR::Node *firstChild = node->getFirstChild();
TR::Register *cmpRegister = cg->evaluate(firstChild);
TR::LabelSymbol *startLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *doneLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
startLabel->setStartInternalControlFlow();
doneLabel->setEndInternalControlFlow();
generateLabelInstruction(LABEL, node, startLabel, cg);
compareGPRegisterToImmediate(node, cmpRegister->getHighOrder(), highValue, cg);
targetRegister = cg->allocateRegister();
if (cg->enableRegisterInterferences())
cg->getLiveRegisters(TR_GPR)->setByteRegisterAssociation(targetRegister);
generateRegInstruction(highSetOpCode, node, targetRegister, cg);
generateLabelInstruction(JNE4, node, doneLabel, cg);
compareGPRegisterToImmediate(node, cmpRegister->getLowOrder(), lowValue, cg);
generateRegInstruction(lowSetOpCode, node, targetRegister, cg);
TR::RegisterDependencyConditions *deps = generateRegisterDependencyConditions((uint8_t)0, 3, cg);
deps->addPostCondition(cmpRegister->getLowOrder(), TR::RealRegister::NoReg, cg);
deps->addPostCondition(cmpRegister->getHighOrder(), TR::RealRegister::NoReg, cg);
deps->addPostCondition(targetRegister, TR::RealRegister::NoReg, cg);
generateLabelInstruction(LABEL, node, doneLabel, deps, cg);
// Result of lcmpXX is an integer.
//
generateRegRegInstruction(MOVSXReg4Reg1, node, targetRegister, targetRegister, cg);
node->setRegister(targetRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
}
else
{
TR_X86CompareAnalyser temp(cg);
targetRegister = temp.longOrderedBooleanAnalyser(node,
highSetOpCode,
lowSetOpCode);
}
return targetRegister;
}
void OMR::X86::I386::TreeEvaluator::compareLongsForOrder(
TR::Node *node,
TR_X86OpCodes highOrderBranchOp,
TR_X86OpCodes highOrderReversedBranchOp,
TR_X86OpCodes lowOrderBranchOp,
TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR::Node *secondChild = node->getSecondChild();
TR::Register * testRegister = secondChild->getRegister();
if (secondChild->getOpCodeValue() == TR::lconst &&
testRegister == NULL && performTransformation(comp, "O^O compareLongsForOrder: checking that the second child node does not have an assigned register: %d\n", testRegister))
{
int32_t lowValue = secondChild->getLongIntLow();
int32_t highValue = secondChild->getLongIntHigh();
TR::Node *firstChild = node->getFirstChild();
// KAS:: need delayed evaluation here and use of memimm instructions to reduce
// register pressure
TR::Register *cmpRegister = cg->evaluate(firstChild);
TR::LabelSymbol *startLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *doneLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *destinationLabel = node->getBranchDestination()->getNode()->getLabel();
List<TR::Register> popRegisters(cg->trMemory());
startLabel->setStartInternalControlFlow();
doneLabel->setEndInternalControlFlow();
generateLabelInstruction(LABEL, node, startLabel, cg);
compareGPRegisterToImmediate(node, cmpRegister->getHighOrder(), highValue, cg);
TR::RegisterDependencyConditions *deps = NULL;
if (node->getNumChildren() == 3)
{
TR::Node *third = node->getChild(2);
cg->evaluate(third);
deps = generateRegisterDependencyConditions(third, cg, 2, &popRegisters);
deps->addPostCondition(cmpRegister->getHighOrder(), TR::RealRegister::NoReg, cg);
deps->addPostCondition(cmpRegister->getLowOrder(), TR::RealRegister::NoReg, cg);
deps->stopAddingConditions();
generateLabelInstruction(highOrderBranchOp, node, destinationLabel, deps, cg);
generateLabelInstruction(JNE4, node, doneLabel, deps, cg);
compareGPRegisterToImmediate(node, cmpRegister->getLowOrder(), lowValue, cg);
generateLabelInstruction(lowOrderBranchOp, node, destinationLabel, deps, cg);
}
else
{
generateLabelInstruction(highOrderBranchOp, node, destinationLabel, cg);
generateLabelInstruction(JNE4, node, doneLabel, cg);
compareGPRegisterToImmediate(node, cmpRegister->getLowOrder(), lowValue, cg);
generateLabelInstruction(lowOrderBranchOp, node, destinationLabel, cg);
deps = generateRegisterDependencyConditions((uint8_t)0, 2, cg);
deps->addPostCondition(cmpRegister->getHighOrder(), TR::RealRegister::NoReg, cg);
deps->addPostCondition(cmpRegister->getLowOrder(), TR::RealRegister::NoReg, cg);
deps->stopAddingConditions();
}
generateLabelInstruction(LABEL, node, doneLabel, deps, cg);
if (deps)
deps->setMayNeedToPopFPRegisters(true);
if (!popRegisters.isEmpty())
{
ListIterator<TR::Register> popRegsIt(&popRegisters);
for (TR::Register *popRegister = popRegsIt.getFirst(); popRegister != NULL; popRegister = popRegsIt.getNext())
{
generateFPSTiST0RegRegInstruction(FSTRegReg, node, popRegister, popRegister, cg);
cg->stopUsingRegister(popRegister);
}
}
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
}
else
{
TR_X86CompareAnalyser temp(cg);
temp.longOrderedCompareAndBranchAnalyser(node,
lowOrderBranchOp,
highOrderBranchOp,
highOrderReversedBranchOp);
}
}
///////////////////////
//
// Member functions
//
// TODO:AMD64: Reorder these to match their declaration in TreeEvaluator.hpp
//
TR::Register *OMR::X86::I386::TreeEvaluator::aconstEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *reg = loadConstant(node, node->getInt(), TR_RematerializableAddress, cg);
node->setRegister(reg);
return reg;
}
TR::Register *OMR::X86::I386::TreeEvaluator::lconstEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *lowRegister,
*highRegister;
int32_t lowValue = node->getLongIntLow();
int32_t highValue = node->getLongIntHigh();
if (abs(lowValue - highValue) <= 128)
{
if (lowValue <= highValue)
{
lowRegister = cg->allocateRegister();
highRegister = loadConstant(node, highValue, TR_RematerializableInt, cg);
if (lowValue == highValue)
{
generateRegRegInstruction(MOV4RegReg, node, lowRegister, highRegister, cg);
}
else
{
generateRegMemInstruction(LEA4RegMem, node, lowRegister,
generateX86MemoryReference(highRegister, lowValue - highValue, cg), cg);
}
}
else
{
lowRegister = loadConstant(node, lowValue, TR_RematerializableInt, cg);
highRegister = cg->allocateRegister();
generateRegMemInstruction(LEA4RegMem, node, highRegister,
generateX86MemoryReference(lowRegister, highValue - lowValue, cg), cg);
}
}
else
{
lowRegister = loadConstant(node, lowValue, TR_RematerializableInt, cg);
highRegister = loadConstant(node, highValue, TR_RematerializableInt, cg);
}
TR::RegisterPair *longRegister = cg->allocateRegisterPair(lowRegister, highRegister);
node->setRegister(longRegister);
return longRegister;
}
// also handles ilstore
TR::Register *OMR::X86::I386::TreeEvaluator::lstoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR::Node *valueChild;
TR::SymbolReference *symRef = node->getSymbolReference();
bool isVolatile = false;
if (symRef && !symRef->isUnresolved())
{
TR::Symbol *symbol = symRef->getSymbol();
isVolatile = symbol->isVolatile();
#ifdef J9_PROJECT_SPECIFIC
TR_OpaqueMethodBlock *caller = node->getOwningMethod();
if (isVolatile && caller)
{
TR_ResolvedMethod *m = comp->fe()->createResolvedMethod(cg->trMemory(), caller, node->getSymbolReference()->getOwningMethod(comp));
if (m->getRecognizedMethod() == TR::java_util_concurrent_atomic_AtomicLong_lazySet)
{
isVolatile = false;
}
}
#endif
}
if (node->getOpCode().isIndirect())
{
valueChild = node->getSecondChild();
}
else
{
valueChild = node->getFirstChild();
}
// Handle special cases
//
if (!isVolatile &&
valueChild->getRegister() == NULL &&
valueChild->getReferenceCount() == 1)
{
// Special case storing a double value into a long variable
//
if (valueChild->getOpCodeValue() == TR::dbits2l &&
!valueChild->normalizeNanValues())
{
if (node->getOpCode().isIndirect())
{
node->setChild(1, valueChild->getFirstChild());
TR::Node::recreate(node, TR::dstorei);
dstoreEvaluator(node, cg);
node->setChild(1, valueChild);
TR::Node::recreate(node, TR::lstorei);
}
else
{
node->setChild(0, valueChild->getFirstChild());
TR::Node::recreate(node, TR::dstore);
dstoreEvaluator(node, cg);
node->setChild(0, valueChild);
TR::Node::recreate(node, TR::lstore);
}
cg->decReferenceCount(valueChild);
return NULL;
}
}
TR::MemoryReference *lowMR = NULL;
TR::MemoryReference *highMR;
TR::Instruction *instr = NULL;
if (!isVolatile &&
valueChild->getOpCodeValue() == TR::lconst &&
valueChild->getRegister() == NULL)
{
lowMR = generateX86MemoryReference(node, cg);
highMR = generateX86MemoryReference(*lowMR, 4, cg);
int32_t lowValue = valueChild->getLongIntLow();
int32_t highValue = valueChild->getLongIntHigh();
if (lowValue == highValue)
{
TR::Register *valueReg = loadConstant(node, lowValue, TR_RematerializableInt, cg);
instr = generateMemRegInstruction(S4MemReg, node, lowMR, valueReg, cg);
generateMemRegInstruction(S4MemReg, node, highMR, valueReg, cg);
cg->stopUsingRegister(valueReg);
}
else
{
instr = generateMemImmInstruction(S4MemImm4, node, lowMR, lowValue, cg);
generateMemImmInstruction(S4MemImm4, node, highMR, highValue, cg);
}
}
else
{
TR::Machine *machine = cg->machine();
TR::Register *eaxReg=NULL, *edxReg=NULL, *ecxReg=NULL, *ebxReg=NULL;
TR::RegisterDependencyConditions *deps = NULL;
TR::Register *valueReg = cg->evaluate(valueChild);
if (valueReg)
{
lowMR = generateX86MemoryReference(node, cg);
highMR = generateX86MemoryReference(*lowMR, 4, cg);
if (isVolatile)
{
if (cg->useSSEForDoublePrecision() && performTransformation(comp, "O^O Using SSE for volatile store %s\n", cg->getDebug()->getName(node)))
{
//Get stack piece
TR::MemoryReference *stackLow = cg->machine()->getDummyLocalMR(TR::Int64);
TR::MemoryReference *stackHigh = generateX86MemoryReference(*stackLow, 4, cg);
//generate: stack1 <- (valueReg->getloworder()) [S4MemReg]
instr = generateMemRegInstruction(S4MemReg, node, stackLow, valueReg->getLowOrder(), cg);
//generate: stack1_plus4 <- (valueReg->gethighorder())
generateMemRegInstruction(S4MemReg, node, stackHigh, valueReg->getHighOrder(), cg);
//generate: xmm <- stack1
TR::MemoryReference *stack = generateX86MemoryReference(*stackLow, 0, cg);
//Allocate XMM Reg
TR::Register *reg = cg->allocateRegister(TR_FPR);
generateRegMemInstruction(cg->getXMMDoubleLoadOpCode(), node, reg, stack, cg);
//generate: lowMR <- xmm
generateMemRegInstruction(MOVSDMemReg, node, lowMR, reg, cg);
//Stop using xmm
cg->stopUsingRegister(reg);
}
else
{
TR_ASSERT_FATAL(cg->comp()->compileRelocatableCode() || cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_CX8), "Assumption of support of the CMPXCHG8B instruction failed in lstoreEvaluator()" );
eaxReg = cg->allocateRegister();
edxReg = cg->allocateRegister();
ecxReg = cg->allocateRegister();
ebxReg = cg->allocateRegister();
deps = generateRegisterDependencyConditions((uint8_t)4, (uint8_t)4, cg);
deps->addPostCondition(eaxReg, TR::RealRegister::eax, cg);
deps->addPostCondition(edxReg, TR::RealRegister::edx, cg);
deps->addPostCondition(ecxReg, TR::RealRegister::ecx, cg);
deps->addPostCondition(ebxReg, TR::RealRegister::ebx, cg);
deps->addPreCondition(eaxReg, TR::RealRegister::eax, cg);
deps->addPreCondition(edxReg, TR::RealRegister::edx, cg);
deps->addPreCondition(ecxReg, TR::RealRegister::ecx, cg);
deps->addPreCondition(ebxReg, TR::RealRegister::ebx, cg);
instr = generateRegMemInstruction(L4RegMem, node, eaxReg, lowMR, cg); // forming the EDX:EAX pair
generateRegMemInstruction(L4RegMem, node, edxReg, highMR, cg);
lowMR->setIgnoreVolatile();
highMR->setIgnoreVolatile();
generateRegRegInstruction(MOV4RegReg, node, ebxReg, valueReg->getLowOrder(), cg); // forming the ECX:EBX pair
generateRegRegInstruction(MOV4RegReg, node, ecxReg, valueReg->getHighOrder(), cg);
TR::MemoryReference *cmpxchgMR = generateX86MemoryReference(node, cg);
generateMemInstruction (cg->comp()->target().isSMP() ? LCMPXCHG8BMem : CMPXCHG8BMem, node, cmpxchgMR, deps, cg);
cg->stopUsingRegister(eaxReg);
cg->stopUsingRegister(edxReg);
cg->stopUsingRegister(ecxReg);
cg->stopUsingRegister(ebxReg);
}
}
else if(symRef && symRef->isUnresolved() && symRef->getSymbol()->isVolatile() && (!comp->getOption(TR_DisableNewX86VolatileSupport) && cg->comp()->target().is32Bit()) )
{
TR_ASSERT_FATAL(cg->comp()->compileRelocatableCode() || cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_CX8), "Assumption of support of the CMPXCHG8B instruction failed in lstoreEvaluator()" );
eaxReg = cg->allocateRegister();
edxReg = cg->allocateRegister();
ecxReg = cg->allocateRegister();
ebxReg = cg->allocateRegister();
deps = generateRegisterDependencyConditions((uint8_t)4, (uint8_t)4, cg);
deps->addPostCondition(eaxReg, TR::RealRegister::eax, cg);
deps->addPostCondition(edxReg, TR::RealRegister::edx, cg);
deps->addPostCondition(ecxReg, TR::RealRegister::ecx, cg);
deps->addPostCondition(ebxReg, TR::RealRegister::ebx, cg);
deps->addPreCondition(eaxReg, TR::RealRegister::eax, cg);
deps->addPreCondition(edxReg, TR::RealRegister::edx, cg);
deps->addPreCondition(ecxReg, TR::RealRegister::ecx, cg);
deps->addPreCondition(ebxReg, TR::RealRegister::ebx, cg);
generateRegRegInstruction(MOV4RegReg, node, ebxReg, valueReg->getLowOrder(), cg); // forming the ECX:EBX pair
generateRegRegInstruction(MOV4RegReg, node, ecxReg, valueReg->getHighOrder(), cg);
instr = generateRegMemInstruction(L4RegMem, node, eaxReg, lowMR, cg); // forming the EDX:EAX pair
generateRegMemInstruction(L4RegMem, node, edxReg, highMR, cg);
lowMR->setIgnoreVolatile();
highMR->setIgnoreVolatile();
lowMR->setProcessAsLongVolatileLow();
highMR->setProcessAsLongVolatileHigh();
TR::MemoryReference *cmpxchgMR = generateX86MemoryReference(node, cg);
generateMemInstruction (cg->comp()->target().isSMP() ? LCMPXCHG8BMem : CMPXCHG8BMem, node, cmpxchgMR, deps, cg);
cg->stopUsingRegister(eaxReg);
cg->stopUsingRegister(edxReg);
cg->stopUsingRegister(ecxReg);
cg->stopUsingRegister(ebxReg);
}
else
{
instr = generateMemRegInstruction(S4MemReg, node, lowMR, valueReg->getLowOrder(), cg);
generateMemRegInstruction(S4MemReg, node, highMR, valueReg->getHighOrder(), cg);
TR::SymbolReference& mrSymRef = lowMR->getSymbolReference();
if (mrSymRef.isUnresolved())
{
padUnresolvedDataReferences(node, mrSymRef, cg);
}
}
}
}
cg->decReferenceCount(valueChild);
if (lowMR && !(valueChild->isDirectMemoryUpdate() && node->getOpCode().isIndirect()))
lowMR->decNodeReferenceCounts(cg);
if (node->getSymbolReference()->getSymbol()->isVolatile())
{
TR_OpaqueMethodBlock *caller = node->getOwningMethod();
if ((lowMR || highMR) && caller)
{
#ifdef J9_PROJECT_SPECIFIC
TR_ResolvedMethod *m = comp->fe()->createResolvedMethod(cg->trMemory(), caller, node->getSymbolReference()->getOwningMethod(comp));
if (m->getRecognizedMethod() == TR::java_util_concurrent_atomic_AtomicLong_lazySet)
{
if (lowMR)
lowMR->setIgnoreVolatile();
if (highMR)
highMR->setIgnoreVolatile();
}
#endif
}
}
if (instr && node->getOpCode().isIndirect())
cg->setImplicitExceptionPoint(instr);
return NULL;
}
TR::Register *OMR::X86::I386::TreeEvaluator::integerPairReturnEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
// Restore the default FPCW if it has been forced to single precision mode.
//
TR::Compilation *comp = cg->comp();
if (cg->enableSinglePrecisionMethods() &&
comp->getJittedMethodSymbol()->usesSinglePrecisionMode())
{
generateMemInstruction(LDCWMem, node, generateX86MemoryReference(cg->findOrCreate2ByteConstant(node, DOUBLE_PRECISION_ROUND_TO_NEAREST), cg), cg);
}
TR::Node *firstChild = node->getFirstChild();
TR::Register *returnRegister = cg->evaluate(firstChild);
TR::Register *lowRegister = returnRegister->getLowOrder();
TR::Register *highRegister = returnRegister->getHighOrder();
const TR::X86LinkageProperties &linkageProperties = cg->getProperties();
TR::RealRegister::RegNum machineLowReturnRegister =
linkageProperties.getLongLowReturnRegister();
TR::RealRegister::RegNum machineHighReturnRegister =
linkageProperties.getLongHighReturnRegister();
TR::RegisterDependencyConditions *dependencies = NULL;
if (machineLowReturnRegister != TR::RealRegister::NoReg)
{
dependencies = generateRegisterDependencyConditions((uint8_t)3, 0, cg);
dependencies->addPreCondition(lowRegister, machineLowReturnRegister, cg);
dependencies->addPreCondition(highRegister, machineHighReturnRegister, cg);
dependencies->stopAddingConditions();
}
if (linkageProperties.getCallerCleanup())
{
generateInstruction(RET, node, dependencies, cg);
}
else
{
generateImmInstruction(RETImm2, node, 0, dependencies, cg);
}
if (comp->getJittedMethodSymbol()->getLinkageConvention() == TR_Private)
{
comp->setReturnInfo(TR_LongReturn);
}
cg->decReferenceCount(firstChild);
return NULL;
}
TR::Register *OMR::X86::I386::TreeEvaluator::integerPairAddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *targetRegister = NULL;
TR::Node *secondChild = node->getSecondChild();
TR::Node *firstChild = node->getFirstChild();
TR::Instruction *instr;
TR::MemoryReference *lowMR,
*highMR;
// See if we can generate a direct memory operation. In this case, no
// target register is generated, and we return NULL to the caller (which
// should be a store) to indicate that the store has already been done.
//
bool isMemOp = node->isDirectMemoryUpdate();
bool firstChildAlreadyEvaluated = false;
bool needsEflags = NEED_CC(node) || (node->getOpCodeValue() == TR::luaddc);
if (isMemOp)
{
// Make sure the original value is evaluated before the update if it
// is going to be used again.
//
if (firstChild->getReferenceCount() > 1)
{
TR::Register *reg = cg->evaluate(firstChild);
lowMR = generateX86MemoryReference(*reg->getMemRef(), 4, cg);
firstChildAlreadyEvaluated = true;
}
else
{
lowMR = generateX86MemoryReference(firstChild, cg, false);
}
highMR = generateX86MemoryReference(*lowMR, 4, cg);
}
if (!needsEflags &&
secondChild->getOpCodeValue() == TR::lconst &&
secondChild->getRegister() == NULL &&
(isMemOp || firstChild->getReferenceCount() == 1))
{
if (!isMemOp)
targetRegister = cg->evaluate(firstChild);
int32_t lowValue = secondChild->getLongIntLow();
int32_t highValue = secondChild->getLongIntHigh();
if (lowValue >= -128 && lowValue <= 127)
{
if (isMemOp)
instr = generateMemImmInstruction(ADD4MemImms, node, lowMR, lowValue, cg);
else
instr = generateRegImmInstruction(ADD4RegImms, node, targetRegister->getLowOrder(), lowValue, cg);
}
else if (lowValue == 128)
{
if (isMemOp)
instr = generateMemImmInstruction(SUB4MemImms, node, lowMR, -128, cg);
else
instr = generateRegImmInstruction(SUB4RegImms, node, targetRegister->getLowOrder(), -128, cg);
// Use SBB of the negation of (highValue + 1) for the high order,
// since we are getting the carry bit in the wrong sense from the SUB.
highValue = -(highValue + 1);
}
else
{
if (isMemOp)
instr = generateMemImmInstruction(ADD4MemImm4, node, lowMR, lowValue, cg);
else
instr = generateRegImmInstruction(ADD4RegImm4, node, targetRegister->getLowOrder(), lowValue, cg);
}
TR_X86OpCodes opCode;
if (highValue >= -128 && highValue <= 127)
{
if (lowValue == 128)
if (isMemOp)
opCode = SBB4MemImms;
else
opCode = SBB4RegImms;
else
if (isMemOp)
opCode = ADC4MemImms;
else
opCode = ADC4RegImms;
}
else
{
if (lowValue == 128)
if (isMemOp)
opCode = SBB4MemImm4;
else
opCode = SBB4RegImm4;
else
if (isMemOp)
opCode = ADC4MemImm4;
else
opCode = ADC4RegImm4;
}
if (isMemOp)
{
generateMemImmInstruction(opCode, node, highMR, highValue, cg);
if (debug("traceMemOp"))
diagnostic("\n*** Node [" POINTER_PRINTF_FORMAT "] inc by const", node);
}
else
{
generateRegImmInstruction(opCode, node, targetRegister->getHighOrder(), highValue, cg);
}
}
else if (isMemOp && !needsEflags)
{
TR::Register *tempReg = cg->evaluate(secondChild);
instr = generateMemRegInstruction(ADD4MemReg, node, lowMR, tempReg->getLowOrder(), cg);
generateMemRegInstruction(ADC4MemReg, node, highMR, tempReg->getHighOrder(), cg);
if (debug("traceMemOp"))
diagnostic("\n*** Node [" POINTER_PRINTF_FORMAT "] inc by var", node);
}
else
{
TR_X86BinaryCommutativeAnalyser temp(cg);
temp.longAddAnalyser(node);
return node->getRegister();
}
if (isMemOp)
{
if (!firstChildAlreadyEvaluated)
lowMR->decNodeReferenceCounts(cg);
else
lowMR->stopUsingRegisters(cg);
cg->setImplicitExceptionPoint(instr);
}
node->setRegister(targetRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return targetRegister;
}
TR::Register *OMR::X86::I386::TreeEvaluator::integerPairSubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *targetRegister = NULL;
TR::Instruction *instr;
TR::MemoryReference *lowMR,
*highMR;
// See if we can generate a direct memory operation. In this case, no
// target register is generated, and we return NULL to the caller (which
// should be a store) to indicate that the store has already been done.
//
bool isMemOp = node->isDirectMemoryUpdate();
bool firstChildAlreadyEvaluated = false;
bool needsEflags = NEED_CC(node) || (node->getOpCodeValue() == TR::lusubb);
if (isMemOp)
{
// Make sure the original value is evaluated before the update if it
// is going to be used again.
//
if (firstChild->getReferenceCount() > 1)
{
TR::Register *reg = cg->evaluate(firstChild);
lowMR = generateX86MemoryReference(*reg->getMemRef(), 4, cg);
firstChildAlreadyEvaluated = true;
}
else
{
lowMR = generateX86MemoryReference(firstChild, cg, false);
}
highMR = generateX86MemoryReference(*lowMR, 4, cg);
}
if (!needsEflags &&
secondChild->getOpCodeValue() == TR::lconst &&
secondChild->getRegister() == NULL &&
(isMemOp || firstChild->getReferenceCount() == 1))
{
if (!isMemOp)
targetRegister = cg->evaluate(firstChild);
int32_t lowValue = secondChild->getLongIntLow();
int32_t highValue = secondChild->getLongIntHigh();
if (lowValue >= -128 && lowValue <= 127)
{
if (isMemOp)
instr = generateMemImmInstruction(SUB4MemImms, node, lowMR, lowValue, cg);
else
instr = generateRegImmInstruction(SUB4RegImms, node, targetRegister->getLowOrder(), lowValue, cg);
}
else if (lowValue == 128)
{
if (isMemOp)
instr = generateMemImmInstruction(ADD4MemImms, node, lowMR, lowValue, cg);
else
instr = generateRegImmInstruction(ADD4RegImms, node, targetRegister->getLowOrder(), -128, cg);
// Use ADC of the negation of (highValue + 1) for the high order,
// since we are getting the carry bit in the wrong sense from the ADD.
highValue = -(highValue + 1);
}
else
{
if (isMemOp)
instr = generateMemImmInstruction(SUB4MemImm4, node, lowMR, lowValue, cg);
else
instr = generateRegImmInstruction(SUB4RegImm4, node, targetRegister->getLowOrder(), lowValue, cg);
}
TR_X86OpCodes opCode;
if (highValue >= -128 && highValue <= 127)
{
if (lowValue == 128)
if (isMemOp)
opCode = ADC4MemImms;
else
opCode = ADC4RegImms;
else
if (isMemOp)
opCode = SBB4MemImms;
else
opCode = SBB4RegImms;
}
else
{
if (lowValue == 128)
if (isMemOp)
opCode = ADC4MemImm4;
else
opCode = ADC4RegImm4;
else
if (isMemOp)
opCode = SBB4MemImm4;
else
opCode = SBB4RegImm4;
}
if (isMemOp)
{
generateMemImmInstruction(opCode, node, highMR, highValue, cg);
if (debug("traceMemOp"))
diagnostic("\n*** Node [" POINTER_PRINTF_FORMAT "] dec by const", node);
}
else
{
generateRegImmInstruction(opCode, node, targetRegister->getHighOrder(), highValue, cg);
}
}
else if (isMemOp && !needsEflags)
{
TR::Register *tempReg = cg->evaluate(secondChild);
instr = generateMemRegInstruction(SUB4MemReg, node, lowMR, tempReg->getLowOrder(), cg);
generateMemRegInstruction(SBB4MemReg, node, highMR, tempReg->getHighOrder(), cg);
if (debug("traceMemOp"))
diagnostic("\n*** Node [" POINTER_PRINTF_FORMAT "] dec by var", node);
}
else
{
TR_X86SubtractAnalyser temp(cg);
temp.longSubtractAnalyser(node);
return node->getRegister();
}
if (isMemOp)
{
if (!firstChildAlreadyEvaluated)
lowMR->decNodeReferenceCounts(cg);
else
lowMR->stopUsingRegisters(cg);
cg->setImplicitExceptionPoint(instr);
}
node->setRegister(targetRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return targetRegister;
}
TR::Register *OMR::X86::I386::TreeEvaluator::integerPairDualMulEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR_ASSERT((node->getOpCodeValue() == TR::lumulh) || (node->getOpCodeValue() == TR::lmul), "Unexpected operator. Expected lumulh or lmul.");
if (node->isDualCyclic() && (node->getChild(2)->getReferenceCount() == 1))
{
// other part of this dual is not used, and is dead
TR::Node *pair = node->getChild(2);
// break dual into parts before evaluation
// pair has only one reference, so need to avoid recursiveness removal of its subtree
pair->incReferenceCount();
node->removeChild(2);
pair->removeChild(2);
cg->decReferenceCount(pair->getFirstChild());
cg->decReferenceCount(pair->getSecondChild());
cg->decReferenceCount(pair);
// evaluate this part again
return cg->evaluate(node);
}
else
{
// use long dual analyser
TR_X86BinaryCommutativeAnalyser temp(cg);
temp.longDualMultiplyAnalyser(node);
}
return node->getRegister();
}
TR::Register *OMR::X86::I386::TreeEvaluator::integerPairMulEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *lowRegister = NULL;
TR::Register *highRegister;
TR::Register *targetRegister;
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::X86ImmSymInstruction *instr;
TR::MemoryReference *nodeMR = NULL;
TR::Compilation *comp = cg->comp();
bool needsUnsignedHighMulOnly = (node->getOpCodeValue() == TR::lumulh) && !node->isDualCyclic();
if (node->isDualCyclic() || needsUnsignedHighMulOnly)
{
return integerPairDualMulEvaluator(node, cg);
}
if (secondChild->getOpCodeValue() == TR::lconst)
{
TR_X86OpCodes opCode;
int32_t lowValue = secondChild->getLongIntLow();
int32_t highValue = secondChild->getLongIntHigh();
int64_t value = secondChild->getLongInt();
int32_t absValue = (highValue < 0) ? -highValue : highValue;
bool firstIU2L = false;
bool intMul = false;
TR::ILOpCodes firstOp = firstChild->getOpCodeValue();
if (firstOp == TR::iu2l)
{
firstIU2L = true;
}
if (firstOp == TR::i2l && value >= TR::getMinSigned<TR::Int32>() && value <= TR::getMaxSigned<TR::Int32>())
{
}
if (lowValue == 0 && highValue == 0)
{
lowRegister = cg->allocateRegister();
generateRegRegInstruction(XOR4RegReg, node, lowRegister, lowRegister, cg);
highRegister = cg->allocateRegister();
generateRegRegInstruction(XOR4RegReg, node, highRegister, highRegister, cg);
}
else if (cg->convertMultiplyToShift(node))
{
// Don't do a direct memory operation if we have to negate the result
//
if (absValue != highValue)
node->setDirectMemoryUpdate(false);
targetRegister = cg->evaluate(node);
if (absValue != highValue)
{
generateRegInstruction(NEG4Reg, node, targetRegister->getLowOrder(), cg);
generateRegImmInstruction(ADC4RegImms, node, targetRegister->getHighOrder(), 0, cg);
generateRegInstruction(NEG4Reg, node, targetRegister->getHighOrder(), cg);