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BinaryEvaluator.cpp
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BinaryEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <stddef.h>
#include <stdint.h>
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "codegen/X86Evaluator.hpp"
#include "compile/Compilation.hpp"
#include "env/IO.hpp"
#include "env/ObjectModel.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/AutomaticSymbol.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "x/codegen/BinaryCommutativeAnalyser.hpp"
#include "x/codegen/DivideCheckSnippet.hpp"
#include "x/codegen/IntegerMultiplyDecomposer.hpp"
#include "x/codegen/SubtractAnalyser.hpp"
#include "x/codegen/X86Instruction.hpp"
#include "codegen/InstOpCode.hpp"
#include "env/CompilerEnv.hpp"
extern TR::Register *intOrLongClobberEvaluate(TR::Node *node, bool nodeIs64Bit, TR::CodeGenerator *cg);
///////////////////
//
// Hack markers
//
// Escape analysis can produce a tree that is not type correct; in particular a
// left-shift with an address first child (TR::loadaddr of local object used for
// initialization of the flags field of the local object). In this case if the
// register is to be clobbered and if the child is evaluated in collected
// reference register, a copy is inserted so that the register used to evaluate
// the shl is not marked as collected. The ideal tr.dev fix should be the
// introduction of a TR::a2i / TR::a2l opcode in the IL. Causes Jgrinder test
// case GC failure.
//
#define SHIFT_MAY_HAVE_ADDRESS_CHILD (1)
// forceSize is a separate function from evaluateAndForceSize so the C++
// compiler can decide whether or not to inline it. In contrast, we really
// want evaluateAndForceSize to be inlined because it can turn into evaluate()
// on IA32, and it has a lot of call sites.
//
static void forceSize(TR::Node *node, TR::Register *reg, bool is64Bit, TR::CodeGenerator *cg)
{
if (is64Bit && node->getSize() <= 4 && !node->isNonNegative())
{
// TODO:AMD64: Don't sign-extend the same register twice. Perhaps use
// the FP precision adjustment flag to indicate when a sign-extension has
// already been done.
generateRegRegInstruction(MOVSXReg8Reg4, node, reg, reg, cg);
}
}
// Used for aiadd, to sign-extend the second child on AMD64 from 4 to 8 bytes.
// Note that there is never a need to sign-extend the first child of any add.
inline TR::Register *evaluateAndForceSize(TR::Node *node, bool is64Bit, TR::CodeGenerator *cg)
{
TR::Register *reg = cg->evaluate(node);
if (cg->comp()->target().is64Bit())
{
forceSize(node, reg, is64Bit, cg);
}
else
{
TR_ASSERT(!is64Bit, "64-bit expressions should be using register pairs on IA32");
}
return reg;
}
bool OMR::X86::TreeEvaluator::analyseSubForLEA(TR::Node *node, TR::CodeGenerator *cg)
{
bool nodeIs64Bit = TR::TreeEvaluator::getNodeIs64Bit(node, cg);
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::ILOpCode &firstOp = firstChild->getOpCode();
TR::MemoryReference *leaMR = NULL;
int32_t stride = 0;
TR::Register *targetRegister;
TR::Register *indexRegister;
// sub
// ? (firstChild)
// const (secondChild)
//
TR_ASSERT(secondChild->getOpCode().isLoadConst(), "assertion failure");
intptr_t displacement = -TR::TreeEvaluator::integerConstNodeValue(secondChild, cg);
intptr_t dummyConstValue = 0;
if (firstChild->getRegister() == NULL && firstChild->getReferenceCount() == 1)
{
stride = TR::MemoryReference::getStrideForNode(firstChild, cg);
if (stride)
{
// sub
// mul/shl (firstChild)
// ?
// stride
// const (secondChild)
//
indexRegister = cg->evaluate(firstChild->getFirstChild());
leaMR = generateX86MemoryReference(NULL,
indexRegister,
stride,
displacement, cg);
targetRegister = cg->allocateRegister();
generateRegMemInstruction(LEARegMem(nodeIs64Bit), node, targetRegister, leaMR, cg);
cg->decReferenceCount(firstChild->getFirstChild());
cg->decReferenceCount(firstChild->getSecondChild());
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
node->setRegister(targetRegister);
return true;
}
if (firstOp.isAdd() &&
TR::TreeEvaluator::constNodeValueIs32BitSigned(secondChild, &dummyConstValue, cg))
{
// sub
// add (firstChild)
// ? (llChild)
// ? (lrchild)
// const (secondChild)
//
TR::Node *llChild = firstChild->getFirstChild();
TR::Node *lrChild = firstChild->getSecondChild();
if (llChild->getRegister() == NULL &&
llChild->getReferenceCount() == 1 &&
(stride = TR::MemoryReference::getStrideForNode(llChild, cg)))
{
// sub
// add (firstChild)
// mul/shl (llChild)
// ?
// stride
// ? (lrchild)
// const (secondChild)
//
leaMR = generateX86MemoryReference(cg->evaluate(lrChild),
cg->evaluate(llChild->getFirstChild()),
stride,
displacement, cg);
cg->decReferenceCount(llChild->getFirstChild());
cg->decReferenceCount(llChild->getSecondChild());
}
else if (lrChild->getRegister() == NULL &&
lrChild->getReferenceCount() == 1 &&
(stride = TR::MemoryReference::getStrideForNode(lrChild, cg)))
{
// sub
// add (firstChild)
// ? (llchild)
// mul/shl (lrChild)
// ?
// stride
// const (secondChild)
//
leaMR = generateX86MemoryReference(cg->evaluate(llChild),
cg->evaluate(lrChild->getFirstChild()),
stride,
displacement, cg);
cg->decReferenceCount(lrChild->getFirstChild());
cg->decReferenceCount(lrChild->getSecondChild());
}
else
{
leaMR = generateX86MemoryReference(cg->evaluate(llChild),
cg->evaluate(lrChild),
0,
displacement, cg);
}
targetRegister = cg->allocateRegister();
generateRegMemInstruction(LEARegMem(nodeIs64Bit), node, targetRegister, leaMR, cg);
cg->decReferenceCount(llChild);
cg->decReferenceCount(lrChild);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
node->setRegister(targetRegister);
return true;
}
}
return false;
}
bool OMR::X86::TreeEvaluator::analyseAddForLEA(TR::Node *node, TR::CodeGenerator *cg)
{
if (!performTransformation(cg->comp(), "O^O analyseAddForLEA\n"))
return false;
bool nodeIs64Bit = TR::TreeEvaluator::getNodeIs64Bit(node, cg);
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::ILOpCode &firstOp = firstChild->getOpCode();
TR::ILOpCode &secondOp = secondChild->getOpCode();
TR::MemoryReference *leaMR = NULL;
int32_t stride = 0;
int32_t stride1 = 0;
int32_t stride2 = 0;
TR::Node *indexNode = NULL;
TR::Node *baseNode = NULL;
TR::Node *constNode = NULL;
TR::Register *targetRegister = NULL;
TR::Register *indexRegister = NULL;
//TR_ASSERT(node->getSize() == firstChild->getSize(), "evaluateAndForceSize never needed for firstChild");
if ((secondOp.isAdd() || secondOp.isSub()) &&
secondChild->getReferenceCount() == 1 && secondChild->getRegister() == NULL)
{
TR::Node *addFirstChild = secondChild->getFirstChild();
TR::Node *addSecondChild = secondChild->getSecondChild();
TR::ILOpCode &addFirstOp = addFirstChild->getOpCode();
TR::ILOpCode &addSecondOp = addSecondChild->getOpCode();
int32_t stride = TR::MemoryReference::getStrideForNode(addFirstChild, cg);
if (stride &&
addFirstChild->getReferenceCount() == 1 && addFirstChild->getRegister() == NULL &&
addSecondOp.isLoadConst())
{
// add
// firstChild (into baseRegister)
// add/sub (secondChild)
// mul/shl (addFirstChild)
// ? (into indexNode)
// stride
// const (addSecondChild)
//
intptr_t offset = TR::TreeEvaluator::integerConstNodeValue(addSecondChild, cg);
if (secondOp.isSub())
offset = -offset;
TR::Register *baseRegister;
if (firstChild->getOpCodeValue() == TR::loadaddr &&
firstChild->getSymbolReference()->getSymbol()->isMethodMetaData())
{
baseRegister = cg->getMethodMetaDataRegister();
offset += firstChild->getSymbolReference()->getOffset();
}
else
{
baseRegister = cg->evaluate(firstChild);
}
indexNode = addFirstChild->getFirstChild();
indexRegister = evaluateAndForceSize(indexNode, nodeIs64Bit, cg);
leaMR = generateX86MemoryReference(baseRegister, indexRegister, stride, offset, cg);
targetRegister = cg->allocateRegister();
generateRegMemInstruction(LEARegMem(nodeIs64Bit), node, targetRegister, leaMR, cg);
cg->decReferenceCount(addSecondChild);
cg->decReferenceCount(addFirstChild->getFirstChild());
cg->decReferenceCount(addFirstChild->getSecondChild());
cg->decReferenceCount(addFirstChild);
cg->decReferenceCount(secondChild);
cg->decReferenceCount(firstChild);
node->setRegister(targetRegister);
return true;
}
}
intptr_t dummyConstValue = 0;
if (secondOp.isLoadConst())
{
constNode = secondChild;
}
if (firstChild->getRegister() == NULL && firstChild->getReferenceCount() == 1)
{
stride1 = TR::MemoryReference::getStrideForNode(firstChild, cg);
}
if (secondChild->getRegister() == NULL && secondChild->getReferenceCount() == 1)
{
stride2 = TR::MemoryReference::getStrideForNode(secondChild, cg);
}
if (stride1 | stride2)
{
if (stride1)
{
indexNode = firstChild;
stride = stride1;
baseNode = secondChild;
}
else
{
indexNode = secondChild;
stride = stride2;
baseNode = firstChild;
}
}
if (indexNode)
{
// add (** children may be reversed **)
// baseNode (possibly also constNode)
// mul/shl (indexNode)
// ? (into indexRegister)
// stride
//
indexRegister = cg->evaluate(indexNode->getFirstChild());
TR::Node *tempNode;
if (constNode)
{
// can be a long for an aladd
if (constNode->getOpCodeValue() == TR::lconst)
leaMR = generateX86MemoryReference(NULL,
indexRegister,
stride,
constNode->getLongInt(), cg);
else
leaMR = generateX86MemoryReference(NULL,
indexRegister,
stride,
constNode->getInt(), cg);
tempNode = NULL;
}
else if (baseNode->getRegister() == NULL &&
baseNode->getReferenceCount() == 1 &&
baseNode->getOpCode().isAdd() &&
baseNode->getSecondChild()->getOpCode().isLoadConst() &&
TR::TreeEvaluator::constNodeValueIs32BitSigned(baseNode->getSecondChild(), &dummyConstValue, cg))
{
// add (** children may be reversed **)
// add (baseNode)
// ?
// const
// mul/shl (indexNode)
// ?
// stride
//
TR_ASSERT(!constNode, "cannot have two const nodes in this pattern");
constNode = baseNode->getSecondChild();
leaMR = generateX86MemoryReference(cg->evaluate(baseNode->getFirstChild()),
indexRegister,
stride,
TR::TreeEvaluator::integerConstNodeValue(constNode, cg), cg);
tempNode = baseNode->getFirstChild();
}
else
{
leaMR = generateX86MemoryReference(cg->evaluate(baseNode),
indexRegister,
stride,
0, cg);
tempNode = baseNode;
}
targetRegister = cg->allocateRegister();
generateRegMemInstruction(LEARegMem(nodeIs64Bit), node, targetRegister, leaMR, cg);
if (tempNode)
{
cg->decReferenceCount(tempNode);
}
cg->decReferenceCount(indexNode->getFirstChild());
cg->decReferenceCount(indexNode->getSecondChild());
cg->decReferenceCount(indexNode);
if (constNode)
{
cg->decReferenceCount(constNode);
}
node->setRegister(targetRegister);
return true;
}
else if (constNode &&
TR::TreeEvaluator::constNodeValueIs32BitSigned(constNode, &dummyConstValue, cg))
{
// add
// firstChild
// const
//
if (firstChild->getRegister() == NULL &&
firstChild->getReferenceCount() == 1 &&
firstOp.isAdd())
{
// add
// add (firstChild)
// ?
// ?
// const
//
// We should only traverse more deeply if firstChild's children do not have
// associated registers. Otherwise, we risk extending the lifetimes of
// firstChild's grandchildren's registers, and hence adding register pressure.
//
if (firstChild->getFirstChild()->getReferenceCount() == 1 &&
firstChild->getFirstChild()->getRegister() == NULL)
{
stride1 = TR::MemoryReference::getStrideForNode(firstChild->getFirstChild(), cg);
}
if (firstChild->getSecondChild()->getReferenceCount() == 1 &&
firstChild->getSecondChild()->getRegister() == NULL)
{
stride2 = TR::MemoryReference::getStrideForNode(firstChild->getSecondChild(), cg);
}
if (stride1 | stride2)
{
if (stride1)
{
// add
// add (firstChild)
// mul/shl (indexNode)
// ?
// stride1
// ? (baseNode)
// const (constNode)
//
baseNode = firstChild->getSecondChild();
indexNode = firstChild->getFirstChild()->getFirstChild();
TR_ASSERT(node->getSize() == indexNode->getSize(), "evaluateAndForceSize never needed for indexNode");
leaMR = generateX86MemoryReference(cg->evaluate(baseNode),
cg->evaluate(indexNode),
stride1,
TR::TreeEvaluator::integerConstNodeValue(constNode, cg),
cg);
cg->decReferenceCount(firstChild->getFirstChild()->getSecondChild());
cg->decReferenceCount(firstChild->getFirstChild());
}
else
{
// add
// add (firstChild)
// ? (baseNode)
// mul/shl (indexNode)
// ?
// stride2
// const (constNode)
//
baseNode = firstChild->getFirstChild();
indexNode = firstChild->getSecondChild()->getFirstChild();
TR_ASSERT(node->getSize() == baseNode->getSize(), "evaluateAndForceSize never needed for baseNode");
leaMR = generateX86MemoryReference(cg->evaluate(baseNode),
cg->evaluate(indexNode),
stride2,
TR::TreeEvaluator::integerConstNodeValue(constNode, cg),
cg);
cg->decReferenceCount(firstChild->getSecondChild()->getSecondChild());
cg->decReferenceCount(firstChild->getSecondChild());
}
}
else
{
baseNode = firstChild->getFirstChild();
indexNode = firstChild->getSecondChild();
TR_ASSERT(node->getSize() == baseNode->getSize(), "evaluateAndForceSize never needed for baseNode");
if (indexNode->getOpCode().isLoadConst())
{
// add
// add
// ? (baseNode)
// const (indexNode)
// const
//
leaMR = generateX86MemoryReference(cg->evaluate(baseNode),
TR::TreeEvaluator::integerConstNodeValue(constNode,cg) +
TR::TreeEvaluator::integerConstNodeValue(indexNode, cg), cg);
}
else
{
leaMR = generateX86MemoryReference(cg->evaluate(baseNode),
cg->evaluate(indexNode),
0,
TR::TreeEvaluator::integerConstNodeValue(constNode, cg), cg);
}
}
targetRegister = cg->allocateRegister();
generateRegMemInstruction(LEARegMem(nodeIs64Bit), node, targetRegister, leaMR, cg);
cg->decReferenceCount(baseNode);
cg->decReferenceCount(indexNode);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(constNode);
node->setRegister(targetRegister);
return true;
}
}
else if(firstChild->getOpCode().getOpCodeValue() == TR::loadaddr &&
(firstChild->getRegister() == NULL && firstChild->getReferenceCount() == 1))
{
// add
// loadaddr (firstChild)
// ? (secondChild)
// fold parent add of 'loadaddr + secondChild' into lea generated for the loadaddr
bool isInternal = node->getOpCode().isArrayRef()
&& node->isInternalPointer()
&& node->getPinningArrayPointer();
leaMR = generateX86MemoryReference(firstChild->getSymbolReference(), cg);
leaMR->populateMemoryReference(secondChild, cg);
// generateLEAForLoadAddr calls leaMR->decNodeReferenceCounts(cg)
//
// leaMR is not first chid's memory reference, it also plus second second child,
// so can't allocate register directly according to first kid's symbol
targetRegister = TR::TreeEvaluator::generateLEAForLoadAddr(firstChild, leaMR, firstChild->getSymbolReference(), cg, isInternal);
cg->decReferenceCount(firstChild);
node->setRegister(targetRegister);
return true;
}
else if((firstChild->getOpCode().isSub() || firstChild->getOpCode().isAdd()) &&
(firstChild->getOpCode().getSize() == node->getOpCode().getSize()) &&
(firstChild->getRegister() == NULL) &&
(firstChild->getSecondChild()->getOpCode().isLoadConst()) &&
TR::TreeEvaluator::constNodeValueIs32BitSigned(firstChild->getSecondChild(), &dummyConstValue, cg) &&
(firstChild->getReferenceCount() == 1)
)
{
// add
// sub/add (firstChild)
// child 0
// loadconstant
// ? (second)
intptr_t val = TR::TreeEvaluator::integerConstNodeValue(firstChild->getSecondChild(), cg);
if (firstChild->getOpCode().isSub())
val = -val;
leaMR = generateX86MemoryReference(cg->evaluate(firstChild->getFirstChild()),
cg->evaluate(secondChild),
0,
val,
cg);
targetRegister = cg->allocateRegister();
generateRegMemInstruction(LEARegMem(nodeIs64Bit), node, targetRegister, leaMR, cg);
node->setRegister(targetRegister);
cg->decReferenceCount(firstChild->getFirstChild());
cg->decReferenceCount(firstChild->getSecondChild());
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return true;
}
return false;
}
static void evaluateIfNotConst(TR::Node *node, TR::CodeGenerator *cg)
{
if (!node->getOpCode().isLoadConst())
{
diagnostic("Evaluating Non Constant %p (%s)\n",
node, node->getOpCode().getName());
cg->evaluate(node);
}
else
{
diagnostic("Not evaluating Constant %p (%s)\n",
node, node->getOpCode().getName());
}
}
TR::Register *OMR::X86::TreeEvaluator::integerDualAddOrSubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR_ASSERT((node->getOpCodeValue() == TR::luaddh) || (node->getOpCodeValue() == TR::ladd)
|| (node->getOpCodeValue() == TR::lusubh) || (node->getOpCodeValue() == TR::lsub)
, "Unexpected dual operator. Expected ladd, luaddh, lsub, or lusubh as part of cyclic dual.");
TR::Node *pair = node->getChild(2);
bool requiresCarryOnEntry = cg->requiresCarry();
if (pair->getReferenceCount() == 1)
{
diagnostic("Found %p (%s) with only reference to %p (%s)\n",
node, node->getOpCode().getName(),
pair, pair->getOpCode().getName());
if (node->isDualHigh())
{
// for high part carry is still required, so evaluate the children for low part for this first
diagnostic("Evaluating Children of %p (%s) for %p (%s)\n",
pair, pair->getOpCode().getName(),
node, node->getOpCode().getName());
evaluateIfNotConst(pair->getFirstChild(), cg);
evaluateIfNotConst(pair->getSecondChild(), cg);
}
else
{
// for low part, high part is not required, but children must be evaluated.
diagnostic("Evaluating Children of %p (%s) for %p (%s) (not required for quad calc)\n",
pair, pair->getOpCode().getName(),
node, node->getOpCode().getName());
evaluateIfNotConst(pair->getFirstChild(), cg);
evaluateIfNotConst(pair->getSecondChild(), cg);
cg->decReferenceCount(pair->getFirstChild());
cg->decReferenceCount(pair->getSecondChild());
}
diagnostic("Evaluating Children of %p (%s) after those of %p (%s)\n",
node, node->getOpCode().getName(),
pair, pair->getOpCode().getName());
evaluateIfNotConst(node->getFirstChild(), cg);
evaluateIfNotConst(node->getSecondChild(), cg);
if (node->isDualHigh())
{
// for high part carry is still required, so evaluate the low part for this first
diagnostic("Evaluating %p (%s) for %p (%s)\n",
pair, pair->getOpCode().getName(),
node, node->getOpCode().getName());
cg->setComputesCarry(true);
cg->evaluate(pair);
}
diagnostic("Evaluating %p (%s) after %p (%s)\n",
node, node->getOpCode().getName(),
pair, pair->getOpCode().getName());
cg->setRequiresCarry(true);
cg->setComputesCarry(true);
cg->evaluate(node);
cg->decReferenceCount(pair);
cg->decReferenceCount(node);
}
else
{
diagnostic("Found %p (%s) for %p (%s)\n",
pair, pair->getOpCode().getName(),
node, node->getOpCode().getName());
TR::Node *lowNode = node->isDualHigh() ? pair : node;
TR::Node *highNode = lowNode->getChild(2);
// Evaluate the children for low part for this first
diagnostic("Evaluating Children of %p (%s) for %p (%s)\n",
lowNode, lowNode->getOpCode().getName(),
highNode, highNode->getOpCode().getName());
evaluateIfNotConst(lowNode->getFirstChild(), cg);
evaluateIfNotConst(lowNode->getSecondChild(), cg);
diagnostic("Evaluating Children of %p (%s) after those for %p (%s)\n",
highNode, highNode->getOpCode().getName(),
lowNode, lowNode->getOpCode().getName());
evaluateIfNotConst(highNode->getFirstChild(), cg);
evaluateIfNotConst(highNode->getSecondChild(), cg);
diagnostic("Evaluating %p (%s) for %p (%s)\n",
lowNode, lowNode->getOpCode().getName(),
highNode, highNode->getOpCode().getName());
cg->setComputesCarry(true);
cg->evaluate(lowNode);
diagnostic("Evaluating %p (%s) after %p (%s)\n",
highNode, highNode->getOpCode().getName(),
lowNode, lowNode->getOpCode().getName());
cg->setRequiresCarry(true);
cg->setComputesCarry(true);
cg->evaluate(highNode);
cg->decReferenceCount(lowNode);
cg->decReferenceCount(highNode);
}
cg->setRequiresCarry(requiresCarryOnEntry);
return node->getRegister();
}
TR::Register *OMR::X86::TreeEvaluator::integerAddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
const TR::ILOpCodes opCode = node->getOpCodeValue();
bool nodeIs64Bit = TR::TreeEvaluator::getNodeIs64Bit(node, cg);
TR::Register *targetRegister = NULL;
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Instruction *instr = NULL;
TR::MemoryReference *tempMR = NULL;
bool oursIsTheOnlyMemRef = true;
bool isWithCarry = (opCode == TR::luaddh);
TR::Compilation *comp = cg->comp();
bool computesCarry = cg->computesCarry();
cg->setComputesCarry(false);
if (node->isDualCyclic() && !computesCarry)
{
// first visit for this node, recurse once
return TR::TreeEvaluator::integerDualAddOrSubEvaluator(node, cg);
}
computesCarry = computesCarry || isWithCarry || node->nodeRequiresConditionCodes();
if (NEED_CC(node) || (opCode == TR::luaddc) || (opCode == TR::iuaddc))
{
TR_ASSERT((nodeIs64Bit && opCode == TR::ladd || opCode == TR::luaddc) ||
(!nodeIs64Bit && opCode == TR::iadd || opCode == TR::iuaddc),
"CC computation not supported for this node %p with opcode %s\n", node, cg->comp()->getDebug()->getName(opCode));
// we need eflags from integerAddAnalyser for the CC sequence
const bool isWithCarry = (opCode == TR::luaddc) || (opCode == TR::iuaddc);
TR_X86BinaryCommutativeAnalyser(cg).integerAddAnalyser(node, AddRegReg(nodeIs64Bit, isWithCarry),
AddRegMem(nodeIs64Bit, isWithCarry),
true, /* produce eflags */
isWithCarry ? node->getChild(2) : 0);
targetRegister = node->getRegister();
return targetRegister;
}
// See if we can generate a direct memory operation. In this case there is no
// target register generated and we return NULL to the caller (which should be
// a store) to indicate that the store has already been done.
//
bool isMemOp = node->isDirectMemoryUpdate();
if (!computesCarry && TR::TreeEvaluator::analyseAddForLEA(node, cg))
{
targetRegister = node->getRegister();
}
else
{
if (isMemOp)
{
// Make sure the original value is evaluated before the update if it
// is going to be used again.
//
if (firstChild->getReferenceCount() > 1)
{
TR::Register *reg = cg->evaluate(firstChild);
tempMR = generateX86MemoryReference(*reg->getMemRef(), 0, cg);
oursIsTheOnlyMemRef = false;
}
else
{
tempMR = generateX86MemoryReference(firstChild, cg);
}
}
intptr_t constValue;
if (!targetRegister &&
secondChild->getOpCode().isLoadConst() &&
(secondChild->getRegister() == NULL) &&
((TR::TreeEvaluator::constNodeValueIs32BitSigned(secondChild, &constValue, cg)) ||
(comp->useCompressedPointers() &&
(constValue == 0) &&
firstChild->getReferenceCount() > 1 && !isMemOp)) &&
performTransformation(comp, "O^O analyseAddForLEA: checking that second node is a memory reference %x\n", constValue))
{
if (!isMemOp)
targetRegister = cg->evaluate(firstChild);
bool internalPointerMismatch = false;
if (targetRegister &&
node->getOpCode().isArrayRef() &&
node->isInternalPointer())
{
if (targetRegister->containsInternalPointer())
{
if (node->getPinningArrayPointer() != targetRegister->getPinningArrayPointer())
{
internalPointerMismatch = true;
}
}
}
// We cannot re-use target register if this is a TR::aiadd and it
// has reference count > 1; this is because the TR::aiadd should NOT
// be marked as a collected reference whereas the first child (base)
// may be marked as a collected reference. Thus re-using the same register
// would cause an inconsistency.
//
if (targetRegister &&
(firstChild->getReferenceCount() > 1 ||
(node->getOpCode().isArrayRef() &&
(internalPointerMismatch || targetRegister->containsCollectedReference()))))
{
TR::Register *firstOperandReg = targetRegister;
// For a non-internal pointer TR::aiadd created when merging news (for example)
// commoning is permissible across a GC point; however the register
// needs to be marked as a collected reference for GC to behave correctly;
// note that support for internal pointer TR::aiadd (e.g. array access) is not present
// still
//
if (targetRegister->containsCollectedReference() &&
(node->getOpCode().isArrayRef()) &&
!node->isInternalPointer())
{
targetRegister = cg->allocateCollectedReferenceRegister();
}
else
{
targetRegister = cg->allocateRegister();
}
// comp()->useCompressedPointers
// ladd
// ==>iu2l
// the firstChild is commoned, so the add & iu2l will get different registers
//
TR::Register *tempReg = firstOperandReg;
if (TR::TreeEvaluator::genNullTestSequence(node, firstOperandReg, targetRegister, cg))
tempReg = targetRegister;
if (computesCarry)
{
generateRegRegInstruction(MOVRegReg(nodeIs64Bit), node, targetRegister, tempReg, cg);
generateRegImmInstruction(AddRegImm4(nodeIs64Bit, isWithCarry), node, targetRegister, constValue, cg);
}
else
{
tempMR = generateX86MemoryReference(tempReg, constValue, cg);
generateRegMemInstruction(LEARegMem(nodeIs64Bit), node, targetRegister, tempMR, cg);
}
}
else
{
if (constValue >= -128 && constValue <= 127)
{
if (computesCarry)
{
if (isMemOp)
instr = generateMemImmInstruction(AddMemImms(nodeIs64Bit, isWithCarry), node, tempMR, constValue, cg);
else
instr = generateRegImmInstruction(AddRegImms(nodeIs64Bit, isWithCarry), node, targetRegister, constValue, cg);
}
else if (constValue == 1)
{
if (isMemOp)
instr = generateMemInstruction(INCMem(nodeIs64Bit), node, tempMR, cg);
else
instr = generateRegImmInstruction(ADDRegImms(nodeIs64Bit), node, targetRegister, 1, cg);
}
else if (constValue == -1)
{
if (isMemOp)
instr = generateMemInstruction(DECMem(nodeIs64Bit), node, tempMR, cg);
else
instr = generateRegImmInstruction(SUBRegImms(nodeIs64Bit), node, targetRegister, 1, cg);
}
else
{
if (isMemOp)
instr = generateMemImmInstruction(ADDMemImms(nodeIs64Bit), node, tempMR, constValue, cg);
else
instr = generateRegImmInstruction(ADDRegImms(nodeIs64Bit), node, targetRegister, constValue, cg);
}
}
else if ((constValue == 128) && !computesCarry)
{
if (isMemOp)
instr = generateMemImmInstruction(SUBMemImms(nodeIs64Bit), node, tempMR, (uint32_t)-128, cg);
else
instr = generateRegImmInstruction(SUBRegImms(nodeIs64Bit), node, targetRegister, (uint32_t)-128, cg);
}
else
{
// comp()->useCompressedPointers
// ladd
// iu2l
// the firstChild is not commoned
//
TR::TreeEvaluator::genNullTestSequence(node, targetRegister, targetRegister, cg);
if (isMemOp)
instr = generateMemImmInstruction(AddMemImm4(nodeIs64Bit, isWithCarry), node, tempMR, constValue, cg);
else
instr = generateRegImmInstruction(AddRegImm4(nodeIs64Bit, isWithCarry), node, targetRegister, constValue, cg);
}
if (debug("traceMemOp"))
diagnostic("\n*** Node [" POINTER_PRINTF_FORMAT "] inc by const %d", node, constValue);
}
}
else if (isMemOp)
{
instr = generateMemRegInstruction(AddMemReg(nodeIs64Bit, isWithCarry), node, tempMR, cg->evaluate(secondChild), cg);
if (debug("traceMemOp"))
diagnostic("\n*** Node [" POINTER_PRINTF_FORMAT "] inc by var", node);
}
if (isMemOp)
{
if (oursIsTheOnlyMemRef)
tempMR->decNodeReferenceCounts(cg);
else
tempMR->stopUsingRegisters(cg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
cg->setImplicitExceptionPoint(instr);
}
else if (targetRegister)
{
node->setRegister(targetRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
}
else
{
TR_X86BinaryCommutativeAnalyser temp(cg);
temp.integerAddAnalyser(node, AddRegReg(nodeIs64Bit, isWithCarry), AddRegMem(nodeIs64Bit, isWithCarry), computesCarry, 0);
targetRegister = node->getRegister();
}
}
if (targetRegister &&
node->getOpCode().isArrayRef() &&
node->isInternalPointer())
{
if (node->getPinningArrayPointer())
{
targetRegister->setContainsInternalPointer();
targetRegister->setPinningArrayPointer(node->getPinningArrayPointer());
}
else
{
TR::Node *firstChild = node->getFirstChild();
if ((firstChild->getOpCodeValue() == TR::aload) &&
firstChild->getSymbolReference()->getSymbol()->isAuto() &&
firstChild->getSymbolReference()->getSymbol()->isPinningArrayPointer())
{
targetRegister->setContainsInternalPointer();
if (!firstChild->getSymbolReference()->getSymbol()->isInternalPointer())
{
targetRegister->setPinningArrayPointer(firstChild->getSymbolReference()->getSymbol()->castToAutoSymbol());
}
else
targetRegister->setPinningArrayPointer(firstChild->getSymbolReference()->getSymbol()->castToInternalPointerAutoSymbol()->getPinningArrayPointer());
}
else if (firstChild->getRegister() &&
firstChild->getRegister()->containsInternalPointer())
{
targetRegister->setContainsInternalPointer();
targetRegister->setPinningArrayPointer(firstChild->getRegister()->getPinningArrayPointer());
}
}
}
return targetRegister;
}
TR::Register *OMR::X86::TreeEvaluator::baddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *targetRegister = NULL;
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Instruction *instr = NULL;
bool countsAreDecremented = false;
TR::MemoryReference *tempMR = NULL;
bool oursIsTheOnlyMemRef = true;
TR::Compilation *comp = cg->comp();
// This comment has been tested on X86_32 and X86_64 Linux only, and has not been tested
// on any Windows operating systems.
// TR_ASSERT(cg->comp()->target().is32Bit(), "AMD64 baddEvaluator not yet supported");
// See if we can generate a direct memory operation. In this case there is no
// target register generated and we return NULL to the caller (which should be
// a store) to indicate that the store has already been done.
//
if (NEED_CC(node))
{
TR_ASSERT(node->getOpCodeValue() == TR::badd,
"CC computation not supported for this node %p with opcode %s\n", node, cg->comp()->getDebug()->getName(node->getOpCode()));
// we need eflags from integerAddAnalyser for the CC sequence
TR_X86BinaryCommutativeAnalyser(cg).integerAddAnalyser(node, ADD1RegReg,
ADD1RegMem,
true/* produce eflags */);
targetRegister = node->getRegister();
return targetRegister;
}
bool isMemOp = node->isDirectMemoryUpdate();
if (isMemOp)
{
// Make sure the original value is evaluated before the update if it
// is going to be used again.
//
if (firstChild->getReferenceCount() > 1)
{
TR::Register *reg = cg->evaluate(firstChild);
tempMR = generateX86MemoryReference(*reg->getMemRef(), 0, cg);