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OMRCodeGenerator.cpp
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OMRCodeGenerator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
// On zOS XLC linker can't handle files with same name at link time.
// This workaround with pragma is needed. What this does is essentially
// give a different name to the codesection (csect) for this file. So it
// doesn't conflict with another file with the same name.
#pragma csect(CODE,"TRZCGBase#C")
#pragma csect(STATIC,"TRZCGBase#S")
#pragma csect(TEST,"TRZCGBase#T")
#include <algorithm>
#include <limits.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "codegen/BackingStore.hpp"
#include "codegen/CodeGenPhase.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/CodeGenerator_inlines.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/GCStackAtlas.hpp"
#include "codegen/GCStackMap.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LinkageConventionsEnum.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/RecognizedMethods.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/RegisterIterator.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/Snippet.hpp"
#include "codegen/StorageInfo.hpp"
#include "codegen/SystemLinkage.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "compile/Compilation.hpp"
#include "compile/Method.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "compile/VirtualGuard.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "control/Recompilation.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "codegen/PrivateLinkage.hpp"
#include "control/RecompilationInfo.hpp"
#endif
#include "cs2/hashtab.h"
#include "env/CompilerEnv.hpp"
#include "env/IO.hpp"
#include "env/Processors.hpp"
#include "env/StackMemoryRegion.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/AliasSetInterface.hpp"
#include "il/AutomaticSymbol.hpp"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ParameterSymbol.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/StaticSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Array.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "infra/BitVector.hpp"
#include "infra/Cfg.hpp"
#include "infra/Flags.hpp"
#include "infra/HashTab.hpp"
#include "infra/List.hpp"
#include "infra/Random.hpp"
#include "infra/SimpleRegex.hpp"
#include "infra/Stack.hpp"
#include "infra/CfgEdge.hpp"
#include "optimizer/OptimizationManager.hpp"
#include "optimizer/Optimizations.hpp"
#include "optimizer/Optimizer.hpp"
#include "optimizer/RegisterCandidate.hpp"
#include "optimizer/Structure.hpp"
#include "optimizer/DataFlowAnalysis.hpp"
#include "ras/Debug.hpp"
#include "ras/DebugCounter.hpp"
#include "ras/Delimiter.hpp"
#include "runtime/CodeCache.hpp"
#include "runtime/Runtime.hpp"
#include "z/codegen/CallSnippet.hpp"
#include "z/codegen/EndianConversion.hpp"
#include "z/codegen/OpMemToMem.hpp"
#include "z/codegen/S390Evaluator.hpp"
#include "z/codegen/S390GenerateInstructions.hpp"
#include "z/codegen/S390Instruction.hpp"
#include "z/codegen/S390OutOfLineCodeSection.hpp"
#include "z/codegen/SystemLinkageLinux.hpp"
#include "z/codegen/SystemLinkagezOS.hpp"
#if J9_PROJECT_SPECIFIC
#include "z/codegen/S390Recompilation.hpp"
#include "z/codegen/S390Register.hpp"
#endif
class TR_IGNode;
namespace TR { class DebugCounterBase; }
namespace TR { class SimpleRegex; }
#define OPT_DETAILS "O^O CODE GENERATION: "
bool compareNodes(TR::Node * node1, TR::Node * node2, TR::CodeGenerator *cg);
bool isMatchingStoreRestore(TR::Instruction *cursorLoad, TR::Instruction *cursorStore, TR::CodeGenerator *cg);
void handleLoadWithRegRanges(TR::Instruction *inst, TR::CodeGenerator *cg);
void
OMR::Z::CodeGenerator::preLowerTrees()
{
OMR::CodeGenerator::preLowerTrees();
_ialoadUnneeded.init();
}
void
OMR::Z::CodeGenerator::lowerTreesWalk(TR::Node * parent, TR::TreeTop * treeTop, vcount_t visitCount)
{
parent->setVisitCount(visitCount);
self()->lowerTreesPreChildrenVisit(parent, treeTop, visitCount);
// Go through the subtrees and lower any nodes that need to be lowered. This
// involves a call to the VM to replace the trees with other trees.
//
for (int32_t childCount = 0; childCount < parent->getNumChildren(); childCount++)
{
TR::Node *child = parent->getChild(childCount);
// If the subtree needs to be lowered, call the VM to lower it
//
if (child->getVisitCount() != visitCount)
{
self()->lowerTreesWalk(child, treeTop, visitCount);
self()->lowerTreeIfNeeded(child, childCount, parent, treeTop);
}
self()->checkIsUnneededIALoad(parent, child, treeTop);
}
self()->lowerTreesPostChildrenVisit(parent, treeTop, visitCount);
}
void
OMR::Z::CodeGenerator::checkIsUnneededIALoad(TR::Node *parent, TR::Node *node, TR::TreeTop *tt)
{
ListIterator<TR_Pair<TR::Node, int32_t> > listIter(&_ialoadUnneeded);
bool inList = false;
if (node->getOpCodeValue() == TR::aloadi)
{
TR_Pair<TR::Node, int32_t> *ptr;
for (ptr = listIter.getFirst(); ptr; ptr = listIter.getNext())
{
if (ptr->getKey() == node)
{
inList = true;
break;
}
}
if (inList)
{
uintptr_t temp = (uintptr_t)ptr->getValue();
int32_t updatedTemp = (int32_t)temp + 1;
ptr->setValue((int32_t*)(intptr_t)updatedTemp);
}
else // Not in list
{
// We only need to track future references to this iaload if refcount > 1
if (node->getReferenceCount() > 1)
{
uint32_t *temp ;
TR_Pair<TR::Node, int32_t> *newEntry = new (self()->trStackMemory()) TR_Pair<TR::Node, int32_t> (node, (int32_t *)1);
_ialoadUnneeded.add(newEntry);
}
node->setUnneededIALoad (true);
}
}
if (node->isUnneededIALoad())
{
if (parent->getOpCodeValue() == TR::ifacmpne || parent->getOpCodeValue() == TR::ificmpeq || parent->getOpCodeValue() == TR::ificmpne || parent->getOpCodeValue() == TR::ifacmpeq)
{
if (!parent->isNopableInlineGuard() || !self()->getSupportsVirtualGuardNOPing())
{
node->setUnneededIALoad(false);
}
else
{
TR_VirtualGuard * virtualGuard = self()->comp()->findVirtualGuardInfo(parent);
if (!parent->isHCRGuard() && !parent->isOSRGuard() && !self()->comp()->performVirtualGuardNOPing() &&
self()->comp()->isVirtualGuardNOPingRequired(virtualGuard) &&
virtualGuard->canBeRemoved())
{
node->setUnneededIALoad(false);
}
}
}
else if (parent->getOpCode().isNullCheck())
{
traceMsg(self()->comp(), "parent %p appears to be a nullcheck over node: %p\n", parent, node);
}
else if (node->getOpCodeValue() == TR::aloadi && !(node->isClassPointerConstant() || node->isMethodPointerConstant()) || parent->getOpCode().isNullCheck())
{
node->setUnneededIALoad(false);
}
else if ((parent->getOpCodeValue() != TR::ifacmpne || tt->getNode()->getOpCodeValue() != TR::ifacmpne))
{
node->setUnneededIALoad(false);
}
}
}
void
OMR::Z::CodeGenerator::lowerTreesPropagateBlockToNode(TR::Node *node)
{
#ifdef J9_PROJECT_SPECIFIC
if (!node->getType().isBCD())
#endif
{
OMR::CodeGenerator::lowerTreesPropagateBlockToNode(node);
}
}
void
OMR::Z::CodeGenerator::lowerTreeIfNeeded(
TR::Node *node,
int32_t childNumberOfNode,
TR::Node *parent,
TR::TreeTop *tt)
{
OMR::CodeGenerator::lowerTreeIfNeeded(node, childNumberOfNode, parent, tt);
// Z
if (self()->comp()->target().cpu.isZ() &&
(node->getOpCode().isLoadVar() || node->getOpCode().isStore()) &&
node->getOpCode().isIndirect())
{
TR::Node* add1 = NULL;
TR::Node* add2 = NULL;
TR::Node* sub = NULL;
TR::Node* const1 = NULL;
TR::Node* const2 = NULL;
TR::Node* base = NULL;
TR::Node* index = NULL;
TR::ILOpCodes addOp, subOp, constOp;
if (self()->comp()->target().is64Bit())
{
addOp = TR::aladd;
subOp = TR::lsub;
constOp = TR::lconst;
}
else
{
addOp = TR::aiadd;
subOp = TR::isub;
constOp = TR::iconst;
}
if (node->getFirstChild()->getOpCodeValue() == addOp)
add1 = node->getFirstChild();
if (add1 && add1->getFirstChild()->getOpCodeValue() == addOp)
{
add2 = add1->getFirstChild();
base = add2->getFirstChild();
}
if (add1 && add1->getSecondChild()->getOpCodeValue() == subOp)
sub = add1->getSecondChild();
if (add2 && add2->getSecondChild()->getOpCode().isLoadConst())
{
const1 = add2->getSecondChild();
index = add1->getSecondChild();
}
if (sub && sub->getSecondChild()->getOpCode().isLoadConst())
{
const2 = sub->getSecondChild();
index = sub->getFirstChild();
}
if (add1 && add2 && const1 == NULL && const2 == NULL)
{
if (add2->getFirstChild()->getOpCodeValue() == addOp)
{
index = add2->getSecondChild();
add2 = add2->getFirstChild();
base = add2->getFirstChild();
if (add2->getSecondChild()->getOpCode().isLoadConst())
const2 = add2->getSecondChild();
if (const2 && add1->getSecondChild()->getOpCode().isLoadConst())
const1 = add1->getSecondChild();
}
}
if (add1 && add2 && const1 && performTransformation(self()->comp(), "%sBase/index/displacement form addressing prep for node [%p]\n", OPT_DETAILS, node))
{
// traceMsg(comp(), "&&& Found pattern root=%llx add1=%llx add2=%llx const1=%llx sub=%llx const2=%llx\n", node, add1, add2, const1, sub, const2);
intptr_t offset = 0;
if (self()->comp()->target().is64Bit())
{
offset = const1->getLongInt();
if (const2)
if (sub)
offset -= const2->getLongInt();
else
offset += const2->getLongInt();
}
else
{
offset = const1->getInt();
if (const2)
if (sub)
offset -= const2->getInt();
else
offset += const2->getInt();
}
TR::Node* newAdd2 = TR::Node::create(addOp, 2, base, index);
TR::Node* newConst = TR::Node::create(constOp, 0);
if (self()->comp()->target().is64Bit())
newConst->setLongInt(offset);
else
newConst->setInt(offset);
TR::Node* newAdd1 = TR::Node::create(addOp, 2, newAdd2, newConst);
node->setAndIncChild(0, newAdd1);
add1->recursivelyDecReferenceCount();
}
}
}
bool OMR::Z::CodeGenerator::supportsInliningOfIsInstance()
{
return !self()->comp()->getOption(TR_DisableInlineIsInstance);
}
bool OMR::Z::CodeGenerator::canTransformUnsafeCopyToArrayCopy()
{
static char *disableTran = feGetEnv("TR_DISABLEUnsafeCopy");
return (!disableTran && !self()->comp()->getCurrentMethod()->isJNINative() && !self()->comp()->getOption(TR_DisableArrayCopyOpts));
}
bool OMR::Z::CodeGenerator::supportsDirectIntegralLoadStoresFromLiteralPool()
{
return true;
}
OMR::Z::CodeGenerator::CodeGenerator(TR::Compilation *comp)
: OMR::CodeGenerator(comp),
_extentOfLitPool(-1),
_recompPatchInsnList(getTypedAllocator<TR::Instruction*>(comp->allocator())),
_constantHash(comp->allocator()),
_constantHashCur(_constantHash),
_constantList(getTypedAllocator<TR::S390ConstantDataSnippet*>(comp->allocator())),
_writableList(getTypedAllocator<TR::S390WritableDataSnippet*>(comp->allocator())),
_transientLongRegisters(comp->trMemory()),
_snippetDataList(getTypedAllocator<TR::S390ConstantDataSnippet*>(comp->allocator())),
_outOfLineCodeSectionList(getTypedAllocator<TR_S390OutOfLineCodeSection*>(comp->allocator())),
_returnTypeInfoInstruction(NULL),
_interfaceSnippetToPICsListHashTab(NULL),
_currentCheckNode(NULL),
_currentBCDCHKHandlerLabel(NULL),
_nodesToBeEvaluatedInRegPairs(comp->allocator()),
_ccInstruction(NULL),
_previouslyAssignedTo(comp->allocator("LocalRA")),
_firstTimeLiveOOLRegisterList(NULL),
_methodBegin(NULL),
_methodEnd(NULL),
_afterRA(false)
{
}
void
OMR::Z::CodeGenerator::initialize()
{
self()->OMR::CodeGenerator::initialize();
TR::CodeGenerator *cg = self();
TR::Compilation *comp = self()->comp();
_cgFlags = 0;
// Initialize Linkage for Code Generator
cg->initializeLinkage();
_unlatchedRegisterList = (TR::RealRegister**)cg->trMemory()->allocateHeapMemory(sizeof(TR::RealRegister*)*(TR::RealRegister::NumRegisters));
_unlatchedRegisterList[0] = 0; // mark that list is empty
bool enableBranchPreload = comp->getOption(TR_EnableBranchPreload);
bool disableBranchPreload = comp->getOption(TR_DisableBranchPreload);
if (enableBranchPreload || (!disableBranchPreload && comp->isOptServer() && comp->target().cpu.isAtLeast(OMR_PROCESSOR_S390_ZEC12)))
cg->setEnableBranchPreload();
else
cg->setDisableBranchPreload();
static bool bpp = (feGetEnv("TR_BPRP")!=NULL);
if ((enableBranchPreload && bpp) || (bpp && !disableBranchPreload && comp->isOptServer() && comp->target().cpu.isAtLeast(OMR_PROCESSOR_S390_ZEC12)))
cg->setEnableBranchPreloadForCalls();
else
cg->setDisableBranchPreloadForCalls();
if (cg->supportsBranchPreloadForCalls())
{
_callsForPreloadList = new (cg->trHeapMemory()) TR::list<TR_BranchPreloadCallData*>(getTypedAllocator<TR_BranchPreloadCallData*>(comp->allocator()));
}
cg->setOnDemandLiteralPoolRun(true);
cg->setGlobalStaticBaseRegisterOn(false);
cg->setGlobalPrivateStaticBaseRegisterOn(false);
cg->setMultiplyIsDestructive();
cg->setSupportsSelect();
cg->setSupportsByteswap();
cg->setIsOutOfLineHotPath(false);
cg->setUsesRegisterPairsForLongs();
cg->setSupportsDivCheck();
cg->setSupportsLoweringConstIDiv();
cg->setSupportsTestUnderMask();
// Initialize to be 8 bytes for bodyInfo / methodInfo
cg->setPreJitMethodEntrySize(8);
// Support divided by power of 2 logic in ldivSimplifier
cg->setSupportsLoweringConstLDivPower2();
//enable LM/STM for volatile longs in 32 bit
cg->setSupportsInlinedAtomicLongVolatiles();
cg->setSupportsConstantOffsetInAddressing();
static char * noVGNOP = feGetEnv("TR_NOVGNOP");
if (noVGNOP == NULL)
{
cg->setSupportsVirtualGuardNOPing();
}
if (!comp->getOption(TR_DisableArraySetOpts))
{
cg->setSupportsArraySet();
}
cg->setSupportsArrayCmp();
cg->setSupportsArrayCmpSign();
if (!comp->compileRelocatableCode())
{
cg->setSupportsArrayTranslateTRxx();
}
cg->setSupportsTestCharComparisonControl(); // TRXX instructions on Danu have mask to disable test char comparison.
cg->setSupportsReverseLoadAndStore();
cg->setSupportsSearchCharString(); // CISC Transformation into SRSTU loop - only on z9.
cg->setSupportsTranslateAndTestCharString(); // CISC Transformation into TRTE loop - only on z6.
if (!comp->getOption(TR_DisableTraps) && TR::Compiler->vm.hasResumableTrapHandler(comp))
{
cg->setHasResumableTrapHandler();
}
if (comp->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z196))
{
cg->setSupportsAtomicLoadAndAdd();
}
else
{
// Max min optimization uses the maxMinHelper evaluator which
// requires conditional loads that are not supported below z196
comp->setOption(TR_DisableMaxMinOptimization);
}
if (comp->target().cpu.isAtLeast(OMR_PROCESSOR_S390_ZEC12))
{
cg->setSupportsZonedDFPConversions();
if (comp->target().cpu.supportsFeature(OMR_FEATURE_S390_TE) && !comp->getOption(TR_DisableTM))
cg->setSupportsTM();
}
if (comp->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z13) && !comp->getOption(TR_DisableArch11PackedToDFP))
cg->setSupportsFastPackedDFPConversions();
if (!comp->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z14))
{
comp->setOption(TR_DisableVectorBCD);
}
// Be pessimistic until we can prove we don't exit after doing code-generation
cg->setExitPointsInMethod(true);
#ifdef DEBUG
// Clear internal counters for internal profiling of
// register allocation
cg->clearTotalSpills();
cg->clearTotalRegisterXfers();
cg->clearTotalRegisterMoves();
#endif
// Set up vector register support for machine after zEC12.
// This should also happen before prepareForGRA
if (comp->getOption(TR_DisableSIMD))
{
comp->setOption(TR_DisableAutoSIMD);
comp->setOption(TR_DisableSIMDArrayCompare);
comp->setOption(TR_DisableSIMDArrayTranslate);
comp->setOption(TR_DisableSIMDUTF16BEEncoder);
comp->setOption(TR_DisableSIMDUTF16LEEncoder);
comp->setOption(TR_DisableSIMDStringHashCode);
comp->setOption(TR_DisableVectorRegGRA);
}
cg->setSupportsRecompilation();
// This enables the tactical GRA
cg->setSupportsGlRegDeps();
cg->addSupportedLiveRegisterKind(TR_GPR);
cg->addSupportedLiveRegisterKind(TR_FPR);
cg->addSupportedLiveRegisterKind(TR_VRF);
cg->setLiveRegisters(new (cg->trHeapMemory()) TR_LiveRegisters(comp), TR_GPR);
cg->setLiveRegisters(new (cg->trHeapMemory()) TR_LiveRegisters(comp), TR_FPR);
cg->setLiveRegisters(new (cg->trHeapMemory()) TR_LiveRegisters(comp), TR_VRF);
cg->setSupportsPrimitiveArrayCopy();
cg->setSupportsReferenceArrayCopy();
cg->setSupportsPartialInlineOfMethodHooks();
cg->setSupportsInliningOfTypeCoersionMethods();
cg->setPerformsChecksExplicitly();
_numberBytesReadInaccessible = 4096;
_numberBytesWriteInaccessible = 4096;
// zLinux sTR requires this as well, otherwise cp00f054.C testcase fails in TR_FPStoreReloadElimination.
cg->setSupportsJavaFloatSemantics();
_localF2ISpill = NULL;
_localD2LSpill = NULL;
_nextAvailableBlockIndex = -1;
_currentBlockIndex = -1;
if (comp->getOption(TR_TraceRA))
{
cg->setGPRegisterIterator(new (cg->trHeapMemory()) TR::RegisterIterator(cg->machine(), TR::RealRegister::FirstGPR, TR::RealRegister::LastAssignableGPR));
cg->setFPRegisterIterator(new (cg->trHeapMemory()) TR::RegisterIterator(cg->machine(), TR::RealRegister::FirstFPR, TR::RealRegister::LastFPR));
cg->setVRFRegisterIterator(new (cg->trHeapMemory()) TR::RegisterIterator(cg->machine(), TR::RealRegister::FirstVRF, TR::RealRegister::LastVRF));
}
if (!comp->getOption(TR_DisableTLHPrefetch) && !comp->compileRelocatableCode())
{
cg->setEnableTLHPrefetching();
}
_reusableTempSlot = NULL;
cg->freeReusableTempSlot();
cg->setSupportsProfiledInlining();
cg->getS390Linkage()->setParameterLinkageRegisterIndex(comp->getJittedMethodSymbol());
cg->getS390Linkage()->initS390RealRegisterLinkage();
cg->setAccessStaticsIndirectly(true);
}
OMR::Z::CodeGenerator::CodeGenerator()
: OMR::CodeGenerator(),
_extentOfLitPool(-1),
_recompPatchInsnList(getTypedAllocator<TR::Instruction*>(self()->comp()->allocator())),
_constantHash(self()->comp()->allocator()),
_constantHashCur(_constantHash),
_constantList(getTypedAllocator<TR::S390ConstantDataSnippet*>(self()->comp()->allocator())),
_writableList(getTypedAllocator<TR::S390WritableDataSnippet*>(self()->comp()->allocator())),
_transientLongRegisters(self()->trMemory()),
_snippetDataList(getTypedAllocator<TR::S390ConstantDataSnippet*>(self()->comp()->allocator())),
_outOfLineCodeSectionList(getTypedAllocator<TR_S390OutOfLineCodeSection*>(self()->comp()->allocator())),
_returnTypeInfoInstruction(NULL),
_interfaceSnippetToPICsListHashTab(NULL),
_currentCheckNode(NULL),
_currentBCDCHKHandlerLabel(NULL),
_nodesToBeEvaluatedInRegPairs(self()->comp()->allocator()),
_ccInstruction(NULL),
_previouslyAssignedTo(self()->comp()->allocator("LocalRA")),
_firstTimeLiveOOLRegisterList(NULL),
_methodBegin(NULL),
_methodEnd(NULL),
_afterRA(false)
{
TR::Compilation *comp = self()->comp();
_cgFlags = 0;
// Initialize Linkage for Code Generator
self()->initializeLinkage();
_unlatchedRegisterList = (TR::RealRegister**)self()->trMemory()->allocateHeapMemory(sizeof(TR::RealRegister*)*(TR::RealRegister::NumRegisters));
_unlatchedRegisterList[0] = 0; // mark that list is empty
bool enableBranchPreload = comp->getOption(TR_EnableBranchPreload);
bool disableBranchPreload = comp->getOption(TR_DisableBranchPreload);
if (enableBranchPreload || (!disableBranchPreload && comp->isOptServer() && self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_ZEC12)))
self()->setEnableBranchPreload();
else
self()->setDisableBranchPreload();
static bool bpp = (feGetEnv("TR_BPRP")!=NULL);
if ((enableBranchPreload && bpp) || (bpp && !disableBranchPreload && comp->isOptServer() && self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_ZEC12)))
self()->setEnableBranchPreloadForCalls();
else
self()->setDisableBranchPreloadForCalls();
if (self()->supportsBranchPreloadForCalls())
{
_callsForPreloadList = new (self()->trHeapMemory()) TR::list<TR_BranchPreloadCallData*>(getTypedAllocator<TR_BranchPreloadCallData*>(comp->allocator()));
}
self()->setOnDemandLiteralPoolRun(true);
self()->setGlobalStaticBaseRegisterOn(false);
self()->setGlobalPrivateStaticBaseRegisterOn(false);
self()->setMultiplyIsDestructive();
self()->setSupportsSelect();
self()->setSupportsByteswap();
self()->setIsOutOfLineHotPath(false);
self()->setUsesRegisterPairsForLongs();
self()->setSupportsDivCheck();
self()->setSupportsLoweringConstIDiv();
self()->setSupportsTestUnderMask();
// Initialize to be 8 bytes for bodyInfo / methodInfo
self()->setPreJitMethodEntrySize(8);
// Support divided by power of 2 logic in ldivSimplifier
self()->setSupportsLoweringConstLDivPower2();
//enable LM/STM for volatile longs in 32 bit
self()->setSupportsInlinedAtomicLongVolatiles();
self()->setSupportsConstantOffsetInAddressing();
static char * noVGNOP = feGetEnv("TR_NOVGNOP");
if (noVGNOP == NULL)
{
self()->setSupportsVirtualGuardNOPing();
}
if (!comp->getOption(TR_DisableArraySetOpts))
{
self()->setSupportsArraySet();
}
self()->setSupportsArrayCmp();
self()->setSupportsArrayCmpSign();
if (!comp->compileRelocatableCode())
{
self()->setSupportsArrayTranslateTRxx();
}
self()->setSupportsTestCharComparisonControl(); // TRXX instructions on Danu have mask to disable test char comparison.
self()->setSupportsReverseLoadAndStore();
self()->setSupportsSearchCharString(); // CISC Transformation into SRSTU loop - only on z9.
self()->setSupportsTranslateAndTestCharString(); // CISC Transformation into TRTE loop - only on z6.
if (!comp->getOption(TR_DisableTraps) && TR::Compiler->vm.hasResumableTrapHandler(comp))
{
self()->setHasResumableTrapHandler();
}
if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z196))
{
self()->setSupportsAtomicLoadAndAdd();
}
else
{
// Max min optimization uses the maxMinHelper evaluator which
// requires conditional loads that are not supported below z196
comp->setOption(TR_DisableMaxMinOptimization);
}
if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_ZEC12))
{
self()->setSupportsZonedDFPConversions();
if (self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_S390_TE) && !comp->getOption(TR_DisableTM))
self()->setSupportsTM();
}
if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z13) && !comp->getOption(TR_DisableArch11PackedToDFP))
self()->setSupportsFastPackedDFPConversions();
if (!self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z14))
{
comp->setOption(TR_DisableVectorBCD);
}
// Be pessimistic until we can prove we don't exit after doing code-generation
self()->setExitPointsInMethod(true);
#ifdef DEBUG
// Clear internal counters for internal profiling of
// register allocation
self()->clearTotalSpills();
self()->clearTotalRegisterXfers();
self()->clearTotalRegisterMoves();
#endif
// Set up vector register support for machine after zEC12.
// This should also happen before prepareForGRA
if (comp->getOption(TR_DisableSIMD))
{
comp->setOption(TR_DisableAutoSIMD);
comp->setOption(TR_DisableSIMDArrayCompare);
comp->setOption(TR_DisableSIMDArrayTranslate);
comp->setOption(TR_DisableSIMDUTF16BEEncoder);
comp->setOption(TR_DisableSIMDUTF16LEEncoder);
comp->setOption(TR_DisableSIMDStringHashCode);
comp->setOption(TR_DisableVectorRegGRA);
}
self()->setSupportsRecompilation();
// This enables the tactical GRA
self()->setSupportsGlRegDeps();
self()->addSupportedLiveRegisterKind(TR_GPR);
self()->addSupportedLiveRegisterKind(TR_FPR);
self()->addSupportedLiveRegisterKind(TR_VRF);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(comp), TR_GPR);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(comp), TR_FPR);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(comp), TR_VRF);
self()->setSupportsPrimitiveArrayCopy();
self()->setSupportsReferenceArrayCopy();
self()->setSupportsPartialInlineOfMethodHooks();
self()->setSupportsInliningOfTypeCoersionMethods();
self()->setPerformsChecksExplicitly();
_numberBytesReadInaccessible = 4096;
_numberBytesWriteInaccessible = 4096;
// zLinux sTR requires this as well, otherwise cp00f054.C testcase fails in TR_FPStoreReloadElimination.
self()->setSupportsJavaFloatSemantics();
_localF2ISpill = NULL;
_localD2LSpill = NULL;
_nextAvailableBlockIndex = -1;
_currentBlockIndex = -1;
if (comp->getOption(TR_TraceRA))
{
self()->setGPRegisterIterator(new (self()->trHeapMemory()) TR::RegisterIterator(self()->machine(), TR::RealRegister::FirstGPR, TR::RealRegister::LastAssignableGPR));
self()->setFPRegisterIterator(new (self()->trHeapMemory()) TR::RegisterIterator(self()->machine(), TR::RealRegister::FirstFPR, TR::RealRegister::LastFPR));
self()->setVRFRegisterIterator(new (self()->trHeapMemory()) TR::RegisterIterator(self()->machine(), TR::RealRegister::FirstVRF, TR::RealRegister::LastVRF));
}
if (!comp->getOption(TR_DisableTLHPrefetch) && !comp->compileRelocatableCode())
{
self()->setEnableTLHPrefetching();
}
_reusableTempSlot = NULL;
self()->freeReusableTempSlot();
self()->setSupportsProfiledInlining();
self()->getS390Linkage()->setParameterLinkageRegisterIndex(comp->getJittedMethodSymbol());
self()->getS390Linkage()->initS390RealRegisterLinkage();
self()->setAccessStaticsIndirectly(true);
}
bool
OMR::Z::CodeGenerator::getSupportsBitPermute()
{
return true;
}
bool OMR::Z::CodeGenerator::prepareForGRA()
{
bool enableVectorGRA = self()->getSupportsVectorRegisters() && !self()->comp()->getOption(TR_DisableVectorRegGRA);
if (!_globalRegisterTable)
{
self()->machine()->initializeGlobalRegisterTable();
self()->setGlobalRegisterTable(self()->machine()->getGlobalRegisterTable());
self()->setLastGlobalGPR(self()->machine()->getLastGlobalGPRRegisterNumber());
self()->setLast8BitGlobalGPR(self()->machine()->getLast8BitGlobalGPRRegisterNumber());
self()->setFirstGlobalFPR(self()->machine()->getFirstGlobalFPRRegisterNumber());
self()->setLastGlobalFPR(self()->machine()->getLastGlobalFPRRegisterNumber());
self()->setFirstGlobalVRF(self()->machine()->getFirstGlobalVRFRegisterNumber());
self()->setLastGlobalVRF(self()->machine()->getLastGlobalVRFRegisterNumber());
if (enableVectorGRA)
{
static char * traceVecGRN = feGetEnv("TR_traceVectorGRA");
if (traceVecGRN)
{
printf("Java func: %s func: %s\n", self()->comp()->getCurrentMethod()->nameChars(), __FUNCTION__);
printf("ff %d\t", self()->machine()->getFirstGlobalFPRRegisterNumber());
printf("lf %d\t", self()->machine()->getLastGlobalFPRRegisterNumber());
printf("fof %d\t", self()->machine()->getFirstOverlappedGlobalFPRRegisterNumber());
printf("lof %d\t", self()->machine()->getLastOverlappedGlobalFPRRegisterNumber());
printf("fv %d\t", self()->machine()->getFirstGlobalVRFRegisterNumber());
printf("lv %d\t", self()->machine()->getLastGlobalVRFRegisterNumber());
printf("fov %d\t", self()->machine()->getFirstOverlappedGlobalVRFRegisterNumber());
printf("lov %d\t", self()->machine()->getLastOverlappedGlobalVRFRegisterNumber());
printf("\n--------------------\n");
}
self()->setFirstOverlappedGlobalFPR(self()->machine()->getFirstOverlappedGlobalFPRRegisterNumber());
self()->setLastOverlappedGlobalFPR (self()->machine()->getLastOverlappedGlobalFPRRegisterNumber());
self()->setFirstOverlappedGlobalVRF(self()->machine()->getFirstOverlappedGlobalVRFRegisterNumber());
self()->setLastOverlappedGlobalVRF (self()->machine()->getLastOverlappedGlobalVRFRegisterNumber());
self()->setOverlapOffsetBetweenAliasedGRNs(self()->getFirstOverlappedGlobalVRF() - self()->getFirstOverlappedGlobalFPR());
}
self()->setSupportsGlRegDepOnFirstBlock();
self()->setConsiderAllAutosAsTacticalGlobalRegisterCandidates();
static char * disableLongGRAOn31Bit = feGetEnv("TR390LONGGRA31BIT");
// Only enable Long Globals on 64bit pltfrms
if (disableLongGRAOn31Bit)
{
self()->setDisableLongGRA();
}
// Initialize _globalGPRsPreservedAcrossCalls and _globalFPRsPreservedAcrossCalls
// We call init here because getNumberOfGlobal[FG]PRs() is initialized during the call to initialize() above.
//
_globalGPRsPreservedAcrossCalls.init(NUM_S390_GPR + NUM_S390_FPR, self()->trMemory());
_globalFPRsPreservedAcrossCalls.init(NUM_S390_GPR + NUM_S390_FPR, self()->trMemory());
TR_GlobalRegisterNumber grn;
for (grn = self()->getFirstGlobalGPR(); grn <= self()->getLastGlobalGPR(); grn++)
{
uint32_t globalReg = self()->getGlobalRegister(grn);
if (globalReg != -1 && self()->getS390Linkage()->getPreserved((TR::RealRegister::RegNum) globalReg))
{
_globalGPRsPreservedAcrossCalls.set(grn);
}
}
for (grn = self()->getFirstGlobalFPR(); grn <= self()->getLastGlobalFPR(); grn++)
{
uint32_t globalReg = self()->getGlobalRegister(grn);
if (globalReg != -1 && self()->getS390Linkage()->getPreserved((TR::RealRegister::RegNum) globalReg))
{
_globalFPRsPreservedAcrossCalls.set(grn);
}
}
TR::Linkage *linkage = self()->getS390Linkage();
if (!self()->comp()->getOption(TR_DisableRegisterPressureSimulation))
{
for (int32_t i = 0; i < TR_numSpillKinds; i++)
_globalRegisterBitVectors[i].init(self()->getNumberOfGlobalRegisters(), self()->trMemory());
for (grn=0; grn < self()->getNumberOfGlobalRegisters(); grn++)
{
TR::RealRegister::RegNum reg = (TR::RealRegister::RegNum)self()->getGlobalRegister(grn);
TR_ASSERT(reg != -1, "Register pressure simulator doesn't support gaps in the global register table; reg %d must be removed", grn);
if (self()->getFirstGlobalGPR() <= grn && grn <= self()->getLastGlobalGPR())
{
_globalRegisterBitVectors[ TR_gprSpill ].set(grn);
}
else if (self()->getFirstGlobalFPR() <= grn && grn <= self()->getLastGlobalFPR())
{
_globalRegisterBitVectors[TR_fprSpill].set(grn);
}
else if (self()->getFirstGlobalVRF() <= grn && grn <= self()->getLastGlobalVRF())
{
_globalRegisterBitVectors[TR_vrfSpill].set(grn);
}
if (!linkage->getPreserved(reg))
_globalRegisterBitVectors[ TR_volatileSpill ].set(grn);
if (linkage->getIntegerArgument(reg) || linkage->getFloatArgument(reg))
{
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
}
if (reg == linkage->getMethodMetaDataRegister())
_globalRegisterBitVectors[ TR_vmThreadSpill ].set(grn);
if (reg == linkage->getLitPoolRegister())
_globalRegisterBitVectors[ TR_litPoolSpill ].set(grn);
if (reg == linkage->getStaticBaseRegister() && self()->isGlobalStaticBaseRegisterOn())
_globalRegisterBitVectors[ TR_staticBaseSpill ].set(grn);
if (reg == TR::RealRegister::GPR0)
_globalRegisterBitVectors[ TR_gpr0Spill ].set(grn);
if (reg == TR::RealRegister::GPR1)
_globalRegisterBitVectors[ TR_gpr1Spill ].set(grn);
if (reg == TR::RealRegister::GPR2)
_globalRegisterBitVectors[ TR_gpr2Spill ].set(grn);
if (reg == TR::RealRegister::GPR3)
_globalRegisterBitVectors[ TR_gpr3Spill ].set(grn);
if (reg == TR::RealRegister::GPR4)
_globalRegisterBitVectors[ TR_gpr4Spill ].set(grn);
if (reg == TR::RealRegister::GPR5)
_globalRegisterBitVectors[ TR_gpr5Spill ].set(grn);
if (reg == TR::RealRegister::GPR6)
_globalRegisterBitVectors[ TR_gpr6Spill ].set(grn);
if (reg == TR::RealRegister::GPR7)
_globalRegisterBitVectors[ TR_gpr7Spill ].set(grn);
if (reg == TR::RealRegister::GPR8)
_globalRegisterBitVectors[ TR_gpr8Spill ].set(grn);
if (reg == TR::RealRegister::GPR9)
_globalRegisterBitVectors[ TR_gpr9Spill ].set(grn);
if (reg == TR::RealRegister::GPR10)
_globalRegisterBitVectors[ TR_gpr10Spill ].set(grn);
if (reg == TR::RealRegister::GPR11)
_globalRegisterBitVectors[ TR_gpr11Spill ].set(grn);
if (reg == TR::RealRegister::GPR12)
_globalRegisterBitVectors[ TR_gpr12Spill ].set(grn);
if (reg == TR::RealRegister::GPR13)
_globalRegisterBitVectors[ TR_gpr13Spill ].set(grn);
if (reg == TR::RealRegister::GPR14)
_globalRegisterBitVectors[ TR_gpr14Spill ].set(grn);
if (reg == TR::RealRegister::GPR15)
_globalRegisterBitVectors[ TR_gpr15Spill ].set(grn);
}
if ((grn = self()->machine()->getGlobalCAARegisterNumber()) != -1)
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
if ((grn = self()->machine()->getGlobalEnvironmentRegisterNumber()) != -1)
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
if ((grn = self()->machine()->getGlobalParentDSARegisterNumber()) != -1)
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
if ((grn = self()->machine()->getGlobalReturnAddressRegisterNumber()) != -1)
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
if ((grn = self()->machine()->getGlobalEntryPointRegisterNumber()) != -1)
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
}