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ARM64Instruction.hpp
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ARM64Instruction.hpp
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/*******************************************************************************
* Copyright (c) 2018, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#ifndef ARM64INSTRUCTION_INCL
#define ARM64INSTRUCTION_INCL
#include <stddef.h>
#include <stdint.h>
#include "codegen/ARM64ConditionCode.hpp"
#include "codegen/ARM64ShiftCode.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/UnresolvedDataSnippet.hpp"
#include "il/LabelSymbol.hpp"
#include "infra/Assert.hpp"
class TR_VirtualGuardSite;
namespace TR { class SymbolReference; }
#define ARM64_INSTRUCTION_LENGTH 4
/*
* @brief Answers if the signed integer value can be placed in 7-bit field
* @param[in] intValue : signed integer value
* @return true if the value can be placed in 7-bit field, false otherwise
*/
inline bool constantIsImm7(int32_t intValue)
{
return (-64 <= intValue && intValue < 64);
}
/*
* @brief Answers if the signed integer value can be placed in 9-bit field
* @param[in] intValue : signed integer value
* @return true if the value can be placed in 9-bit field, false otherwise
*/
inline bool constantIsImm9(int32_t intValue)
{
return (-256 <= intValue && intValue < 256);
}
/*
* @brief Answers if the unsigned integer value can be encoded in a 4-bit field
* @param[in] intValue : unsigned integer value
* @return true if the value can be encoded in a 4-bit field, false otherwise
*/
inline bool constantIsUnsignedImm4(uint64_t intValue)
{
return (intValue < (1<<4)); // 16
}
/*
* @brief Answers if the unsigned integer value can be encoded in a 12-bit field
* @param[in] intValue : unsigned integer value
* @return true if the value can be encoded in a 12-bit field, false otherwise
*/
inline bool constantIsUnsignedImm12(uint64_t intValue)
{
return (intValue < (1<<12)); // 4096
}
/*
* @brief Answers if the unsigned integer value can be encoded in a 16-bit field
* @param[in] intValue : unsigned integer value
* @return true if the value can be encoded in a 16-bit field, false otherwise
*/
inline bool constantIsUnsignedImm16(uint64_t intValue)
{
return (intValue < (1<<16)); // 65536
}
/*
* @brief Answers if the signed integer value can be placed in 21-bit field
* @param[in] intValue : signed integer value
* @return true if the value can be placed in 21-bit field, false otherwise
*/
inline bool constantIsSignedImm21(intptr_t intValue)
{
return (-0x100000 <= intValue && intValue < 0x100000);
}
/*
* @brief Answers if the signed integer value can be placed in 28-bit field
* @param[in] intValue : signed integer value
* @return true if the value can be placed in 28-bit field, false otherwise
*/
inline bool constantIsSignedImm28(intptr_t intValue)
{
return (-0x8000000 <= intValue && intValue < 0x8000000);
}
namespace TR
{
class ARM64ImmInstruction : public TR::Instruction
{
uint32_t _sourceImmediate;
public:
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] imm : immediate value
* @param[in] cg : CodeGenerator
*/
ARM64ImmInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, uint32_t imm, TR::CodeGenerator *cg)
: TR::Instruction(op, node, cg), _sourceImmediate(imm)
{
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] imm : immediate value
* @param[in] precedingInstruction : preceding instruction
* @param[in] cg : CodeGenerator
*/
ARM64ImmInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, uint32_t imm,
TR::Instruction *precedingInstruction, TR::CodeGenerator *cg)
: TR::Instruction(op, node, precedingInstruction, cg), _sourceImmediate(imm)
{
}
/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsImm; }
/**
* @brief Gets source immediate
* @return source immediate
*/
uint32_t getSourceImmediate() {return _sourceImmediate;}
/**
* @brief Sets source immediate
* @param[in] si : immediate value
* @return source immediate
*/
uint32_t setSourceImmediate(uint32_t si) {return (_sourceImmediate = si);}
/**
* @brief Encodes the immediate value into the instruction
* @param[in] instruction : instruction address
*/
virtual void insertImmediateField(uint32_t *instruction)
{
// Write the 32-bit immediate with no masking or shifting.
// Be aware this will overwrite the entire 32-bit instruction
// with the immediate value.
//
*instruction = _sourceImmediate;
}
/**
* @brief Generates binary encoding of the instruction
* @return instruction cursor
*/
virtual uint8_t *generateBinaryEncoding();
};
class ARM64RelocatableImmInstruction : public TR::Instruction
{
uintptr_t _sourceImmediate;
TR_ExternalRelocationTargetKind _reloKind;
TR::SymbolReference *_symbolReference;
public:
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] imm : immediate value
* @param[in] relocationKind : relocation kind
* @param[in] cg : CodeGenerator
*/
ARM64RelocatableImmInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, uintptr_t imm,
TR_ExternalRelocationTargetKind relocationKind, TR::CodeGenerator *cg)
: TR::Instruction(op, node, cg),
_sourceImmediate(imm), _reloKind(relocationKind), _symbolReference(NULL)
{
setNeedsAOTRelocation();
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] imm : immediate value
* @param[in] relocationKind : relocation kind
* @param[in] precedingInstruction : preceding instruction
* @param[in] cg : CodeGenerator
*/
ARM64RelocatableImmInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, uintptr_t imm,
TR_ExternalRelocationTargetKind relocationKind, TR::Instruction *precedingInstruction,
TR::CodeGenerator *cg)
: TR::Instruction(op, node, precedingInstruction, cg),
_sourceImmediate(imm), _reloKind(relocationKind), _symbolReference(NULL)
{
setNeedsAOTRelocation();
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] imm : immediate value
* @param[in] relocationKind : relocation kind
* @param[in] sr : symbol reference
* @param[in] cg : CodeGenerator
*/
ARM64RelocatableImmInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, uintptr_t imm,
TR_ExternalRelocationTargetKind relocationKind, TR::SymbolReference *sr,
TR::CodeGenerator *cg)
: TR::Instruction(op, node, cg),
_sourceImmediate(imm), _reloKind(relocationKind), _symbolReference(sr)
{
setNeedsAOTRelocation();
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] imm : immediate value
* @param[in] relocationKind : relocation kind
* @param[in] sr : symbol reference
* @param[in] precedingInstruction : preceding instruction
* @param[in] cg : CodeGenerator
*/
ARM64RelocatableImmInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, uintptr_t imm,
TR_ExternalRelocationTargetKind relocationKind, TR::SymbolReference *sr,
TR::Instruction *precedingInstruction, TR::CodeGenerator *cg)
: TR::Instruction(op, node, precedingInstruction, cg),
_sourceImmediate(imm), _reloKind(relocationKind), _symbolReference(sr)
{
setNeedsAOTRelocation();
}
/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsRelocatableImm; }
/**
* @brief Gets source immediate
* @return source immediate
*/
uintptr_t getSourceImmediate() {return _sourceImmediate;}
/**
* @brief Sets source immediate
* @param[in] si : immediate value
* @return source immediate
*/
uintptr_t setSourceImmediate(intptr_t si) {return (_sourceImmediate = si);}
/**
* @brief Encodes the immediate value into the instruction
* @param[in] instruction : instruction address
*/
void insertImmediateField(uintptr_t *instruction)
{
*instruction = _sourceImmediate;
}
/**
* @brief Sets relocation kind
* @param[in] reloKind : relocation kind
* @return relocation kind
*/
TR_ExternalRelocationTargetKind setReloKind(TR_ExternalRelocationTargetKind reloKind) { return (_reloKind = reloKind); }
/**
* @brief Gets relocation kind
* @return relocation kind
*/
TR_ExternalRelocationTargetKind getReloKind() { return _reloKind; }
/**
* @brief Sets symbol reference
* @param[in] sr : symbol reference
* @return symbol reference
*/
TR::SymbolReference *setSymbolReference(TR::SymbolReference *sr) { return (_symbolReference = sr); }
/**
* @brief Gets symbol reference
* @return symbol reference
*/
TR::SymbolReference *getSymbolReference() { return _symbolReference; }
/**
* @brief Generates binary encoding of the instruction
* @return instruction cursor
*/
virtual uint8_t *generateBinaryEncoding();
/**
* @brief Estimates binary length
* @param[in] currentEstimate : current estimated length
* @return estimated binary length
*/
virtual int32_t estimateBinaryLength(int32_t currentEstimate);
};
class ARM64ImmSymInstruction : public TR::Instruction
{
uintptr_t _addrImmediate;
TR::SymbolReference *_symbolReference;
TR::Snippet *_snippet;
public:
ARM64ImmSymInstruction(TR::InstOpCode::Mnemonic op,
TR::Node *node,
uintptr_t imm,
TR::RegisterDependencyConditions *cond,
TR::SymbolReference *sr,
TR::Snippet *s,
TR::CodeGenerator *cg)
: TR::Instruction(op, node, cond, cg),
_addrImmediate(imm), _symbolReference(sr), _snippet(s)
{
}
ARM64ImmSymInstruction(TR::InstOpCode::Mnemonic op,
TR::Node *node,
uintptr_t imm,
TR::RegisterDependencyConditions *cond,
TR::SymbolReference *sr,
TR::Snippet *s,
TR::Instruction *precedingInstruction,
TR::CodeGenerator *cg)
: TR::Instruction(op, node, cond, precedingInstruction, cg),
_addrImmediate(imm), _symbolReference(sr), _snippet(s)
{
}
/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsImmSym; }
/**
* @brief Gets address immediate
* @return address immediate
*/
uintptr_t getAddrImmediate() { return _addrImmediate; }
/**
* @brief Sets address immediate
* @param[in] imm : address immediate
* @return address immediate
*/
uintptr_t setAddrImmediate(uintptr_t imm) { return (_addrImmediate = imm); }
/**
* @brief Gets symbol reference
* @return symbol reference
*/
TR::SymbolReference *getSymbolReference() { return _symbolReference; }
/**
* @brief Sets symbol reference
* @param[in] sr : symbol reference
* @return symbol reference
*/
TR::SymbolReference *setSymbolReference(TR::SymbolReference *sr)
{
return (_symbolReference = sr);
}
/**
* @brief Gets call snippet
* @return call snippet
*/
TR::Snippet *getCallSnippet() { return _snippet;}
/**
* @brief Sets call snippet
* @param[in] s : call snippet
* @return call snippet
*/
TR::Snippet *setCallSnippet(TR::Snippet *s) { return (_snippet = s); }
virtual TR::Snippet *getSnippetForGC() {return _snippet;}
/**
* @brief Sets immediate field in binary encoding
* @param[in] instruction : instruction cursor
* @param[in] distance : branch distance
*/
void insertImmediateField(uint32_t *instruction, int32_t distance)
{
TR_ASSERT((distance & 0x3) == 0, "branch distance is not aligned");
*instruction |= ((distance >> 2) & 0x3ffffff); // imm26
}
/**
* @brief Generates binary encoding of the instruction
* @return instruction cursor
*/
virtual uint8_t *generateBinaryEncoding();
};
class ARM64LabelInstruction : public TR::Instruction
{
TR::LabelSymbol *_symbol;
public:
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sym : label symbol
* @param[in] cg : CodeGenerator
*/
ARM64LabelInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::LabelSymbol *sym, TR::CodeGenerator *cg)
: TR::Instruction(op, node, cg), _symbol(sym)
{
if (sym != NULL && op == TR::InstOpCode::label)
sym->setInstruction(this);
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sym : label symbol
* @param[in] precedingInstruction : preceding instruction
* @param[in] cg : CodeGenerator
*/
ARM64LabelInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::LabelSymbol *sym,
TR::Instruction *precedingInstruction, TR::CodeGenerator *cg)
: TR::Instruction(op, node, precedingInstruction, cg), _symbol(sym)
{
if (sym!=NULL && op==TR::InstOpCode::label)
sym->setInstruction(this);
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sym : label symbol
* @param[in] cond : register dependency condition
* @param[in] cg : CodeGenerator
*/
ARM64LabelInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::LabelSymbol *sym,
TR::RegisterDependencyConditions *cond, TR::CodeGenerator *cg)
: TR::Instruction(op, node, cond, cg), _symbol(sym)
{
if (sym!=NULL && op==TR::InstOpCode::label)
sym->setInstruction(this);
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sym : label symbol
* @param[in] cond : register dependency condition
* @param[in] precedingInstruction : preceding instruction
* @param[in] cg : CodeGenerator
*/
ARM64LabelInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::LabelSymbol *sym,
TR::RegisterDependencyConditions *cond,
TR::Instruction *precedingInstruction, TR::CodeGenerator *cg)
: TR::Instruction(op, node, cond, precedingInstruction, cg), _symbol(sym)
{
if (sym!=NULL && op==TR::InstOpCode::label)
sym->setInstruction(this);
}
/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsLabel; }
/**
* @brief Gets label symbol
* @return label symbol
*/
TR::LabelSymbol *getLabelSymbol() {return _symbol;}
/**
* @brief Sets label symbol
* @param[in] sym : label symbol
* @return label symbol
*/
TR::LabelSymbol *setLabelSymbol(TR::LabelSymbol *sym)
{
return (_symbol = sym);
}
virtual TR::Snippet *getSnippetForGC() {return getLabelSymbol()->getSnippet();}
/**
* @brief Sets immediate field in binary encoding
* @param[in] instruction : instruction cursor
* @param[in] distance : branch distance
*/
void insertImmediateField(uint32_t *instruction, int32_t distance)
{
TR_ASSERT((distance & 0x3) == 0, "branch distance is not aligned");
*instruction |= ((distance >> 2) & 0x3ffffff); // imm26
}
/**
* @brief Assigns registers
* @param[in] kindToBeAssigned : register kind
*/
virtual void assignRegisters(TR_RegisterKinds kindToBeAssigned);
/**
* @brief Generates binary encoding of the instruction
* @return instruction cursor
*/
virtual uint8_t *generateBinaryEncoding();
/**
* @brief Estimates binary length
* @param[in] currentEstimate : current estimated length
* @return estimated binary length
*/
virtual int32_t estimateBinaryLength(int32_t currentEstimate);
protected:
/**
* @brief Assigns registers for OutOfLineCodeSection
*
* @param[in] kindToBeAssigned : register kind
*/
void assignRegistersForOutOfLineCodeSection(TR_RegisterKinds kindToBeAssigned);
};
class ARM64ConditionalBranchInstruction : public ARM64LabelInstruction
{
int32_t _estimatedBinaryLocation;
TR::ARM64ConditionCode _cc;
public:
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sym : label symbol
* @param[in] cc : branch condition code
* @param[in] cg : CodeGenerator
*/
ARM64ConditionalBranchInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::LabelSymbol *sym,
TR::ARM64ConditionCode cc,
TR::CodeGenerator *cg)
: ARM64LabelInstruction(op, node, sym, cg), _cc(cc),
_estimatedBinaryLocation(0)
{
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sym : label symbol
* @param[in] cc : branch condition code
* @param[in] precedingInstruction : preceding instruction
* @param[in] cg : CodeGenerator
*/
ARM64ConditionalBranchInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::LabelSymbol *sym,
TR::ARM64ConditionCode cc,
TR::Instruction *precedingInstruction, TR::CodeGenerator *cg)
: ARM64LabelInstruction(op, node, sym, precedingInstruction, cg), _cc(cc),
_estimatedBinaryLocation(0)
{
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sym : label symbol
* @param[in] cc : branch condition code
* @param[in] cond : register dependency condition
* @param[in] cg : CodeGenerator
*/
ARM64ConditionalBranchInstruction(
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::LabelSymbol *sym,
TR::ARM64ConditionCode cc,
TR::RegisterDependencyConditions *cond, TR::CodeGenerator *cg)
: ARM64LabelInstruction(op, node, sym, cond, cg), _cc(cc),
_estimatedBinaryLocation(0)
{
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sym : label symbol
* @param[in] cc : branch condition code
* @param[in] cond : register dependency condition
* @param[in] precedingInstruction : preceding instruction
* @param[in] cg : CodeGenerator
*/
ARM64ConditionalBranchInstruction(
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::LabelSymbol *sym,
TR::ARM64ConditionCode cc,
TR::RegisterDependencyConditions *cond,
TR::Instruction *precedingInstruction, TR::CodeGenerator *cg)
: ARM64LabelInstruction(op, node, sym, cond, precedingInstruction, cg), _cc(cc),
_estimatedBinaryLocation(0)
{
}
/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsConditionalBranch; }
/**
* @brief Gets estimated binary location
* @return estimated binary location
*/
int32_t getEstimatedBinaryLocation() {return _estimatedBinaryLocation;}
/**
* @brief Sets estimated binary location
* @param[in] l : estimated binary location
* @return estimated binary location
*/
int32_t setEstimatedBinaryLocation(int32_t l) {return (_estimatedBinaryLocation = l);}
/**
* @brief Gets condition code
* @return condition code
*/
TR::ARM64ConditionCode getConditionCode() {return _cc;}
/**
* @brief Sets condition code
* @param[in] cc : condition code
* @return condition code
*/
TR::ARM64ConditionCode setConditionCode(TR::ARM64ConditionCode cc) {return (_cc = cc);}
/**
* @brief Sets immediate field in binary encoding
* @param[in] instruction : instruction cursor
* @param[in] distance : branch distance
*/
void insertImmediateField(uint32_t *instruction, int32_t distance)
{
TR_ASSERT((distance & 0x3) == 0, "branch distance is not aligned");
*instruction |= ((distance >> 2) & 0x7ffff) << 5; // imm19
}
/**
* @brief Sets condition code in binary encoding
* @param[in] instruction : instruction cursor
*/
void insertConditionCodeField(uint32_t *instruction)
{
*instruction |= (_cc & 0xf);
}
/**
* @brief Generates binary encoding of the instruction
* @return instruction cursor
*/
virtual uint8_t *generateBinaryEncoding();
/**
* @brief Estimates binary length
* @param[in] currentEstimate : current estimated length
* @return estimated binary length
*/
virtual int32_t estimateBinaryLength(int32_t currentEstimate);
};
class ARM64CompareBranchInstruction : public ARM64LabelInstruction
{
int32_t _estimatedBinaryLocation;
TR::Register *_source1Register;
public:
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sreg : source register
* @param[in] sym : label symbol
* @param[in] cg : CodeGenerator
*/
ARM64CompareBranchInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::Register *sreg, TR::LabelSymbol *sym,
TR::CodeGenerator *cg)
: ARM64LabelInstruction(op, node, sym, cg), _source1Register(sreg),
_estimatedBinaryLocation(0)
{
useRegister(sreg);
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sreg : source register
* @param[in] sym : label symbol
* @param[in] precedingInstruction : preceding instruction
* @param[in] cg : CodeGenerator
*/
ARM64CompareBranchInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::Register *sreg, TR::LabelSymbol *sym,
TR::Instruction *precedingInstruction, TR::CodeGenerator *cg)
: ARM64LabelInstruction(op, node, sym, precedingInstruction, cg), _source1Register(sreg),
_estimatedBinaryLocation(0)
{
useRegister(sreg);
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sreg : source register
* @param[in] sym : label symbol
* @param[in] cond : register dependency condition
* @param[in] cg : CodeGenerator
*/
ARM64CompareBranchInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::Register *sreg, TR::LabelSymbol *sym,
TR::RegisterDependencyConditions *cond, TR::CodeGenerator *cg)
: ARM64LabelInstruction(op, node, sym, cond, cg), _source1Register(sreg),
_estimatedBinaryLocation(0)
{
useRegister(sreg);
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] sreg : source register
* @param[in] sym : label symbol
* @param[in] cond : register dependency condition
* @param[in] precedingInstruction : preceding instruction
* @param[in] cg : CodeGenerator
*/
ARM64CompareBranchInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::Register *sreg, TR::LabelSymbol *sym,
TR::RegisterDependencyConditions *cond, TR::Instruction *precedingInstruction,
TR::CodeGenerator *cg)
: ARM64LabelInstruction(op, node, sym, cond, precedingInstruction, cg), _source1Register(sreg),
_estimatedBinaryLocation(0)
{
useRegister(sreg);
}
/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsCompareBranch; }
/**
* @brief Gets estimated binary location
* @return estimated binary location
*/
int32_t getEstimatedBinaryLocation() {return _estimatedBinaryLocation;}
/**
* @brief Sets estimated binary location
* @param[in] l : estimated binary location
* @return estimated binary location
*/
int32_t setEstimatedBinaryLocation(int32_t l) {return (_estimatedBinaryLocation = l);}
/**
* @brief Gets source register
* @return source register
*/
TR::Register *getSource1Register() {return _source1Register;}
/**
* @brief Sets source register
* @param[in] sr : source register
* @return source register
*/
TR::Register *setSource1Register(TR::Register *sr) {return (_source1Register = sr);}
/**
* @brief Sets immediate field in binary encoding
* @param[in] instruction : instruction cursor
* @param[in] distance : branch distance
*/
void insertImmediateField(uint32_t *instruction, int32_t distance)
{
TR_ASSERT((distance & 0x3) == 0, "branch distance is not aligned");
*instruction |= ((distance >> 2) & 0x7ffff) << 5;
}
/**
* @brief Sets source register in binary encoding
* @param[in] instruction : instruction cursor
*/
void insertSource1Register(uint32_t *instruction)
{
TR::RealRegister *source1 = toRealRegister(_source1Register);
source1->setRegisterFieldRD(instruction);
}
/**
* @brief Answers whether this instruction references the given virtual register
* @param[in] reg : virtual register
* @return true when the instruction references the virtual register
*/
virtual bool refsRegister(TR::Register *reg);
/**
* @brief Answers whether this instruction uses the given virtual register
* @param[in] reg : virtual register
* @return true when the instruction uses the virtual register
*/
virtual bool usesRegister(TR::Register *reg);
/**
* @brief Answers whether this instruction defines the given virtual register
* @param[in] reg : virtual register
* @return true when the instruction defines the virtual register
*/
virtual bool defsRegister(TR::Register *reg);
/**
* @brief Answers whether this instruction defines the given real register
* @param[in] reg : real register
* @return true when the instruction defines the real register
*/
virtual bool defsRealRegister(TR::Register *reg);
/**
* @brief Assigns registers
* @param[in] kindToBeAssigned : register kind
*/
virtual void assignRegisters(TR_RegisterKinds kindToBeAssigned);
/**
* @brief Generates binary encoding of the instruction
* @return instruction cursor
*/
virtual uint8_t *generateBinaryEncoding();
};
class ARM64RegBranchInstruction : public TR::Instruction
{
TR::Register *_register;
public:
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] treg : branch target
* @param[in] cg : CodeGenerator
*/
ARM64RegBranchInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::Register *treg, TR::CodeGenerator *cg)
: TR::Instruction(op, node, cg), _register(treg)
{
useRegister(treg);
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] treg : branch target
* @param[in] precedingInstruction : preceding instruction
* @param[in] cg : CodeGenerator
*/
ARM64RegBranchInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::Register *treg,
TR::Instruction *precedingInstruction, TR::CodeGenerator *cg)
: TR::Instruction(op, node, precedingInstruction, cg), _register(treg)
{
useRegister(treg);
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] treg : branch target
* @param[in] cond : register dependency condition
* @param[in] cg : CodeGenerator
*/
ARM64RegBranchInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::Register *treg,
TR::RegisterDependencyConditions *cond, TR::CodeGenerator *cg)
: TR::Instruction(op, node, cond, cg), _register(treg)
{
useRegister(treg);
}
/*
* @brief Constructor
* @param[in] op : instruction opcode
* @param[in] node : node
* @param[in] treg : branch target
* @param[in] cond : register dependency condition
* @param[in] precedingInstruction : preceding instruction
* @param[in] cg : CodeGenerator
*/
ARM64RegBranchInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::Register *treg,
TR::RegisterDependencyConditions *cond,
TR::Instruction *precedingInstruction, TR::CodeGenerator *cg)
: TR::Instruction(op, node, cond, precedingInstruction, cg), _register(treg)
{
useRegister(treg);
}
/**
* @brief Gets instruction kind
* @return instruction kind
*/
virtual Kind getKind() { return IsRegBranch; }
/**
* @brief Gets target register
* @return target register
*/
TR::Register *getTargetRegister() {return _register;}
/**
* @brief Sets target register
* @param[in] tr : target register
* @return target register
*/
TR::Register *setTargetRegister(TR::Register *tr) {return (_register = tr);}
/**
* @brief Sets target register in binary encoding
* @param[in] instruction : instruction cursor
*/
void insertTargetRegister(uint32_t *instruction)
{
TR::RealRegister *target = toRealRegister(_register);
target->setRegisterFieldRN(instruction);
}
/**
* @brief Answers whether this instruction references the given virtual register
* @param[in] reg : virtual register
* @return true when the instruction references the virtual register
*/
virtual bool refsRegister(TR::Register *reg);
/**
* @brief Answers whether this instruction uses the given virtual register
* @param[in] reg : virtual register
* @return true when the instruction uses the virtual register
*/
virtual bool usesRegister(TR::Register *reg);
/**
* @brief Answers whether this instruction defines the given virtual register
* @param[in] reg : virtual register
* @return true when the instruction defines the virtual register
*/
virtual bool defsRegister(TR::Register *reg);
/**
* @brief Answers whether this instruction defines the given real register
* @param[in] reg : real register
* @return true when the instruction defines the real register
*/
virtual bool defsRealRegister(TR::Register *reg);
/**
* @brief Assigns registers
* @param[in] kindToBeAssigned : register kind
*/
virtual void assignRegisters(TR_RegisterKinds kindToBeAssigned);
/**
* @brief Generates binary encoding of the instruction
* @return instruction cursor
*/
virtual uint8_t *generateBinaryEncoding();
};
class ARM64AdminInstruction : public TR::Instruction
{
TR::Node *_fenceNode;
public: