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OMRMachine.cpp
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OMRMachine.cpp
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/*******************************************************************************
* Copyright (c) 2018, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <stddef.h>
#include <stdint.h>
#include "codegen/ARM64Instruction.hpp"
#include "codegen/BackingStore.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/GenerateInstructions.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Machine.hpp"
#include "codegen/Machine_inlines.hpp"
#include "codegen/RealRegister.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "infra/Assert.hpp"
// Register Association
#define ARM64_REGISTER_HEAVIEST_WEIGHT 0x0000ffff
#define ARM64_REGISTER_INITIAL_PRESERVED_WEIGHT 0x00001000
#define ARM64_REGISTER_ASSOCIATED_WEIGHT 0x00000800
#define ARM64_REGISTER_PLACEHOLDER_WEIGHT 0x00000100
#define ARM64_REGISTER_BASIC_WEIGHT 0x00000080
OMR::ARM64::Machine::Machine(TR::CodeGenerator *cg) :
OMR::Machine(cg)
{
self()->initializeRegisterFile();
self()->clearRegisterAssociations();
}
// `currentInstruction` argument will be required when we implement live register analysis
TR::RealRegister *OMR::ARM64::Machine::findBestFreeRegister(TR::Instruction *currentInstruction,
TR_RegisterKinds rk,
bool considerUnlatched,
TR::Register *virtualReg)
{
uint32_t preference = (virtualReg != NULL) ? virtualReg->getAssociation() : 0;
int32_t first;
int32_t last;
switch(rk)
{
case TR_GPR:
first = TR::RealRegister::FirstGPR;
last = TR::RealRegister::LastAssignableGPR;
break;
case TR_FPR:
first = TR::RealRegister::FirstFPR;
last = TR::RealRegister::LastFPR;
break;
default:
TR_ASSERT(false, "Unsupported RegisterKind.");
}
uint32_t bestWeightSoFar = 0xffffffff;
TR::RealRegister *freeRegister = NULL;
TR::RealRegister *bestRegister = NULL;
/****************************************************************************************************************/
/* STEP 1 Register Associations */
/****************************************************************************************************************/
// Register Associations are best effort. If you really need to map a virtual to a real, use register pre/post dependency conditions.
// Check if the preferred register is free
if ((preference != 0) && (_registerFile[preference] != NULL) &&
((_registerFile[preference]->getState() == TR::RealRegister::Free) ||
(considerUnlatched && (_registerFile[preference]->getState() == TR::RealRegister::Unlatched))))
{
bestRegister = _registerFile[preference];
if (bestRegister->getState() == TR::RealRegister::Unlatched)
{
bestRegister->setAssignedRegister(NULL);
bestRegister->setState(TR::RealRegister::Free);
}
self()->cg()->traceRegisterAssignment("BEST FREE REG by pref for %R is %R", virtualReg, bestRegister);
return bestRegister;
}
/*******************************************************************************************************************/
/* STEP 2 Good 'ol linear search */
/****************************************************************************************************************/
// If no association or assoc fails, find any other free register
for (int32_t i = first; i <= last; i++)
{
if ((_registerFile[i]->getState() == TR::RealRegister::Free ||
(considerUnlatched &&
_registerFile[i]->getState() == TR::RealRegister::Unlatched)) &&
_registerFile[i]->getWeight() < bestWeightSoFar)
{
freeRegister = _registerFile[i];
bestWeightSoFar = freeRegister->getWeight();
}
}
if (freeRegister != NULL && freeRegister->getState() == TR::RealRegister::Unlatched)
{
freeRegister->setAssignedRegister(NULL);
freeRegister->setState(TR::RealRegister::Free);
}
if (freeRegister != NULL)
self()->cg()->traceRegisterAssignment("BEST FREE REG for %R is %R", virtualReg, freeRegister);
else
self()->cg()->traceRegisterAssignment("BEST FREE REG for %R is NULL (could not find one)", virtualReg);
return freeRegister;
}
TR::RealRegister *OMR::ARM64::Machine::freeBestRegister(TR::Instruction *currentInstruction,
TR::Register *virtualRegister,
TR::RealRegister *forced)
{
TR::Register *candidates[NUM_ARM64_MAXR];
TR::Compilation *comp = self()->cg()->comp();
TR::MemoryReference *tmemref;
TR_BackingStore *location;
TR::RealRegister *best;
TR::Instruction *cursor;
TR::Node *currentNode = currentInstruction->getNode();
TR_RegisterKinds rk = (virtualRegister == NULL) ? TR_GPR : virtualRegister->getKind();
int numCandidates = 0;
int first, last;
int32_t dataSize = 0;
TR::InstOpCode::Mnemonic loadOp;
if (forced != NULL)
{
best = forced;
candidates[0] = best->getAssignedRegister();
}
else
{
switch (rk)
{
case TR_GPR:
first = TR::RealRegister::FirstGPR;
last = TR::RealRegister::LastGPR;
break;
case TR_FPR:
first = TR::RealRegister::FirstFPR;
last = TR::RealRegister::LastFPR;
break;
default:
TR_ASSERT(false, "Unsupported RegisterKind.");
break;
}
for (int i = first; i <= last; i++)
{
TR::RealRegister *realReg = self()->getRealRegister((TR::RealRegister::RegNum)i);
if (realReg->getState() == TR::RealRegister::Assigned)
{
candidates[numCandidates++] = realReg->getAssignedRegister();
}
}
TR_ASSERT(numCandidates != 0, "All registers are blocked");
cursor = currentInstruction;
while (numCandidates > 1 &&
cursor != NULL &&
cursor->getOpCodeValue() != TR::InstOpCode::label &&
cursor->getOpCodeValue() != TR::InstOpCode::proc)
{
for (int i = 0; i < numCandidates; i++)
{
if (cursor->refsRegister(candidates[i]))
{
candidates[i] = candidates[--numCandidates];
}
}
cursor = cursor->getPrev();
}
best = toRealRegister(candidates[0]->getAssignedRegister());
}
TR::Register *registerToSpill = candidates[0];
TR_Debug *debugObj = self()->cg()->getDebug();
const bool containsInternalPointer = registerToSpill->containsInternalPointer();
const bool containsCollectedReference = registerToSpill->containsCollectedReference();
location = registerToSpill->getBackingStorage();
switch (rk)
{
case TR_GPR:
if (!comp->getOption(TR_DisableOOL) &&
(self()->cg()->isOutOfLineColdPath() || self()->cg()->isOutOfLineHotPath()) &&
registerToSpill->getBackingStorage())
{
// reuse the spill slot
if (debugObj)
self()->cg()->traceRegisterAssignment("\nOOL: Reuse backing store (%p) for %s inside OOL\n",
location, debugObj->getName(registerToSpill));
}
else if (!containsInternalPointer)
{
location = self()->cg()->allocateSpill(TR::Compiler->om.sizeofReferenceAddress(), registerToSpill->containsCollectedReference(), NULL);
if (debugObj)
self()->cg()->traceRegisterAssignment("\nSpilling %s to (%p)\n",debugObj->getName(registerToSpill), location);
}
else
{
location = self()->cg()->allocateInternalPointerSpill(registerToSpill->getPinningArrayPointer());
if (debugObj)
self()->cg()->traceRegisterAssignment("\nSpilling internal pointer %s to (%p)\n", debugObj->getName(registerToSpill), location);
}
break;
case TR_FPR:
if (!comp->getOption(TR_DisableOOL) &&
(self()->cg()->isOutOfLineColdPath() || self()->cg()->isOutOfLineHotPath()) &&
registerToSpill->getBackingStorage())
{
// reuse the spill slot
if (debugObj)
self()->cg()->traceRegisterAssignment("\nOOL: Reuse backing store (%p) for %s inside OOL\n",
location, debugObj->getName(registerToSpill));
}
else
{
location = self()->cg()->allocateSpill(8, false, NULL);
if (debugObj)
self()->cg()->traceRegisterAssignment("\nSpilling FPR %s to (%p)\n", debugObj->getName(registerToSpill), location);
}
break;
default:
TR_ASSERT(false, "Unsupported RegisterKind.");
break;
}
registerToSpill->setBackingStorage(location);
tmemref = new (self()->cg()->trHeapMemory()) TR::MemoryReference(currentNode, location->getSymbolReference(), self()->cg());
if (!comp->getOption(TR_DisableOOL))
{
if (!self()->cg()->isOutOfLineColdPath())
{
// the spilledRegisterList contains all registers that are spilled before entering
// the OOL cold path, post dependencies will be generated using this list
self()->cg()->getSpilledRegisterList()->push_front(registerToSpill);
// OOL cold path: depth = 3, hot path: depth = 2, main line: depth = 1
// if the spill is outside of the OOL cold/hot path, we need to protect the spill slot
// if we reverse spill this register inside the OOL cold/hot path
if (!self()->cg()->isOutOfLineHotPath())
{// main line
location->setMaxSpillDepth(1);
}
else
{
// hot path
// do not overwrite main line spill depth
if (location->getMaxSpillDepth() != 1)
{
location->setMaxSpillDepth(2);
}
}
if (debugObj)
self()->cg()->traceRegisterAssignment("OOL: adding %s to the spilledRegisterList, maxSpillDepth = %d ",
debugObj->getName(registerToSpill), location->getMaxSpillDepth());
}
else
{
// do not overwrite mainline and hot path spill depth
// if this spill is inside OOL cold path, we do not need to protecting the spill slot
// because the post condition at OOL entry does not expect this register to be spilled
if (location->getMaxSpillDepth() != 1 &&
location->getMaxSpillDepth() != 2 )
{
location->setMaxSpillDepth(3);
self()->cg()->traceRegisterAssignment("OOL: In OOL cold path, spilling %s not adding to spilledRegisterList", registerToSpill->getRegisterName(self()->cg()->comp()));
}
}
}
if (self()->cg()->comp()->getOption(TR_TraceCG))
{
diagnostic("\n\tspilling %s (%s)",
best->getAssignedRegister()->getRegisterName(self()->cg()->comp()),
best->getRegisterName(self()->cg()->comp()));
}
switch (rk)
{
case TR_GPR:
loadOp = TR::InstOpCode::ldrimmx;
break;
case TR_FPR:
loadOp = TR::InstOpCode::vldrimmd;
break;
default:
TR_ASSERT(false, "Unsupported RegisterKind.");
break;
}
generateTrg1MemInstruction(self()->cg(), loadOp, currentNode, best, tmemref, currentInstruction);
self()->cg()->traceRegFreed(registerToSpill, best);
best->setAssignedRegister(NULL);
best->setState(TR::RealRegister::Free);
registerToSpill->setAssignedRegister(NULL);
return best;
}
TR::RealRegister *OMR::ARM64::Machine::reverseSpillState(TR::Instruction *currentInstruction,
TR::Register *spilledRegister,
TR::RealRegister *targetRegister)
{
TR::Compilation *comp = self()->cg()->comp();
TR::MemoryReference *tmemref;
TR::RealRegister *sameReg;
TR_BackingStore *location = spilledRegister->getBackingStorage();
TR::Node *currentNode = currentInstruction->getNode();
TR_RegisterKinds rk = spilledRegister->getKind();
TR_Debug *debugObj = self()->cg()->getDebug();
int32_t dataSize = 0;
TR::InstOpCode::Mnemonic storeOp;
if (targetRegister == NULL)
{
targetRegister = self()->findBestFreeRegister(currentInstruction, rk, false, spilledRegister);
if (targetRegister == NULL)
{
targetRegister = self()->freeBestRegister(currentInstruction, spilledRegister, NULL);
}
targetRegister->setState(TR::RealRegister::Assigned);
}
if (self()->cg()->isOutOfLineColdPath())
{
// the future and total use count might not always reflect register spill state
// for example a new register assignment in the hot path would cause FC != TC
// in this case, assign a new register and return
if (!location)
{
if (debugObj)
self()->cg()->traceRegisterAssignment("OOL: Not generating reverse spill for (%s)\n", debugObj->getName(spilledRegister));
return targetRegister;
}
}
if (comp->getOption(TR_TraceCG))
{
diagnostic("\n\tre-assigning spilled %s to %s",
spilledRegister->getRegisterName(comp),
targetRegister->getRegisterName(comp));
}
tmemref = new (self()->cg()->trHeapMemory()) TR::MemoryReference(currentNode, location->getSymbolReference(), self()->cg());
if (comp->getOption(TR_DisableOOL))
{
switch (rk)
{
case TR_GPR:
dataSize = TR::Compiler->om.sizeofReferenceAddress();
storeOp = TR::InstOpCode::strimmx;
break;
case TR_FPR:
dataSize = 8;
storeOp = TR::InstOpCode::vstrimmd;
break;
default:
TR_ASSERT(false, "Unsupported RegisterKind.");
break;
}
self()->cg()->freeSpill(location, dataSize, 0);
generateMemSrc1Instruction(self()->cg(), storeOp, currentNode, tmemref, targetRegister, currentInstruction);
}
else
{
switch (rk)
{
case TR_GPR:
dataSize = TR::Compiler->om.sizeofReferenceAddress();
break;
case TR_FPR:
dataSize = 8;
break;
default:
TR_ASSERT(false, "Unsupported RegisterKind.");
break;
}
if (self()->cg()->isOutOfLineColdPath())
{
bool isOOLentryReverseSpill = false;
if (currentInstruction->isLabel())
{
if (((TR::ARM64LabelInstruction*)currentInstruction)->getLabelSymbol()->isStartOfColdInstructionStream())
{
// indicates that we are at OOL entry point post conditions. Since
// we are now exiting the OOL cold path (going reverse order)
// and we called reverseSpillState(), the main line path
// expects the Virt reg to be assigned to a real register
// we can now safely unlock the protected backing storage
// This prevents locking backing storage for future OOL blocks
isOOLentryReverseSpill = true;
}
}
// OOL: only free the spill slot if the register was spilled in the same or less dominant path
// ex: spilled in cold path, reverse spill in hot path or main line
// we have to spill this register again when we reach OOL entry point due to post
// conditions. We want to guarantee that the same spill slot will be protected and reused.
// maxSpillDepth: 3:cold path, 2:hot path, 1:main line
// Also free the spill if maxSpillDepth==0, which will be the case if the reverse spill also occured on the hot path.
// If the reverse spill occured on both paths then this is the last chance we have to free the spill slot.
if (location->getMaxSpillDepth() == 3 || location->getMaxSpillDepth() == 0 || isOOLentryReverseSpill)
{
if (location->getMaxSpillDepth() != 0)
location->setMaxSpillDepth(0);
else if (debugObj)
self()->cg()->traceRegisterAssignment("\nOOL: reverse spill %s in less dominant path (%d / 3), reverse spill on both paths indicated, free spill slot (%p)\n",
debugObj->getName(spilledRegister), location->getMaxSpillDepth(), location);
self()->cg()->freeSpill(location, dataSize, 0);
if (!self()->cg()->isFreeSpillListLocked())
{
spilledRegister->setBackingStorage(NULL);
}
}
else
{
if (debugObj)
self()->cg()->traceRegisterAssignment("\nOOL: reverse spill %s in less dominant path (%d / 3), protect spill slot (%p)\n",
debugObj->getName(spilledRegister), location->getMaxSpillDepth(), location);
}
}
else if (self()->cg()->isOutOfLineHotPath())
{
// the spilledRegisterList contains all registers that are spilled before entering
// the OOL path (in backwards RA). Post dependencies will be generated using this list.
// Any registers reverse spilled before entering OOL should be removed from the spilled list
if (debugObj)
self()->cg()->traceRegisterAssignment("\nOOL: removing %s from the spilledRegisterList\n", debugObj->getName(spilledRegister));
self()->cg()->getSpilledRegisterList()->remove(spilledRegister);
// Reset maxSpillDepth here so that in the cold path we know to free the spill
// and so that the spill is not included in future GC points in the hot path while it is protected
location->setMaxSpillDepth(0);
if (location->getMaxSpillDepth() == 2)
{
self()->cg()->freeSpill(location, dataSize, 0);
if (!self()->cg()->isFreeSpillListLocked())
{
spilledRegister->setBackingStorage(NULL);
}
}
else
{
if (debugObj)
self()->cg()->traceRegisterAssignment("\nOOL: reverse spilling %s in less dominant path (%d / 2), protect spill slot (%p)\n",
debugObj->getName(spilledRegister), location->getMaxSpillDepth(), location);
}
}
else // main line
{
if (debugObj)
self()->cg()->traceRegisterAssignment("\nOOL: removing %s from the spilledRegisterList)\n", debugObj->getName(spilledRegister));
self()->cg()->getSpilledRegisterList()->remove(spilledRegister);
location->setMaxSpillDepth(0);
self()->cg()->freeSpill(location, dataSize, 0);
if (!self()->cg()->isFreeSpillListLocked())
{
spilledRegister->setBackingStorage(NULL);
}
}
switch (rk)
{
case TR_GPR:
storeOp = TR::InstOpCode::strimmx;
break;
case TR_FPR:
storeOp = TR::InstOpCode::vstrimmd;
break;
default:
TR_ASSERT(false, "Unsupported RegisterKind.");
break;
}
generateMemSrc1Instruction(self()->cg(), storeOp, currentNode, tmemref, targetRegister, currentInstruction);
}
return targetRegister;
}
TR::RealRegister *OMR::ARM64::Machine::assignOneRegister(TR::Instruction *currentInstruction,
TR::Register *virtualRegister)
{
TR_RegisterKinds rk = virtualRegister->getKind();
TR::RealRegister *assignedRegister = virtualRegister->getAssignedRealRegister();
TR::CodeGenerator *cg = self()->cg();
TR::Compilation *comp = cg->comp();
if (assignedRegister == NULL)
{
cg->clearRegisterAssignmentFlags();
cg->setRegisterAssignmentFlag(TR_NormalAssignment);
if (virtualRegister->getTotalUseCount() != virtualRegister->getFutureUseCount())
{
cg->setRegisterAssignmentFlag(TR_RegisterReloaded);
assignedRegister = self()->reverseSpillState(currentInstruction, virtualRegister, NULL);
}
else
{
assignedRegister = self()->findBestFreeRegister(currentInstruction, rk, true, virtualRegister);
if (assignedRegister == NULL)
{
cg->setRegisterAssignmentFlag(TR_RegisterSpilled);
assignedRegister = self()->freeBestRegister(currentInstruction, virtualRegister, NULL);
}
if (!comp->getOption(TR_DisableOOL) && cg->isOutOfLineColdPath())
{
cg->getFirstTimeLiveOOLRegisterList()->push_front(virtualRegister);
}
}
virtualRegister->setAssignedRegister(assignedRegister);
assignedRegister->setAssignedRegister(virtualRegister);
assignedRegister->setState(TR::RealRegister::Assigned);
cg->traceRegAssigned(virtualRegister, assignedRegister);
}
else
{
TR_Debug *debugObj = cg->getDebug();
auto registerName = (debugObj != NULL) ? debugObj->getName(assignedRegister) : "NULL";
TR_ASSERT_FATAL(assignedRegister->getAssignedRegister(), "assignedRegister(%s) does not have assigned virtual register", registerName);
}
// Do bookkeeping register use count
decFutureUseCountAndUnlatch(currentInstruction, virtualRegister);
return assignedRegister;
}
/* generate instruction for register copy */
static void registerCopy(TR::Instruction *precedingInstruction,
TR_RegisterKinds rk,
TR::RealRegister *targetReg,
TR::RealRegister *sourceReg,
TR::CodeGenerator *cg)
{
TR::Node *node = precedingInstruction->getNode();
TR::RealRegister *zeroReg;
switch (rk)
{
case TR_GPR:
zeroReg = cg->machine()->getRealRegister(TR::RealRegister::xzr);
generateTrg1Src2Instruction(cg, TR::InstOpCode::orrx, node, targetReg, zeroReg, sourceReg, precedingInstruction); /* mov (register) */
break;
case TR_FPR:
generateTrg1Src1Instruction(cg, TR::InstOpCode::fmovd, node, targetReg, sourceReg, precedingInstruction);
break;
default:
TR_ASSERT(false, "Unsupported RegisterKind.");
break;
}
}
/* generate instructions for register exchange */
static void registerExchange(TR::Instruction *precedingInstruction,
TR_RegisterKinds rk,
TR::RealRegister *targetReg,
TR::RealRegister *sourceReg,
TR::RealRegister *middleReg,
TR::CodeGenerator *cg)
{
// middleReg is not used if rk==TR_GPR.
TR::Node *node = precedingInstruction->getNode();
if (rk == TR_GPR)
{
generateTrg1Src2Instruction(cg, TR::InstOpCode::eorx, node, targetReg, targetReg, sourceReg, precedingInstruction);
generateTrg1Src2Instruction(cg, TR::InstOpCode::eorx, node, sourceReg, targetReg, sourceReg, precedingInstruction);
generateTrg1Src2Instruction(cg, TR::InstOpCode::eorx, node, targetReg, targetReg, sourceReg, precedingInstruction);
}
else
{
registerCopy(precedingInstruction, rk, targetReg, middleReg, cg);
registerCopy(precedingInstruction, rk, sourceReg, targetReg, cg);
registerCopy(precedingInstruction, rk, middleReg, sourceReg, cg);
}
}
void OMR::ARM64::Machine::coerceRegisterAssignment(TR::Instruction *currentInstruction,
TR::Register *virtualRegister,
TR::RealRegister::RegNum registerNumber)
{
TR::Compilation *comp = self()->cg()->comp();
TR::RealRegister *targetRegister = _registerFile[registerNumber];
TR::RealRegister *realReg = virtualRegister->getAssignedRealRegister();
TR::RealRegister *currentAssignedRegister = realReg ? toRealRegister(realReg) : NULL;
TR_RegisterKinds rk = virtualRegister->getKind();
if (comp->getOption(TR_TraceCG))
{
if (currentAssignedRegister)
diagnostic("\n\tcoercing %s from %s to %s",
virtualRegister->getRegisterName(comp),
currentAssignedRegister->getRegisterName(comp),
targetRegister->getRegisterName(comp));
else
diagnostic("\n\tcoercing %s to %s",
virtualRegister->getRegisterName(comp),
targetRegister->getRegisterName(comp));
}
if (currentAssignedRegister == targetRegister)
return;
if ( targetRegister->getState() == TR::RealRegister::Free
|| targetRegister->getState() == TR::RealRegister::Unlatched)
{
#ifdef DEBUG
if (comp->getOption(TR_TraceCG))
diagnostic(", which is free");
#endif
if (currentAssignedRegister == NULL)
{
if (virtualRegister->getTotalUseCount() != virtualRegister->getFutureUseCount())
{
self()->cg()->setRegisterAssignmentFlag(TR_RegisterReloaded);
self()->reverseSpillState(currentInstruction, virtualRegister, targetRegister);
}
else
{
if (!comp->getOption(TR_DisableOOL) && self()->cg()->isOutOfLineColdPath())
{
self()->cg()->getFirstTimeLiveOOLRegisterList()->push_front(virtualRegister);
}
}
}
else
{
registerCopy(currentInstruction, rk, currentAssignedRegister, targetRegister, self()->cg());
currentAssignedRegister->setState(TR::RealRegister::Free);
currentAssignedRegister->setAssignedRegister(NULL);
}
}
else
{
TR::RealRegister *spareReg = NULL;
TR::Register *currentTargetVirtual = targetRegister->getAssignedRegister();
bool needTemp = (rk == TR_FPR); // xor is unavailable for register exchange
if (targetRegister->getState() == TR::RealRegister::Blocked)
{
#ifdef DEBUG
if (comp->getOption(TR_TraceCG))
diagnostic(", which is blocked and assigned to %s",
currentTargetVirtual->getRegisterName(comp));
#endif
if (!currentAssignedRegister || needTemp)
{
spareReg = self()->findBestFreeRegister(currentInstruction, rk, false, currentTargetVirtual);
self()->cg()->setRegisterAssignmentFlag(TR_IndirectCoercion);
if (spareReg == NULL)
{
self()->cg()->setRegisterAssignmentFlag(TR_RegisterSpilled);
virtualRegister->block();
spareReg = self()->freeBestRegister(currentInstruction, currentTargetVirtual);
virtualRegister->unblock();
}
}
if (currentAssignedRegister)
{
self()->cg()->traceRegAssigned(currentTargetVirtual, currentAssignedRegister);
registerExchange(currentInstruction, rk, targetRegister, currentAssignedRegister, spareReg, self()->cg());
currentAssignedRegister->setState(TR::RealRegister::Blocked);
currentAssignedRegister->setAssignedRegister(currentTargetVirtual);
currentTargetVirtual->setAssignedRegister(currentAssignedRegister);
// For Non-GPR, spareReg remains FREE.
}
else
{
self()->cg()->traceRegAssigned(currentTargetVirtual, spareReg);
registerCopy(currentInstruction, rk, targetRegister, spareReg, self()->cg());
spareReg->setState(TR::RealRegister::Blocked);
currentTargetVirtual->setAssignedRegister(spareReg);
spareReg->setAssignedRegister(currentTargetVirtual);
// spareReg is assigned.
if (virtualRegister->getTotalUseCount() != virtualRegister->getFutureUseCount())
{
self()->cg()->setRegisterAssignmentFlag(TR_RegisterReloaded);
self()->reverseSpillState(currentInstruction, virtualRegister, targetRegister);
}
else
{
if (!comp->getOption(TR_DisableOOL) && self()->cg()->isOutOfLineColdPath())
{
self()->cg()->getFirstTimeLiveOOLRegisterList()->push_front(virtualRegister);
}
}
}
}
else if (targetRegister->getState() == TR::RealRegister::Assigned)
{
#ifdef DEBUG
if (comp->getOption(TR_TraceCG))
diagnostic(", which is assigned to %s",
currentTargetVirtual->getRegisterName(comp));
#endif
if (!currentAssignedRegister || needTemp)
spareReg = self()->findBestFreeRegister(currentInstruction, rk, false, currentTargetVirtual);
self()->cg()->setRegisterAssignmentFlag(TR_IndirectCoercion);
if (currentAssignedRegister)
{
if (!needTemp || (spareReg != NULL))
{
self()->cg()->traceRegAssigned(currentTargetVirtual, currentAssignedRegister);
registerExchange(currentInstruction, rk, targetRegister,
currentAssignedRegister, spareReg, self()->cg());
currentAssignedRegister->setState(TR::RealRegister::Assigned);
currentAssignedRegister->setAssignedRegister(currentTargetVirtual);
currentTargetVirtual->setAssignedRegister(currentAssignedRegister);
// spareReg is still FREE.
}
else
{
self()->freeBestRegister(currentInstruction, currentTargetVirtual, targetRegister);
self()->cg()->traceRegAssigned(currentTargetVirtual, currentAssignedRegister);
self()->cg()->setRegisterAssignmentFlag(TR_RegisterSpilled);
registerCopy(currentInstruction, rk, currentAssignedRegister, targetRegister, self()->cg());
currentAssignedRegister->setState(TR::RealRegister::Free);
currentAssignedRegister->setAssignedRegister(NULL);
}
}
else
{
if (spareReg == NULL)
{
self()->cg()->setRegisterAssignmentFlag(TR_RegisterSpilled);
self()->freeBestRegister(currentInstruction, currentTargetVirtual, targetRegister);
}
else
{
self()->cg()->traceRegAssigned(currentTargetVirtual, spareReg);
registerCopy(currentInstruction, rk, targetRegister, spareReg, self()->cg());
spareReg->setState(TR::RealRegister::Assigned);
spareReg->setAssignedRegister(currentTargetVirtual);
currentTargetVirtual->setAssignedRegister(spareReg);
// spareReg is assigned.
}
if (virtualRegister->getTotalUseCount() != virtualRegister->getFutureUseCount())
{
self()->cg()->setRegisterAssignmentFlag(TR_RegisterReloaded);
self()->reverseSpillState(currentInstruction, virtualRegister, targetRegister);
}
else
{
if (!comp->getOption(TR_DisableOOL) && self()->cg()->isOutOfLineColdPath())
{
self()->cg()->getFirstTimeLiveOOLRegisterList()->push_front(virtualRegister);
}
}
}
self()->cg()->resetRegisterAssignmentFlag(TR_IndirectCoercion);
}
else
{
#ifdef DEBUG
if (comp->getOption(TR_TraceCG))
diagnostic(", which is in an unknown state %d", targetRegister->getState());
#endif
}
}
targetRegister->setState(TR::RealRegister::Assigned);
targetRegister->setAssignedRegister(virtualRegister);
virtualRegister->setAssignedRegister(targetRegister);
self()->cg()->traceRegAssigned(virtualRegister, targetRegister);
}
void OMR::ARM64::Machine::initializeRegisterFile()
{
_registerFile[TR::RealRegister::NoReg] = NULL;
_registerFile[TR::RealRegister::SpilledReg] = NULL;
_registerFile[TR::RealRegister::x0] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x0,
self()->cg());
_registerFile[TR::RealRegister::x1] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x1,
self()->cg());
_registerFile[TR::RealRegister::x2] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x2,
self()->cg());
_registerFile[TR::RealRegister::x3] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x3,
self()->cg());
_registerFile[TR::RealRegister::x4] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x4,
self()->cg());
_registerFile[TR::RealRegister::x5] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x5,
self()->cg());
_registerFile[TR::RealRegister::x6] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x6,
self()->cg());
_registerFile[TR::RealRegister::x7] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x7,
self()->cg());
_registerFile[TR::RealRegister::x8] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x8,
self()->cg());
_registerFile[TR::RealRegister::x9] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x9,
self()->cg());
_registerFile[TR::RealRegister::x10] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x10,
self()->cg());
_registerFile[TR::RealRegister::x11] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x11,
self()->cg());
_registerFile[TR::RealRegister::x12] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x12,
self()->cg());
_registerFile[TR::RealRegister::x13] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x13,
self()->cg());
_registerFile[TR::RealRegister::x14] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x14,
self()->cg());
_registerFile[TR::RealRegister::x15] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x15,
self()->cg());
_registerFile[TR::RealRegister::x16] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x16,
self()->cg());
_registerFile[TR::RealRegister::x17] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x17,
self()->cg());
_registerFile[TR::RealRegister::x18] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x18,
self()->cg());
_registerFile[TR::RealRegister::x19] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x19,
self()->cg());
_registerFile[TR::RealRegister::x20] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x20,
self()->cg());
_registerFile[TR::RealRegister::x21] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x21,
self()->cg());
_registerFile[TR::RealRegister::x22] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x22,
self()->cg());
_registerFile[TR::RealRegister::x23] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x23,
self()->cg());
_registerFile[TR::RealRegister::x24] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x24,
self()->cg());
_registerFile[TR::RealRegister::x25] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x25,
self()->cg());
_registerFile[TR::RealRegister::x26] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x26,
self()->cg());
_registerFile[TR::RealRegister::x27] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x27,
self()->cg());
_registerFile[TR::RealRegister::x28] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x28,
self()->cg());
_registerFile[TR::RealRegister::x29] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::x29,
self()->cg());
/* x30 is used as LR on ARM64 */
_registerFile[TR::RealRegister::lr] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::lr,
self()->cg());
/* SP */
_registerFile[TR::RealRegister::sp] = new (self()->cg()->trHeapMemory()) TR::RealRegister(TR_GPR,
0,
TR::RealRegister::Free,
TR::RealRegister::sp,
self()->cg());