-
Notifications
You must be signed in to change notification settings - Fork 392
/
OMRMachine.cpp
2062 lines (1829 loc) · 97.2 KB
/
OMRMachine.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include "p/codegen/OMRMachine.hpp"
#include <stdint.h>
#include <string.h>
#include <algorithm>
#include "codegen/BackingStore.hpp"
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/Machine_inlines.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "compile/Compilation.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/ObjectModel.hpp"
#include "env/Processors.hpp"
#include "env/TRMemory.hpp"
#include "il/Block.hpp"
#include "il/ILOpCodes.hpp"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "infra/Assert.hpp"
#include "infra/BitVector.hpp"
#include "infra/List.hpp"
#include "p/codegen/GenerateInstructions.hpp"
#include "p/codegen/PPCCRBackingStore.hpp"
#include "p/codegen/PPCInstruction.hpp"
#include "p/codegen/PPCOpsDefines.hpp"
#include "ras/Debug.hpp"
#include "env/IO.hpp"
namespace TR { class AutomaticSymbol; }
static void registerExchange(TR::Instruction *precedingI,
TR_RegisterKinds rk,
TR::RealRegister *tReg,
TR::RealRegister *sReg,
TR::RealRegister *mReg,
TR::CodeGenerator *cg);
static void registerCopy(TR::Instruction *precedingI,
TR_RegisterKinds rk,
TR::RealRegister *tReg,
TR::RealRegister *sReg,
TR::CodeGenerator *cg);
static int32_t spillSizeForRegister(TR::Register *virtReg)
{
switch (virtReg->getKind())
{
case TR_GPR:
return TR::Compiler->om.sizeofReferenceAddress();
case TR_FPR:
return virtReg->isSinglePrecision() ? 4 : 8;
case TR_VSX_SCALAR:
return 8;
case TR_CCR:
return 4;
case TR_VSX_VECTOR:
case TR_VRF:
return 16;
}
TR_ASSERT(false, "Unexpected register kind");
return 0;
}
static const char *
getRegisterName(TR::Register * reg, TR::CodeGenerator * cg)
{
return (reg? cg->getDebug()->getName(reg) : "NULL");
}
static bool boundNext(TR::Instruction *currentInstruction, int32_t realNum, TR::Register *virtReg, bool isOOL)
{
TR::Instruction *cursor = currentInstruction;
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)realNum;
TR::Node *nodeBBStart = NULL;
while (!(isOOL && cursor == NULL) && cursor->getOpCodeValue() != TR::InstOpCode::proc)
{
TR::RegisterDependencyConditions *conditions;
if ((conditions = cursor->getDependencyConditions()) != NULL)
{
TR::Register *boundReg = conditions->searchPostConditionRegister(realReg);
if (boundReg == NULL)
boundReg = conditions->searchPreConditionRegister(realReg);
if (boundReg != NULL)
{
if (boundReg == virtReg)
return true;
return false;
}
}
TR::Node *node = cursor->getNode();
if (nodeBBStart!=NULL && node!=nodeBBStart)
return true;
if (node!=NULL && node->getOpCodeValue()==TR::BBStart)
{
TR::Block *block = node->getBlock();
if (!block->isExtensionOfPreviousBlock())
nodeBBStart = node;
}
cursor = cursor->getPrev();
}
return true;
}
OMR::Power::Machine::Machine(TR::CodeGenerator *cg) :
OMR::Machine(cg)
{
self()->initializeRegisterFile();
memset( _registerAssociations, 0, sizeof(TR::Register*)*TR::RealRegister::NumRegisters );
}
void OMR::Power::Machine::initREGAssociations()
{
// Track the last 4 real GPRs assigned so that we try not to reuse them.
_4thLastGPRAssigned = -1;
_3rdLastGPRAssigned = -1;
_2ndLastGPRAssigned = -1;
_lastGPRAssigned = -1;
int icount;
int nextV = 0;
int lastFPRv, lastVRFv;
const TR::PPCLinkageProperties &linkage = self()->cg()->getProperties();
// We assume the volatile/preserved registers to be consecutive
// because the private linkage will either be a single volatile set or
// end up resembling the system linkage. In both cases all volatiles are together,
// and so are the preserved registers
// pick the volatiles from traditional BFPs
for (icount=TR::RealRegister::FirstFPR; icount<=TR::RealRegister::LastFPR; icount++)
{
if (!linkage.getPreserved((TR::RealRegister::RegNum)icount))
_registerAllocationFPR[nextV++] = icount;
}
lastFPRv = nextV - 1;
// Then, pick the preserves from traditional BFPs
for (icount=TR::RealRegister::LastFPR; icount>=TR::RealRegister::FirstFPR; icount--)
{
if (linkage.getPreserved((TR::RealRegister::RegNum)icount))
_registerAllocationFPR[nextV++] = icount;
}
_lastPreservedFPRAvail = nextV - 1;
// pick all the volatiles from VRF
for (icount=TR::RealRegister::LastFPR+1; icount<=TR::RealRegister::LastVSR; icount++)
{
if (!linkage.getPreserved((TR::RealRegister::RegNum)icount))
_registerAllocationFPR[nextV++] = icount;
}
lastVRFv = nextV - 1;
// Now VRF the preserves
for (icount=TR::RealRegister::LastVSR; icount>=TR::RealRegister::LastFPR+1; icount--)
{
if (linkage.getPreserved((TR::RealRegister::RegNum)icount))
_registerAllocationFPR[nextV++] = icount;
}
_lastPreservedVRFAvail = nextV - 1;
// Power6: roll over the biggest set of registers we can afford, because no renaming
// Power8/SAR: confine to the smallest set of registers we can get away, because map cache
// Others: neutral --- take Power6 way for now
int rollingAllocator = !(self()->cg()->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P8));
_inUseFPREnd = rollingAllocator?lastFPRv:0;
_lastFPRAlloc = _inUseFPREnd;
_inUseVFREnd = rollingAllocator?lastVRFv:(_lastPreservedFPRAvail + 1);
_lastVRFAlloc = _inUseVFREnd;
}
TR::RealRegister *OMR::Power::Machine::findBestFreeRegister(TR::Instruction *currentInstruction,
TR_RegisterKinds rk,
bool excludeGPR0,
bool considerUnlatched,
TR::Register *virtualReg)
{
uint32_t preference = (virtualReg==NULL)?0:virtualReg->getAssociation();
uint64_t interference = 0;
int first, maskI;
int last;
bool liveRegOn = (self()->cg()->getLiveRegisters(rk) != NULL);
if (liveRegOn && virtualReg != NULL)
interference = virtualReg->getInterference();
// After liveReg is used by default, the following code should go away
bool avoidGPR0 = (virtualReg!=NULL ?
virtualReg->containsCollectedReference() || virtualReg->containsInternalPointer() :
false );
if (!liveRegOn && avoidGPR0)
interference |= 1;
switch(rk)
{
case TR_GPR:
maskI = first = TR::RealRegister::FirstGPR;
if (excludeGPR0)
first++;
last = TR::RealRegister::LastGPR;
break;
case TR_FPR:
case TR_VSX_SCALAR:
case TR_VSX_VECTOR:
maskI = TR::RealRegister::FirstFPR;
break;
case TR_CCR:
maskI = first = TR::RealRegister::FirstCCR;
last = TR::RealRegister::LastCCR;
break;
case TR_VRF:
maskI = TR::RealRegister::FirstVRF;
break;
}
if (liveRegOn && preference!=0 && (interference & (1<<(preference-maskI))))
{
if (!boundNext(currentInstruction, preference, virtualReg, (self()->cg()->isOutOfLineColdPath() || self()->cg()->isOutOfLineHotPath())))
preference = 0;
}
if (preference!=0 && (!excludeGPR0 || preference!=TR::RealRegister::gr0) &&
(_registerFile[preference]->getState() == TR::RealRegister::Free ||
(considerUnlatched &&_registerFile[preference]->getState() == TR::RealRegister::Unlatched)))
{
if (_registerFile[preference]->getState() == TR::RealRegister::Unlatched)
{
_registerFile[preference]->setAssignedRegister(NULL);
_registerFile[preference]->setState(TR::RealRegister::Free);
}
return _registerFile[preference];
}
uint32_t bestWeightSoFar = 0xffffffff;
TR::RealRegister *freeRegister = NULL;
uint64_t iOld=0, iNew;
// For FPR/VSR/VRF
if (rk == TR_FPR || rk == TR_VSX_SCALAR || rk == TR_VSX_VECTOR || rk == TR_VRF)
{
int rollingAllocator = !(self()->cg()->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P8));
// Find the best in the used FPR set so far
int i, idx;
if (rk != TR_VRF)
{
i = _lastFPRAlloc;
do {
if (++i > _inUseFPREnd) i = 0;
iNew = interference & (1<<(_registerAllocationFPR[i]-maskI));
if ( ( _registerFile[_registerAllocationFPR[i]]->getState() == TR::RealRegister::Free ||
(considerUnlatched && _registerFile[_registerAllocationFPR[i]]->getState() == TR::RealRegister::Unlatched))
&&
( freeRegister == NULL ||
(iOld && !iNew) ||
((iOld || !iNew) && !rollingAllocator && // Rolling: weight is not considered once used
_registerFile[_registerAllocationFPR[i]]->getWeight()<bestWeightSoFar)
)
)
{
iOld = iNew;
idx = i;
freeRegister = _registerFile[_registerAllocationFPR[i]];
bestWeightSoFar = freeRegister->getWeight();
}
} while (i != _lastFPRAlloc);
if (freeRegister != NULL)
_lastFPRAlloc = idx;
}
// Find the best in the used VRF set so far
if (freeRegister==NULL && rk!=TR_FPR)
{
i = _lastVRFAlloc;
do {
if (++i > _inUseVFREnd) i = _lastPreservedFPRAvail+1; // first VRF
iNew = interference & (1<<(_registerAllocationFPR[i]-maskI));
if ( ( _registerFile[_registerAllocationFPR[i]]->getState() == TR::RealRegister::Free ||
(considerUnlatched && _registerFile[_registerAllocationFPR[i]]->getState() == TR::RealRegister::Unlatched))
&&
( freeRegister == NULL ||
(iOld && !iNew) ||
((iOld || !iNew) && !rollingAllocator && // Rolling: weight is not considered once used
_registerFile[_registerAllocationFPR[i]]->getWeight()<bestWeightSoFar)
)
)
{
iOld = iNew;
idx = i;
freeRegister = _registerFile[_registerAllocationFPR[i]];
bestWeightSoFar = freeRegister->getWeight();
}
} while (i != _lastVRFAlloc);
if (freeRegister != NULL)
_lastVRFAlloc = idx;
}
// If no register was assigned, try the not-used-so-far register set.
// Remember they are already in increasing weight in _registerAllocationFPR
if (freeRegister==NULL && rk!=TR_VRF)
{
for (i = _inUseFPREnd+1; i<=_lastPreservedFPRAvail; i++)
{
iNew = interference & (1<<(_registerAllocationFPR[i]-maskI));
if ( (_registerFile[_registerAllocationFPR[i]]->getState() == TR::RealRegister::Free ||
(considerUnlatched && _registerFile[_registerAllocationFPR[i]]->getState() == TR::RealRegister::Unlatched))
&&
( freeRegister == NULL || !iNew )
)
{
freeRegister = _registerFile[_registerAllocationFPR[i]];
idx = i;
if (!iNew)
break;
}
}
if (freeRegister != NULL) // We have assigned an unused reg, add it to the used set
_inUseFPREnd = _lastFPRAlloc = idx;
}
if (freeRegister==NULL && rk!=TR_FPR)
{
for (i = _inUseVFREnd+1; i<=_lastPreservedVRFAvail; i++)
{
iNew = interference & (1<<(_registerAllocationFPR[i]-maskI));
if ( (_registerFile[_registerAllocationFPR[i]]->getState() == TR::RealRegister::Free ||
(considerUnlatched && _registerFile[_registerAllocationFPR[i]]->getState() == TR::RealRegister::Unlatched))
&&
( freeRegister == NULL || !iNew )
)
{
freeRegister = _registerFile[_registerAllocationFPR[i]];
idx = i;
if (!iNew)
break;
}
}
if (freeRegister != NULL) // We have assigned an unused reg, add it to the used set
_inUseVFREnd = _lastVRFAlloc = idx;
}
}
else
{
int iChosen;
for (int i = first; i <= last; i++)
{
int currentReg = 1<<(i-maskI);
iNew = interference & currentReg;
//Inject interference for last four assignments to prevent write-after-write dependancy in same p6 dispatch group.
if(rk == TR_GPR && (self()->cg()->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6)))
{
if (_lastGPRAssigned != -1)
iNew |= currentReg & _lastGPRAssigned;
if (_2ndLastGPRAssigned != -1)
iNew |= currentReg & _2ndLastGPRAssigned;
if (_3rdLastGPRAssigned != -1)
iNew |= currentReg & _3rdLastGPRAssigned;
if (_4thLastGPRAssigned != -1)
iNew |= currentReg & _4thLastGPRAssigned;
}
if ( ( _registerFile[i]->getState() == TR::RealRegister::Free ||
(considerUnlatched && _registerFile[i]->getState() == TR::RealRegister::Unlatched))
&& ( freeRegister == NULL ||
(iOld && !iNew) ||
((iOld || !iNew) && _registerFile[i]->getWeight()<bestWeightSoFar))
)
{
iOld = iNew;
freeRegister = _registerFile[i];
iChosen = i;
bestWeightSoFar = freeRegister->getWeight();
}
}
//Track the last four registers used for use in above interference injection.
if ((rk == TR_GPR) && (freeRegister != NULL) && (self()->cg()->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6)))
{
_4thLastGPRAssigned = _3rdLastGPRAssigned;
_3rdLastGPRAssigned = _2ndLastGPRAssigned;
_2ndLastGPRAssigned = _lastGPRAssigned;
_lastGPRAssigned = 1<<(iChosen-maskI);
}
}
if (freeRegister!=NULL && freeRegister->getState()==TR::RealRegister::Unlatched)
{
freeRegister->setAssignedRegister(NULL);
freeRegister->setState(TR::RealRegister::Free);
}
return freeRegister;
}
TR::RealRegister *OMR::Power::Machine::freeBestRegister(TR::Instruction *currentInstruction,
TR::Register *virtReg,
TR::RealRegister *forced,
bool excludeGPR0)
{
TR::Register *candidates[NUM_PPC_MAXR];
TR::MemoryReference *tmemref;
TR_BackingStore *location;
TR::RealRegister *best, *crtemp=NULL;
TR::Instruction *cursor;
TR::InstOpCode::Mnemonic opCode;
TR::Machine *machine = self()->cg()->machine();
TR::Node *currentNode = currentInstruction->getNode();
TR_RegisterKinds rk = (virtReg==NULL)?TR_GPR:virtReg->getKind();
int32_t numCandidates=0, first, last, maskI;
uint64_t interference=0;
TR::RealRegister::RegState crtemp_state;
TR::Compilation *comp = self()->cg()->comp();
if (forced != NULL)
{
best = forced;
candidates[0] = best->getAssignedRegister();
}
else
{
switch (rk)
{
case TR_GPR:
maskI = first = TR::RealRegister::FirstGPR;
if (excludeGPR0)
first++;
last = TR::RealRegister::LastGPR;
break;
case TR_FPR:
maskI = first = TR::RealRegister::FirstFPR;
last = TR::RealRegister::LastFPR;
break;
case TR_VSX_SCALAR:
maskI = first = TR::RealRegister::FirstFPR;
last = TR::RealRegister::LastVSR;
break;
case TR_VSX_VECTOR:
maskI = first = TR::RealRegister::FirstFPR;
last = TR::RealRegister::LastVSR;
break;
case TR_CCR:
maskI = first = TR::RealRegister::FirstCCR;
last = TR::RealRegister::LastCCR;
break;
case TR_VRF:
maskI = first = TR::RealRegister::FirstVRF;
last = TR::RealRegister::LastVRF;
break;
}
int32_t preference = 0, pref_favored = 0;
if (self()->cg()->getLiveRegisters(rk) != NULL && virtReg != NULL)
{
interference = virtReg->getInterference();
preference = virtReg->getAssociation();
// Consider yielding
if (preference != 0 && boundNext(currentInstruction, preference, virtReg, (self()->cg()->isOutOfLineColdPath() || self()->cg()->isOutOfLineHotPath())))
{
pref_favored = 1;
interference &= ~((uint64_t)(1<<(preference - maskI)));
}
}
uint64_t allInterfere;
for (int i = first; i <= last; i++)
{
uint64_t iInterfere = interference & (1<<(i-maskI));
TR::RealRegister *realReg = machine->getRealRegister((TR::RealRegister::RegNum)i);
if (realReg->getState() == TR::RealRegister::Assigned)
{
TR::Register *associatedVirtual = realReg->getAssignedRegister();
if (numCandidates == 0)
{
candidates[numCandidates++] = associatedVirtual;
allInterfere = iInterfere;
}
else
{
if (iInterfere)
{
if (allInterfere)
candidates[numCandidates++] = associatedVirtual;
}
else
{
if (allInterfere)
{
numCandidates = allInterfere = 0;
candidates[0] = associatedVirtual;
}
else
{
if (i==preference && pref_favored)
{
TR::Register *tempReg = candidates[0];
candidates[0] = associatedVirtual;
associatedVirtual = tempReg;
}
candidates[numCandidates] = associatedVirtual;
}
numCandidates++;
}
}
}
}
TR_ASSERT(numCandidates !=0, "All %s registers are blocked\n", virtReg->getRegisterKindName(comp, rk));
cursor = currentInstruction;
while (numCandidates > 1 &&
cursor != NULL &&
cursor->getOpCodeValue() != TR::InstOpCode::label &&
cursor->getOpCodeValue() != TR::InstOpCode::proc)
{
for (int i = 0; i < numCandidates; i++)
{
if (cursor->refsRegister(candidates[i]))
{
candidates[i] = candidates[--numCandidates];
}
}
cursor = cursor->getPrev();
}
best = toRealRegister(candidates[0]->getAssignedRegister());
}
switch (rk)
{
// XXX: Reusing backing stores here is causing the virtual being spilled to be clobbered
case TR_GPR:
if (false /*!cg()->comp()->getOption(TR_DisableOOL) && (cg()->isOutOfLineColdPath() || cg()->isOutOfLineHotPath()) &&
virtReg->getBackingStorage()*/)
{
location = virtReg->getBackingStorage();
// reuse the spill slot
if (self()->cg()->getDebug())
self()->cg()->traceRegisterAssignment("\nOOL: Reuse backing store (%p) for %s inside OOL\n",
location, self()->cg()->getDebug()->getName(virtReg));
}
else
{
if (candidates[0]->getBackingStorage())
{
// If there is backing storage associated with a register, it means the
// backing store wasn't returned to the free list and it can be used.
//
location = candidates[0]->getBackingStorage();
// If best register already has a backing store it's because we reverse spilled it in an
// OOL region while the free spill list was locked and we didn't clean this up after unlocking
// the list (see TODO in PPCInstruction.cpp). Therefore we need to set the
// occupied flag for this reuse.
if (location->getSymbolReference()->getSymbol()->getSize() > TR::Compiler->om.sizeofReferenceAddress())
location->setFirstHalfIsOccupied();
else
location->setIsOccupied();
}
else
{
if (candidates[0]->containsInternalPointer())
{
TR::AutomaticSymbol *parray = candidates[0]->getPinningArrayPointer();
location = self()->cg()->allocateInternalPointerSpill(parray);
}
else
{
location = self()->cg()->allocateSpill(TR::Compiler->om.sizeofReferenceAddress(), candidates[0]->containsCollectedReference(), NULL);
}
}
}
break;
case TR_FPR:
if (false /*!cg()->comp()->getOption(TR_DisableOOL) && (cg()->isOutOfLineColdPath() || cg()->isOutOfLineHotPath()) &&
virtReg->getBackingStorage()*/)
{
location = virtReg->getBackingStorage();
// reuse the spill slot
if (self()->cg()->getDebug())
self()->cg()->traceRegisterAssignment("\nOOL: Reuse backing store (%p) for %s inside OOL\n",
location, self()->cg()->getDebug()->getName(virtReg));
}
else
{
if (candidates[0]->getBackingStorage())
{
// If there is backing storage associated with a register, it means the
// backing store wasn't returned to the free list and it can be used.
//
location = candidates[0]->getBackingStorage();
// If best register already has a backing store it's because we reverse spilled it in an
// OOL region while the free spill list was locked and we didn't clean this up after unlocking
// the list (see TODO in PPCInstruction.cpp). Therefore we need to set the
// occupied flag for this reuse.
if (candidates[0]->isSinglePrecision() && location->getSymbolReference()->getSymbol()->getSize() > 4)
location->setFirstHalfIsOccupied();
else
location->setIsOccupied();
}
else
{
location = self()->cg()->allocateSpill(candidates[0]->isSinglePrecision()? 4:8, false, NULL);
}
}
break;
case TR_VSX_SCALAR:
if (candidates[0]->getBackingStorage())
{
// If there is backing storage associated with a register, it means the
// backing store wasn't returned to the free list and it can be used.
//
location = candidates[0]->getBackingStorage();
// If best register already has a backing store it's because we reverse spilled it in an
// OOL region while the free spill list was locked and we didn't clean this up after unlocking
// the list (see TODO in PPCInstruction.cpp). Therefore we need to set the
// occupied flag for this reuse.
if (candidates[0]->isSinglePrecision() && location->getSymbolReference()->getSymbol()->getSize() > 4)
location->setFirstHalfIsOccupied();
else
location->setIsOccupied();
}
else
{
location = self()->cg()->allocateSpill(candidates[0]->isSinglePrecision()? 4:8, false, NULL);
}
break;
case TR_CCR:
if (false /*!cg()->comp()->getOption(TR_DisableOOL) && (cg()->isOutOfLineColdPath() || cg()->isOutOfLineHotPath()) &&
virtReg->getBackingStorage()*/)
{
location = virtReg->getBackingStorage();
// reuse the spill slot
if (self()->cg()->getDebug())
self()->cg()->traceRegisterAssignment("\nOOL: Reuse backing store (%p) for %s inside OOL\n",
location, self()->cg()->getDebug()->getName(virtReg));
}
else
{
if (candidates[0]->getBackingStorage())
{
// If there is backing storage associated with a register, it means the
// backing store wasn't returned to the free list and it can be used.
//
location = candidates[0]->getBackingStorage();
// If best register already has a backing store it's because we reverse spilled it in an
// OOL region while the free spill list was locked and we didn't clean this up after unlocking
// the list (see TODO in PPCInstruction.cpp). Therefore we need to set the
// occupied flag for this reuse.
if (location->getSymbolReference()->getSymbol()->getSize() > 4)
location->setFirstHalfIsOccupied();
else
location->setIsOccupied();
}
else
{
location = new (self()->cg()->trHeapMemory()) TR_PPCCRBackingStore(comp, self()->cg()->allocateSpill(4, false, NULL)); // TODO: Could this be 1 byte?
}
}
break;
case TR_VSX_VECTOR:
case TR_VRF:
if (candidates[0]->getBackingStorage())
{
// If there is backing storage associated with a register, it means the
// backing store wasn't returned to the free list and it can be used.
//
location = candidates[0]->getBackingStorage();
// If best register already has a backing store it's because we reverse spilled it in an
// OOL region while the free spill list was locked and we didn't clean this up after unlocking
// the list (see TODO in PPCInstruction.cpp). Therefore we need to set the
// occupied flag for this reuse.
location->setIsOccupied();
}
else
{
location = self()->cg()->allocateSpill(16, false, NULL);
}
break;
}
if (rk == TR_CCR)
toPPCCRBackingStore(location)->setCcrFieldIndex(
best->getRegisterNumber() - TR::RealRegister::FirstCCR);
candidates[0]->setBackingStorage(location);
tmemref = TR::MemoryReference::createWithSymRef(self()->cg(), currentNode, location->getSymbolReference(), TR::Compiler->om.sizeofReferenceAddress());
if (rk == TR_CCR)
{
crtemp = self()->findBestFreeRegister(currentInstruction, TR_GPR);
if (crtemp == NULL)
crtemp = self()->freeBestRegister(currentInstruction, NULL);
else
crtemp->setHasBeenAssignedInMethod(true);
crtemp_state = crtemp->getState();
TR::Instruction *ccrInstr = generateSrc1Instruction(self()->cg(), TR::InstOpCode::mtocrf, currentNode, crtemp, 1<<(7-toPPCCRBackingStore(location)->getCcrFieldIndex()), currentInstruction);
self()->cg()->traceRAInstruction(ccrInstr);
}
if (!comp->getOption(TR_DisableOOL))
{
if (!self()->cg()->isOutOfLineColdPath())
{
TR_Debug *debugObj = self()->cg()->getDebug();
// the spilledRegisterList contains all registers that are spilled before entering
// the OOL cold path, post dependencies will be generated using this list
self()->cg()->getSpilledRegisterList()->push_front(candidates[0]);
// OOL cold path: depth = 3, hot path: depth =2, main line: depth = 1
// if the spill is outside of the OOL cold/hot path, we need to protect the spill slot
// if we reverse spill this register inside the OOL cold/hot path
if (!self()->cg()->isOutOfLineHotPath())
{// main line
location->setMaxSpillDepth(1);
}
else
{
// hot path
// do not overwrite main line spill depth
if (location->getMaxSpillDepth() != 1)
location->setMaxSpillDepth(2);
}
if (debugObj)
self()->cg()->traceRegisterAssignment("OOL: adding %s to the spilledRegisterList, maxSpillDepth = %d\n",
debugObj->getName(candidates[0]), location->getMaxSpillDepth());
}
else
{
// do not overwrite mainline and hot path spill depth
// if this spill is inside OOL cold path, we do not need to protecting the spill slot
// because the post condition at OOL entry does not expect this register to be spilled
if (location->getMaxSpillDepth() != 1 &&
location->getMaxSpillDepth() != 2 )
location->setMaxSpillDepth(3);
}
}
TR::Instruction *reloadInstr = NULL;
TR::RealRegister *tempIndexRegister = NULL;
switch (rk)
{
case TR_GPR:
reloadInstr = generateTrg1MemInstruction(self()->cg(),TR::InstOpCode::Op_load, currentNode, best, tmemref, currentInstruction);
break;
case TR_FPR:
if (candidates[0]->isSinglePrecision())
{
opCode = TR::InstOpCode::lfs;
tmemref->setLength(4);
}
else
{
opCode = TR::InstOpCode::lfd;
tmemref->setLength(8);
}
reloadInstr = generateTrg1MemInstruction(self()->cg(), opCode, currentNode, best, tmemref, currentInstruction);
break;
case TR_VSX_SCALAR:
tempIndexRegister = self()->findBestFreeRegister(currentInstruction, TR_GPR);
if (tempIndexRegister == NULL)
tempIndexRegister = self()->freeBestRegister(currentInstruction, NULL);
tmemref->setUsingDelayedIndexedForm();
tmemref->setIndexRegister(tempIndexRegister);
tmemref->setIndexModifiable();
opCode = TR::InstOpCode::lxsdx;
tmemref->setLength(8);
reloadInstr = generateTrg1MemInstruction(self()->cg(), opCode, currentNode, best, tmemref, currentInstruction);
self()->cg()->stopUsingRegister(tempIndexRegister);
break;
case TR_CCR:
reloadInstr = generateTrg1MemInstruction(self()->cg(),TR::InstOpCode::Op_load, currentNode, crtemp, tmemref, currentInstruction);
break;
case TR_VSX_VECTOR:
tempIndexRegister = self()->findBestFreeRegister(currentInstruction, TR_GPR);
if (tempIndexRegister == NULL)
tempIndexRegister = self()->freeBestRegister(currentInstruction, NULL);
tmemref->setUsingDelayedIndexedForm();
tmemref->setIndexRegister(tempIndexRegister);
tmemref->setIndexModifiable();
opCode = TR::InstOpCode::lxvd2x;
tmemref->setLength(16);
reloadInstr = generateTrg1MemInstruction(self()->cg(), opCode, currentNode, best, tmemref, currentInstruction);
self()->cg()->stopUsingRegister(tempIndexRegister);
break;
case TR_VRF:
// Until stack frame is 16-byte aligned, we cannot use VMX load/store here
// So, we use VSX load/store instead as a work-around
TR_ASSERT(self()->cg()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX), "VSX support not enabled");
tempIndexRegister = self()->findBestFreeRegister(currentInstruction, TR_GPR);
if (tempIndexRegister == NULL)
tempIndexRegister = self()->freeBestRegister(currentInstruction, NULL);
tmemref->setUsingDelayedIndexedForm();
tmemref->setIndexRegister(tempIndexRegister);
tmemref->setIndexModifiable();
opCode = TR::InstOpCode::lxvd2x;
tmemref->setLength(16);
reloadInstr = generateTrg1MemInstruction(self()->cg(), opCode, currentNode, best, tmemref, currentInstruction);
self()->cg()->stopUsingRegister(tempIndexRegister);
break;
}
self()->cg()->traceRegFreed(candidates[0], best);
self()->cg()->traceRAInstruction(reloadInstr);
best->setAssignedRegister(NULL);
best->setState(TR::RealRegister::Free);
candidates[0]->setAssignedRegister(NULL);
return best;
}
// Sets the register association of a real register to a virtual register
// Used to track the old real register association
TR::Register *OMR::Power::Machine::setVirtualAssociatedWithReal(TR::RealRegister::RegNum regNum, TR::Register * virtReg)
{
if (virtReg)
{
// disable previous association
if (virtReg->getAssociation())
_registerAssociations[virtReg->getAssociation()] = 0;
virtReg->setAssociation(regNum);
}
return (_registerAssociations[regNum] = virtReg);
}
TR::Register *OMR::Power::Machine::getVirtualAssociatedWithReal(TR::RealRegister::RegNum regNum)
{
return(_registerAssociations[regNum]);
}
TR::RealRegister *OMR::Power::Machine::reverseSpillState(TR::Instruction *currentInstruction,
TR::Register *spilledRegister,
TR::RealRegister *targetRegister,
bool excludeGPR0)
{
TR::MemoryReference *tmemref;
TR::Compilation *comp = self()->cg()->comp();
TR::RealRegister *sameReg, *crtemp = NULL;
TR_BackingStore *location = spilledRegister->getBackingStorage();
TR::Node *currentNode = currentInstruction->getNode();
TR_RegisterKinds rk = spilledRegister->getKind();
TR::InstOpCode::Mnemonic opCode;
TR_Debug *debugObj = self()->cg()->getDebug();
if (targetRegister == NULL)
{
if ((rk == TR_CCR) && (!self()->cg()->isOutOfLineColdPath() && !self()->cg()->isOutOfLineHotPath()) && ((sameReg=self()->cg()->machine()->getRealRegister((TR::RealRegister::RegNum)(TR::RealRegister::FirstCCR+toPPCCRBackingStore(location)->getCcrFieldIndex())))->getState() == TR::RealRegister::Free))
{
targetRegister = sameReg;
}
else
{
targetRegister = self()->findBestFreeRegister(currentInstruction, rk, excludeGPR0, false, spilledRegister);
}
if (targetRegister == NULL)
{
targetRegister = self()->freeBestRegister(currentInstruction,
spilledRegister, NULL, excludeGPR0);
}
targetRegister->setState(TR::RealRegister::Assigned);
}
if (self()->cg()->isOutOfLineColdPath())
{
// the future and total use count might not always reflect register spill state
// for example a new register assignment in the hot path would cause FC != TC
// in this case, assign a new register and return
if (!location)
{
if (debugObj)
self()->cg()->traceRegisterAssignment("OOL: Not generating reverse spill for (%s)\n", debugObj->getName(spilledRegister));
return targetRegister;
}
}
if (rk == TR_CCR)
{
crtemp = self()->findBestFreeRegister(currentInstruction, TR_GPR);
if (crtemp == NULL)
crtemp = self()->freeBestRegister(currentInstruction, NULL);
else
crtemp->setHasBeenAssignedInMethod(true);
}
tmemref = TR::MemoryReference::createWithSymRef(self()->cg(), currentNode, location->getSymbolReference(), TR::Compiler->om.sizeofReferenceAddress());
TR::Instruction *spillInstr = NULL;
int32_t dataSize = spillSizeForRegister(spilledRegister);
if (comp->getOption(TR_DisableOOL))
{
self()->cg()->freeSpill(location, dataSize, 0);
}
else
{
if (self()->cg()->isOutOfLineColdPath())
{
bool isOOLentryReverseSpill = false;
if (currentInstruction->isLabel())
{
if (((TR::PPCLabelInstruction*)currentInstruction)->getLabelSymbol()->isStartOfColdInstructionStream())
{
// indicates that we are at OOL entry point post conditions. Since
// we are now exiting the OOL cold path (going reverse order)
// and we called reverseSpillState(), the main line path
// expects the Virt reg to be assigned to a real register
// we can now safely unlock the protected backing storage
// This prevents locking backing storage for future OOL blocks
isOOLentryReverseSpill = true;
}
}
// OOL: only free the spill slot if the register was spilled in the same or less dominant path
// ex: spilled in cold path, reverse spill in hot path or main line
// we have to spill this register again when we reach OOL entry point due to post
// conditions. We want to guarantee that the same spill slot will be protected and reused.
// maxSpillDepth: 3:cold path, 2:hot path, 1:main line
// Also free the spill if maxSpillDepth==0, which will be the case if the reverse spill also occured on the hot path.
// If the reverse spill occured on both paths then this is the last chance we have to free the spill slot.
if (location->getMaxSpillDepth() == 3 || location->getMaxSpillDepth() == 0 || isOOLentryReverseSpill)
{
if (location->getMaxSpillDepth() != 0)
location->setMaxSpillDepth(0);
else if (debugObj)
self()->cg()->traceRegisterAssignment("\nOOL: reverse spill %s in less dominant path (%d / 3), reverse spill on both paths indicated, free spill slot (%p)\n",
debugObj->getName(spilledRegister), location->getMaxSpillDepth(), location);
self()->cg()->freeSpill(location, dataSize, 0);
if (!self()->cg()->isFreeSpillListLocked())
{
spilledRegister->setBackingStorage(NULL);
}
}
else
{
if (debugObj)
self()->cg()->traceRegisterAssignment("\nOOL: reverse spill %s in less dominant path (%d / 3), protect spill slot (%p)\n",
debugObj->getName(spilledRegister), location->getMaxSpillDepth(), location);
}
}
else if (self()->cg()->isOutOfLineHotPath())
{
// the spilledRegisterList contains all registers that are spilled before entering
// the OOL path (in backwards RA). Post dependencies will be generated using this list.
// Any registers reverse spilled before entering OOL should be removed from the spilled list
if (debugObj)
self()->cg()->traceRegisterAssignment("\nOOL: removing %s from the spilledRegisterList\n", debugObj->getName(spilledRegister));
self()->cg()->getSpilledRegisterList()->remove(spilledRegister);