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OMRX86Instruction.cpp
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OMRX86Instruction.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include "codegen/X86Instruction.hpp"
#include <stddef.h>
#include <stdint.h>
#include "codegen/CodeGenerator.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/RegisterRematerializationInfo.hpp"
#include "codegen/Relocation.hpp"
#include "codegen/Snippet.hpp"
#include "codegen/UnresolvedDataSnippet.hpp"
#include "compile/Compilation.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/Block.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/List.hpp"
#include "ras/Debug.hpp"
#include "runtime/Runtime.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "x/codegen/GuardedDevirtualSnippet.hpp"
#endif
#include "x/codegen/OutlinedInstructions.hpp"
#include "codegen/InstOpCode.hpp"
#include "x/codegen/X86Register.hpp"
class TR_VirtualGuardSite;
// Hack markers
//
// TODO: Implement these more systematically
//
#define BACKWARD_BRANCH_BOUNDARY_SPACING (16) // K8 opt guide section 6.1; no indication that this helps on Intel
#define BACKWARD_BRANCH_MAX_PADDING (5)
// Assign an 8-bit register to a virtual register.
//
TR::RealRegister *assign8BitGPRegister(TR::Instruction *instr,
TR::Register *virtReg,
TR::CodeGenerator *cg)
{
TR::Machine *machine = cg->machine();
TR::RealRegister *assignedRegister = virtReg->getAssignedRealRegister();
TR::RealRegister *candidate = toRealRegister(assignedRegister);
cg->clearRegisterAssignmentFlags();
cg->setRegisterAssignmentFlag(TR_NormalAssignment);
if (candidate->getRegisterNumber() > TR::RealRegister::Last8BitGPR)
{
if ((candidate = machine->findBestFreeGPRegister(instr, virtReg, TR_ByteReg)) == NULL)
{
cg->setRegisterAssignmentFlag(TR_RegisterSpilled);
candidate = machine->freeBestGPRegister(instr, virtReg, TR_ByteReg);
}
machine->coerceGPRegisterAssignment(instr, virtReg, candidate->getRegisterNumber());
assignedRegister = candidate;
}
virtReg->setAssignedAsByteRegister(true);
return assignedRegister;
}
// Assign any GP (including XMM) register to a virtual register.
//
TR::RealRegister *assignGPRegister(TR::Instruction *instr,
TR::Register *virtReg,
TR_RegisterSizes requestedRegSize,
TR::CodeGenerator *cg)
{
TR::Machine *machine = cg->machine();
TR::RealRegister *assignedRegister;
cg->clearRegisterAssignmentFlags();
cg->setRegisterAssignmentFlag(TR_NormalAssignment);
// Depending on direction of assignment, must get register back from
// spilled state
//
if (virtReg->getTotalUseCount() != virtReg->getFutureUseCount())
{
cg->setRegisterAssignmentFlag(TR_RegisterReloaded);
assignedRegister = machine->reverseGPRSpillState(instr, virtReg, NULL, requestedRegSize);
}
// If first use, totaluse and futureuse will be the same
//
else
{
if ((assignedRegister = machine->findBestFreeGPRegister(instr, virtReg, requestedRegSize, true)))
{
if (cg->enableBetterSpillPlacements())
cg->removeBetterSpillPlacementCandidate(assignedRegister);
}
else
{
cg->setRegisterAssignmentFlag(TR_RegisterSpilled);
assignedRegister = machine->freeBestGPRegister(instr, virtReg, requestedRegSize);
}
}
virtReg->setAssignedRegister(assignedRegister);
virtReg->setAssignedAsByteRegister(requestedRegSize == TR_ByteReg);
assignedRegister->setAssignedRegister(virtReg);
assignedRegister->setState(TR::RealRegister::Assigned, virtReg->isPlaceholderReg());
cg->traceRegAssigned(virtReg, assignedRegister);
return assignedRegister;
}
////////////////////////////////////////////////////////////////////////////////
// TR::X86LabelInstruction:: member functions
////////////////////////////////////////////////////////////////////////////////
void TR::X86LabelInstruction::initialize(TR::LabelSymbol* sym, bool b)
{
_symbol = sym;
_needToClearFPStack = b;
_outlinedInstructionBranch = NULL;
_reloType = TR_NoRelocation;
_permitShortening = true;
if (sym && self()->getOpCodeValue() == TR::InstOpCode::label)
sym->setInstruction(this);
else if (sym)
sym->setDirectlyTargeted();
}
TR::X86LabelInstruction::X86LabelInstruction(TR::InstOpCode::Mnemonic op,
TR::Node* node,
TR::LabelSymbol* sym,
TR::CodeGenerator* cg,
bool b)
: TR::Instruction(node, op, cg)
{
initialize(sym, b);
}
TR::X86LabelInstruction::X86LabelInstruction(TR::Instruction* precedingInstruction,
TR::InstOpCode::Mnemonic op,
TR::LabelSymbol* sym,
TR::CodeGenerator* cg,
bool b)
: TR::Instruction(op, precedingInstruction, cg)
{
initialize(sym, b);
}
TR::X86LabelInstruction::X86LabelInstruction(TR::InstOpCode::Mnemonic op,
TR::Node* node,
TR::LabelSymbol* sym,
TR::RegisterDependencyConditions* cond,
TR::CodeGenerator* cg,
bool b)
: TR::Instruction(cond, node, op, cg)
{
initialize(sym, b);
}
TR::X86LabelInstruction::X86LabelInstruction(TR::Instruction* precedingInstruction,
TR::InstOpCode::Mnemonic op,
TR::LabelSymbol* sym,
TR::RegisterDependencyConditions* cond,
TR::CodeGenerator* cg,
bool b)
: TR::Instruction(cond, op, precedingInstruction, cg)
{
initialize(sym, b);
}
TR::X86LabelInstruction *TR::X86LabelInstruction::getX86LabelInstruction()
{
return this;
}
TR::Snippet *TR::X86LabelInstruction::getSnippetForGC()
{
return getLabelSymbol() ? getLabelSymbol()->getSnippet() : NULL;
}
void TR::X86LabelInstruction::assignOutlinedInstructions(
TR_RegisterKinds kindsToBeAssigned,
TR::X86LabelInstruction *labelInstruction)
{
// Switch to the outlined instruction stream and assign registers.
//
TR_OutlinedInstructions *oi = cg()->findOutlinedInstructionsFromLabel(labelInstruction->getLabelSymbol());
TR_ASSERT(oi, "Could not find OutlinedInstructions stream from label. instr=%p, label=%p\n", labelInstruction, labelInstruction->getLabelSymbol());
if (!oi->hasBeenRegisterAssigned())
oi->assignRegisters(kindsToBeAssigned, generateVFPSaveInstruction(getPrev(), cg()));
}
// Take the now-assigned register dependencies from this instruction and replicate
// them on the outlined instruction branch instruction.
//
void TR::X86LabelInstruction::addPostDepsToOutlinedInstructionsBranch()
{
TR::RegisterDependencyConditions *mergeDeps = getDependencyConditions()->clone(cg());
TR_ASSERT(!_outlinedInstructionBranch->getDependencyConditions(), "not expecting existing reg deps on an OOL branch");
_outlinedInstructionBranch->setDependencyConditions(mergeDeps);
TR::RegisterDependencyGroup *depGroup = mergeDeps->getPostConditions();
for (auto i = 0U; i < mergeDeps->getNumPostConditions(); i++)
{
// Bump the use count on all cloned dependencies.
//
TR::RegisterDependency *dependency = depGroup->getRegisterDependency(i);
TR::Register *virtReg = dependency->getRegister();
virtReg->incTotalUseCount();
virtReg->incFutureUseCount();
#ifdef DEBUG
// Ensure all register dependencies have been assigned.
//
TR_ASSERT(!dependency->isNoReg(), "unassigned merge dep register");
#endif
}
}
void TR::X86LabelInstruction::assignRegisters(TR_RegisterKinds kindsToBeAssigned)
{
TR::Compilation *comp = cg()->comp();
if (getNeedToClearFPStack())
{
cg()->machine()->popEntireStack();
}
if (kindsToBeAssigned & TR_GPR_Mask)
{
if (getDependencyConditions())
{
// ----------------------
// Assign post conditions
// ----------------------
//
getDependencyConditions()->assignPostConditionRegisters(this, kindsToBeAssigned, cg());
if (getOpCodeValue() == TR::InstOpCode::label && getLabelSymbol()->isInternalControlFlowMerge())
{
// This is the merge label of a non-linear internal control flow region.
// Record the register assigner state before continuing on the main path.
//
cg()->prepareForNonLinearRegisterAssignmentAtMerge(this);
}
else if (getOpCodeValue() != TR::InstOpCode::label && getLabelSymbol()->isStartOfColdInstructionStream())
{
if (getLabelSymbol()->isNonLinear() && cg()->getUseNonLinearRegisterAssigner())
{
// This is a branch to an outlined instruction sequence. Now perform
// register assignment over it.
//
cg()->performNonLinearRegisterAssignmentAtBranch(this, kindsToBeAssigned);
}
else
{
// Classic out-of-line instruction register assignment
//
assignOutlinedInstructions(kindsToBeAssigned, this);
}
}
else if (_outlinedInstructionBranch)
{
// OBSOLETE???
addPostDepsToOutlinedInstructionsBranch();
assignOutlinedInstructions(kindsToBeAssigned, _outlinedInstructionBranch);
}
// ---------------------
// Assign pre conditions
// ---------------------
//
getDependencyConditions()->assignPreConditionRegisters(this, kindsToBeAssigned, cg());
}
else if (getOpCodeValue() != TR::InstOpCode::label && getLabelSymbol()->isStartOfColdInstructionStream())
{
if (getLabelSymbol()->isNonLinear() && cg()->getUseNonLinearRegisterAssigner())
{
// This is a branch to an outlined instruction sequence. Now perform
// register assignment over it.
//
cg()->performNonLinearRegisterAssignmentAtBranch(this, kindsToBeAssigned);
}
else
{
// Classic out-of-line instruction register assignment
//
assignOutlinedInstructions(kindsToBeAssigned, this);
}
}
else if (getOpCodeValue() == TR::InstOpCode::label && getLabelSymbol()->isInternalControlFlowMerge())
{
// This is the merge label of a non-linear internal control flow region.
// Record the register assigner state before continuing on the main path.
//
cg()->prepareForNonLinearRegisterAssignmentAtMerge(this);
}
else if (getLabelSymbol())
{
#ifdef J9_PROJECT_SPECIFIC
TR::Snippet *snippet = getLabelSymbol()->getSnippet();
TR::X86GuardedDevirtualSnippet *devirtSnippet;
// If this is a GuardedDevirtualSnippet, then must find out what real register
// contains the class object reference. This must be used by the snippet to generate
// the full virtual call sequence.
//
if (snippet && (devirtSnippet = snippet->getGuardedDevirtualSnippet()))
{
TR::Register *classObjectRegister = devirtSnippet->getClassObjectRegister();
if (classObjectRegister != NULL && !classObjectRegister->getRealRegister())
{
TR::RealRegister *assignedClassObjectRegister = toRealRegister(classObjectRegister->getAssignedRealRegister());
if (assignedClassObjectRegister == NULL &&
classObjectRegister->getTotalUseCount() == classObjectRegister->getFutureUseCount())
{
TR::Machine *machine = cg()->machine();
cg()->clearRegisterAssignmentFlags();
cg()->setRegisterAssignmentFlag(TR_NormalAssignment);
if ((assignedClassObjectRegister = machine->findBestFreeGPRegister(this, classObjectRegister, TR_WordReg)) != NULL)
{
machine->coerceGPRegisterAssignment(this, classObjectRegister, assignedClassObjectRegister->getRegisterNumber());
// No use of this register here in the original stream. So, need to
// bump its total use count without bumping its future use count
// so that it doesn't look like the first time a register is seen. That is
// make it fail the getTotalUseCount() == getFutureUseCount() test used
// to detect the first reference to a register in the assignment direction
//
classObjectRegister->incTotalUseCount();
}
}
if (assignedClassObjectRegister)
{
devirtSnippet->setClassObjectRegister(assignedClassObjectRegister);
}
}
}
#endif
}
// Save better spill placement information at conditional branch
// instructions, and enable or disable better spill placement when
// entering or leaving a region of internal control flow.
//
if (getOpCode().isConditionalBranchOp() && cg()->internalControlFlowNestingDepth() == 0)
{
if (cg()->enableBetterSpillPlacements())
cg()->saveBetterSpillPlacements(this);
}
}
else
{
if (getDependencyConditions())
{
// should only get here for X87 assignment, which is a forward pass
TR_ASSERT(cg()->getAssignmentDirection() != cg()->Backward, "Assigning non-GPR registers in a forward pass");
getDependencyConditions()->assignPreConditionRegisters(this->getPrev(), kindsToBeAssigned, cg());
getDependencyConditions()->assignPostConditionRegisters(this, kindsToBeAssigned, cg());
}
}
}
////////////////////////////////////////////////////////////////////////////////
// TR::X86FenceInstruction:: member functions
////////////////////////////////////////////////////////////////////////////////
TR::X86FenceInstruction::X86FenceInstruction(TR::InstOpCode::Mnemonic op, TR::Node *node, TR::Node * fenceNode, TR::CodeGenerator *cg)
: TR::Instruction(node, op, cg), _fenceNode(fenceNode)
{
}
TR::X86FenceInstruction::X86FenceInstruction(TR::Instruction *precedingInstruction,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::CodeGenerator *cg)
: TR::Instruction(op, precedingInstruction, cg), _fenceNode(node)
{
}
////////////////////////////////////////////////////////////////////////////////
// TR::X86ImmInstruction:: member functions
////////////////////////////////////////////////////////////////////////////////
TR::X86ImmInstruction::X86ImmInstruction(TR::InstOpCode::Mnemonic op,
TR::Node * node,
int32_t imm,
TR::CodeGenerator *cg,
int32_t reloKind)
: TR::Instruction(node, op, cg), _sourceImmediate(imm),
_adjustsFramePointerBy(0),
_reloKind(reloKind)
{
}
TR::X86ImmInstruction::X86ImmInstruction(TR::Instruction *precedingInstruction,
TR::InstOpCode::Mnemonic op,
int32_t imm,
TR::CodeGenerator *cg,
int32_t reloKind)
: TR::Instruction(op, precedingInstruction, cg), _sourceImmediate(imm),
_adjustsFramePointerBy(0),
_reloKind(reloKind)
{
}
TR::X86ImmInstruction::X86ImmInstruction(TR::InstOpCode::Mnemonic op,
TR::Node *node,
int32_t imm,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg,
int32_t reloKind)
: TR::Instruction(cond, node, op, cg), _sourceImmediate(imm),
_adjustsFramePointerBy(0),
_reloKind(reloKind)
{
}
TR::X86ImmInstruction::X86ImmInstruction(TR::Instruction *precedingInstruction,
TR::InstOpCode::Mnemonic op,
int32_t imm,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg,
int32_t reloKind)
: TR::Instruction(cond, op, precedingInstruction, cg), _sourceImmediate(imm),
_adjustsFramePointerBy(0),
_reloKind(reloKind)
{
if (cond && cg->enableRegisterAssociations())
cond->createRegisterAssociationDirective(this, cg);
}
#if defined(DEBUG) || defined(PROD_WITH_ASSUMES)
// The following safe virtual downcast method is only used in an assertion
// check within "toIA32ImmInstruction"
//
TR::X86ImmInstruction *TR::X86ImmInstruction::getX86ImmInstruction()
{
return this;
}
#endif
////////////////////////////////////////////////////////////////////////////////
// TR::X86ImmSnippetInstruction:: member functions
////////////////////////////////////////////////////////////////////////////////
TR::X86ImmSnippetInstruction::X86ImmSnippetInstruction(TR::InstOpCode::Mnemonic op,
TR::Node *node,
int32_t imm,
TR::UnresolvedDataSnippet *us,
TR::CodeGenerator *cg)
: TR::X86ImmInstruction(imm, node, op, cg), _unresolvedSnippet(us)
{
}
TR::X86ImmSnippetInstruction::X86ImmSnippetInstruction(TR::Instruction *precedingInstruction,
TR::InstOpCode::Mnemonic op,
int32_t imm,
TR::UnresolvedDataSnippet *us,
TR::CodeGenerator *cg)
: TR::X86ImmInstruction(imm, op, precedingInstruction, cg), _unresolvedSnippet(us)
{
}
TR::Snippet *TR::X86ImmSnippetInstruction::getSnippetForGC()
{
return getUnresolvedSnippet();
}
////////////////////////////////////////////////////////////////////////////////
// TR::X86ImmSymInstruction:: member functions
////////////////////////////////////////////////////////////////////////////////
TR::X86ImmSymInstruction::X86ImmSymInstruction(TR::InstOpCode::Mnemonic op,
TR::Node *node,
int32_t imm,
TR::SymbolReference *sr,
TR::CodeGenerator *cg)
: TR::X86ImmInstruction(imm, node, op, cg),
_symbolReference(sr)
{
}
TR::X86ImmSymInstruction::X86ImmSymInstruction(TR::Instruction *precedingInstruction,
TR::InstOpCode::Mnemonic op,
int32_t imm,
TR::SymbolReference *sr,
TR::CodeGenerator *cg)
: TR::X86ImmInstruction(imm, op, precedingInstruction, cg),
_symbolReference(sr)
{
}
TR::X86ImmSymInstruction::X86ImmSymInstruction(TR::InstOpCode::Mnemonic op,
TR::Node *node,
int32_t imm,
TR::SymbolReference *sr,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg)
: TR::X86ImmInstruction(cond, imm, node, op, cg),
_symbolReference(sr)
{
}
TR::X86ImmSymInstruction::X86ImmSymInstruction(TR::Instruction *precedingInstruction,
TR::InstOpCode::Mnemonic op,
int32_t imm,
TR::SymbolReference *sr,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg)
: TR::X86ImmInstruction(cond, imm, op, precedingInstruction, cg),
_symbolReference(sr)
{
}
////////////////////////////////////////////////////////////////////////////////
// TR::X86RegInstruction:: member functions
////////////////////////////////////////////////////////////////////////////////
TR::X86RegInstruction::X86RegInstruction(TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *reg,
TR::CodeGenerator *cg)
: TR::Instruction(node, op, cg), _targetRegister(reg)
{
useRegister(reg);
getOpCode().trackUpperBitsOnReg(reg, cg);
// Check the live discardable register list to see if this is the first
// instruction that kills the rematerialisable range of a register.
//
if (cg->enableRematerialisation() &&
reg->isDiscardable() &&
getOpCode().modifiesTarget())
{
TR::ClobberingInstruction *clob = new (cg->trHeapMemory()) TR::ClobberingInstruction(this, cg->trMemory());
clob->addClobberedRegister(reg);
cg->addClobberingInstruction(clob);
cg->removeLiveDiscardableRegister(reg);
cg->clobberLiveDependentDiscardableRegisters(clob, reg);
if (debug("dumpRemat"))
{
diagnostic("---> Clobbering %s discardable register %s at instruction %p\n",
cg->getDebug()->toString(reg->getRematerializationInfo()), cg->getDebug()->getName(reg), this);
}
}
}
TR::X86RegInstruction::X86RegInstruction(TR::Instruction *precedingInstruction,
TR::InstOpCode::Mnemonic op,
TR::Register *reg,
TR::CodeGenerator *cg)
: TR::Instruction(op, precedingInstruction, cg), _targetRegister(reg)
{
useRegister(reg);
getOpCode().trackUpperBitsOnReg(reg, cg);
}
TR::X86RegInstruction::X86RegInstruction(TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *reg,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg)
: TR::Instruction(cond, node, op, cg), _targetRegister(reg)
{
useRegister(reg);
getOpCode().trackUpperBitsOnReg(reg, cg);
// Check the live discardable register list to see if this is the first
// instruction that kills the rematerialisable range of a register.
//
if (cg->enableRematerialisation() &&
reg->isDiscardable() &&
getOpCode().modifiesTarget())
{
TR::ClobberingInstruction *clob = new (cg->trHeapMemory()) TR::ClobberingInstruction(this, cg->trMemory());
clob->addClobberedRegister(reg);
cg->addClobberingInstruction(clob);
cg->removeLiveDiscardableRegister(reg);
cg->clobberLiveDependentDiscardableRegisters(clob, reg);
if (debug("dumpRemat"))
{
diagnostic("---> Clobbering %s discardable register %s at instruction %p\n",
cg->getDebug()->toString(reg->getRematerializationInfo()), cg->getDebug()->getName(reg), this);
}
}
}
TR::X86RegInstruction::X86RegInstruction(TR::Instruction *precedingInstruction,
TR::InstOpCode::Mnemonic op,
TR::Register *reg,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg)
: TR::Instruction(cond, op, precedingInstruction, cg), _targetRegister(reg)
{
useRegister(reg);
getOpCode().trackUpperBitsOnReg(reg, cg);
}
TR::X86RegInstruction *TR::X86RegInstruction::getX86RegInstruction()
{
return this;
}
bool TR::X86RegInstruction::refsRegister(TR::Register *reg)
{
if (reg == getTargetRegister())
{
return true;
}
else if (getDependencyConditions())
{
return getDependencyConditions()->refsRegister(reg);
}
return false;
}
bool TR::X86RegInstruction::defsRegister(TR::Register *reg)
{
if (reg == getTargetRegister() && getOpCode().modifiesTarget())
{
return true;
}
else if (getDependencyConditions())
{
return getDependencyConditions()->defsRegister(reg);
}
return false;
}
bool TR::X86RegInstruction::usesRegister(TR::Register *reg)
{
if (reg == getTargetRegister())
{
return true;
}
else if (getDependencyConditions())
{
return getDependencyConditions()->usesRegister(reg);
}
return false;
}
void TR::X86RegInstruction::assignRegisters(TR_RegisterKinds kindsToBeAssigned)
{
if (getDependencyConditions())
{
getTargetRegister()->block();
if ((cg()->getAssignmentDirection() == cg()->Backward))
{
getDependencyConditions()->assignPostConditionRegisters(this, kindsToBeAssigned, cg());
}
else
{
getDependencyConditions()->assignPreConditionRegisters(this->getPrev(), kindsToBeAssigned, cg());
}
getTargetRegister()->unblock();
}
if (kindsToBeAssigned & getTargetRegister()->getKindAsMask())
{
TR::RealRegister *assignedRegister = getTargetRegister()->getAssignedRealRegister();
TR_RegisterSizes requestedRegSize = getOpCode().hasByteTarget() ? TR_ByteReg : TR_WordReg;
if (assignedRegister == NULL)
{
assignedRegister = assignGPRegister(this, getTargetRegister(), requestedRegSize, cg());
}
else if (requestedRegSize == TR_ByteReg)
{
assignedRegister = assign8BitGPRegister(this, getTargetRegister(), cg());
}
if (getTargetRegister()->decFutureUseCount() == 0 &&
assignedRegister->getState() != TR::RealRegister::Locked)
{
cg()->traceRegFreed(getTargetRegister(), assignedRegister);
getTargetRegister()->setAssignedRegister(NULL);
assignedRegister->setState(TR::RealRegister::Unlatched);
}
setTargetRegister(assignedRegister);
}
if (getDependencyConditions())
{
getTargetRegister()->block();
if ((cg()->getAssignmentDirection() == cg()->Backward))
{
getDependencyConditions()->assignPreConditionRegisters(this, kindsToBeAssigned, cg());
}
else
{
getDependencyConditions()->assignPostConditionRegisters(this, kindsToBeAssigned, cg());
}
getTargetRegister()->unblock();
}
}
////////////////////////////////////////////////////////////////////////////////
// TR::X86RegRegInstruction:: member functions
////////////////////////////////////////////////////////////////////////////////
TR::X86RegRegInstruction::X86RegRegInstruction(TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *treg,
TR::Register *sreg,
TR::CodeGenerator *cg)
: TR::X86RegInstruction(treg, node, op, cg), _sourceRegister(sreg)
{
useRegister(sreg);
}
TR::X86RegRegInstruction::X86RegRegInstruction(TR::Instruction *precedingInstruction,
TR::InstOpCode::Mnemonic op,
TR::Register *treg,
TR::Register *sreg,
TR::CodeGenerator *cg)
: TR::X86RegInstruction(treg, op, precedingInstruction, cg), _sourceRegister(sreg)
{
useRegister(sreg);
}
TR::X86RegRegInstruction::X86RegRegInstruction(TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *treg,
TR::Register *sreg,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg)
: TR::X86RegInstruction(cond, treg, node, op, cg), _sourceRegister(sreg)
{
useRegister(sreg);
}
TR::X86RegRegInstruction::X86RegRegInstruction(TR::Instruction *precedingInstruction,
TR::InstOpCode::Mnemonic op,
TR::Register *treg,
TR::Register *sreg,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg)
: TR::X86RegInstruction(cond, treg, op, precedingInstruction, cg), _sourceRegister(sreg)
{
useRegister(sreg);
}
bool TR::X86RegRegInstruction::refsRegister(TR::Register *reg)
{
if (reg == getTargetRegister() || reg == getSourceRegister())
{
return true;
}
else if (getDependencyConditions())
{
return getDependencyConditions()->refsRegister(reg);
}
return false;
}
bool TR::X86RegRegInstruction::defsRegister(TR::Register *reg)
{
if ((reg == getTargetRegister() && getOpCode().modifiesTarget()) ||
(reg == getSourceRegister() && getOpCode().modifiesSource()))
{
return true;
}
else if (getDependencyConditions())
{
return getDependencyConditions()->defsRegister(reg);
}
return false;
}
bool TR::X86RegRegInstruction::usesRegister(TR::Register *reg)
{
if ((reg == getTargetRegister() &&
getOpCode().usesTarget()) ||
reg == getSourceRegister())
{
return true;
}
else if (getDependencyConditions())
{
return getDependencyConditions()->usesRegister(reg);
}
return false;
}
void TR::X86RegRegInstruction::assignRegisters(TR_RegisterKinds kindsToBeAssigned)
{
if (getDependencyConditions())
{
if ((cg()->getAssignmentDirection() == cg()->Backward))
{
getTargetRegister()->block();
getSourceRegister()->block();
getDependencyConditions()->assignPostConditionRegisters(this, kindsToBeAssigned, cg());
getTargetRegister()->unblock();
getSourceRegister()->unblock();
}
}
if (kindsToBeAssigned & getTargetRegister()->getKindAsMask())
{
TR::Register *firstRegister = getTargetRegister();
TR::Register *secondRegister = getSourceRegister();
TR_RegisterSizes firstRequestedRegSize = getOpCode().hasByteTarget() ? TR_ByteReg :
getOpCode().hasXMMTarget() ? TR_QuadWordReg :
TR_WordReg;
TR_RegisterSizes secondRequestedRegSize = getOpCode().hasByteSource() ? TR_ByteReg :
getOpCode().hasXMMSource() ? TR_QuadWordReg :
TR_WordReg;
// Ensure both source and target registers have the
// same width if they are the same virtual register.
//
if (firstRegister == secondRegister)
{
firstRequestedRegSize = secondRequestedRegSize;
}
bool regRegCopy = isRegRegMove();
TR::InstOpCode::Mnemonic opCode = getOpCodeValue();
if (getDependencyConditions())
{
getDependencyConditions()->blockPreConditionRegisters();
getDependencyConditions()->blockPostConditionRegisters();
}
secondRegister->block();
TR::RealRegister *assignedFirstRegister = firstRegister->getAssignedRealRegister();
if (assignedFirstRegister == NULL)
{
assignedFirstRegister = assignGPRegister(this, firstRegister, firstRequestedRegSize, cg());
}
else if (firstRequestedRegSize == TR_ByteReg)
{
assignedFirstRegister = assign8BitGPRegister(this, firstRegister, cg());
}
if (firstRegister->decFutureUseCount() == 0 &&
assignedFirstRegister->getState() != TR::RealRegister::Locked)
{
cg()->traceRegFreed(firstRegister, assignedFirstRegister);
firstRegister->setAssignedRegister(NULL);
assignedFirstRegister->setState(TR::RealRegister::Unlatched);
}
secondRegister->unblock();
firstRegister->block();
TR::RealRegister *assignedSecondRegister = secondRegister->getAssignedRealRegister();
if (assignedSecondRegister == NULL)
{
TR::Machine *machine = cg()->machine();
cg()->clearRegisterAssignmentFlags();
cg()->setRegisterAssignmentFlag(TR_NormalAssignment);
// If first use, totaluse and futureuse will be the same
//
if (secondRegister->getTotalUseCount() == secondRegister->getFutureUseCount())
{
if (regRegCopy && assignedFirstRegister->getState() == TR::RealRegister::Unlatched)
{
assignedSecondRegister = assignedFirstRegister;
}
else if ((assignedSecondRegister = machine->findBestFreeGPRegister(this, secondRegister, secondRequestedRegSize, true)))
{
if (cg()->enableBetterSpillPlacements())
cg()->removeBetterSpillPlacementCandidate(toRealRegister(assignedSecondRegister));
}
else
{
cg()->setRegisterAssignmentFlag(TR_RegisterSpilled);
assignedSecondRegister = machine->freeBestGPRegister(this, secondRegister, secondRequestedRegSize);
}
}
// Depending on direction of assignment, must get register back from spilled state
//
else
{
cg()->setRegisterAssignmentFlag(TR_RegisterReloaded);
assignedSecondRegister = machine->reverseGPRSpillState(this, secondRegister, NULL, secondRequestedRegSize);
}
secondRegister->setAssignedRegister(assignedSecondRegister);
secondRegister->setAssignedAsByteRegister(secondRequestedRegSize == TR_ByteReg);
assignedSecondRegister->setAssignedRegister(secondRegister);
assignedSecondRegister->setState(TR::RealRegister::Assigned, secondRegister->isPlaceholderReg());
cg()->traceRegAssigned(secondRegister, assignedSecondRegister);
}
else if (secondRequestedRegSize == TR_ByteReg)
{
assignedSecondRegister = assign8BitGPRegister(this, secondRegister, cg());
}
if (secondRegister->decFutureUseCount() == 0 &&
assignedSecondRegister->getState() != TR::RealRegister::Locked)
{
cg()->traceRegFreed(secondRegister, assignedSecondRegister);
secondRegister->setAssignedRegister(NULL);
assignedSecondRegister->setState(TR::RealRegister::Unlatched);
}
firstRegister->unblock();
if (getDependencyConditions())
{
getDependencyConditions()->unblockPreConditionRegisters();
getDependencyConditions()->unblockPostConditionRegisters();
}
setTargetRegister(assignedFirstRegister);
setSourceRegister(assignedSecondRegister);
if (getSourceRegister() == getTargetRegister() && regRegCopy)
{
// Remove this instruction from the stream because it is a noop
// need to leave this instruction's pointers alone because they
// will be used in the main assignment loop to traverse to the
// instruction to be assigned after this one
//
if (getPrev())
{
getPrev()->setNext(getNext());
}
if (getNext())
{
getNext()->setPrev(getPrev());
}
}
// If both operands to an SSE conversion routine are the same XMMR,
// the type of the register needs to be flipped to that of the source
// operand during the backward pass, so that preceding code will see
// the correct type.
//
if (firstRegister == secondRegister)