-
Notifications
You must be signed in to change notification settings - Fork 392
/
OMRInstOpCode.enum
748 lines (745 loc) · 52.4 KB
/
OMRInstOpCode.enum
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
/*******************************************************************************
* Copyright (c) 2018, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
/*
* This file will be included within an enum. Only comments and enumerator
* definitions are permitted.
*/
#include "compiler/codegen/OMRInstOpCode.enum"
// Opcode BINARY OPCODE comments
/* Branch,exception generation and system Instruction */
/* Compare _ Branch (immediate) */
cbzw, /* 0x34000000 CBZ */
cbnzw, /* 0x35000000 CBNZ */
cbzx, /* 0xB4000000 CBZ */
cbnzx, /* 0xB5000000 CBNZ */
/* Test bit & branch (immediate) */
tbz, /* 0x36000000 TBZ */
tbnz, /* 0x37000000 TBNZ */
/* Conditional branch (immediate) */
b_cond, /* 0x54000000 B_cond */
/* Exception generation */
brkarm64, /* 0xD4200000 BRK AArch64 Specific BRK */
/* System */
dsb, /* 0xD503309F DSB */
dmb, /* 0xD50330BF DMB */
/* Unconditional branch (register) */
br, /* 0xD61F0000 BR */
blr, /* 0xD63F0000 BLR */
ret, /* 0xD65F0000 RET */
/* Unconditional branch (immediate) */
b, /* 0x14000000 B */
bl, /* 0x94000000 BL */
/* Loads and stores */
/* Load/store exclusive */
stxrb, /* 0x08007C00 STXRB */
stlxrb, /* 0x0800FC00 STLXRB */
ldxrb, /* 0x085F7C00 LDXRB */
ldaxrb, /* 0x085FFC00 LDAXRB */
stlrb, /* 0x089FFC00 STLRB */
ldarb, /* 0x08DFFC00 LDARB */
stxrh, /* 0x48007C00 STXRH */
stlxrh, /* 0x4800FC00 STLXRH */
ldxrh, /* 0x485F7C00 LDXRH */
ldaxrh, /* 0x485FFC00 LDAXRH */
stlrh, /* 0x489FFC00 STLRH */
ldarh, /* 0x48DFFC00 LDARH */
stxrw, /* 0x88007C00 STXR */
stlxrw, /* 0x8800FC00 STLXR */
stxpw, /* 0x88200000 STXP */
stlxpw, /* 0x88208000 STLXP */
ldxrw, /* 0x885F7C00 LDXR */
ldaxrw, /* 0x885FFC00 LDAXR */
ldxpw, /* 0x887F0000 LDXP */
ldaxpw, /* 0x887F8000 LDAXP */
stlrw, /* 0x889FFC00 STLR */
ldarw, /* 0x88DFFC00 LDAR */
stxrx, /* 0xC8007C00 STXR */
stlxrx, /* 0xC800FC00 STLXR */
stxpx, /* 0xC8200000 STXP */
stlxpx, /* 0xC8208000 STLXP */
ldxrx, /* 0xC85F7C00 LDXR */
ldaxrx, /* 0xC85FFC00 LDAXR */
ldxpx, /* 0xC87F0000 LDXP */
ldaxpx, /* 0xC87F8000 LDAXP */
stlrx, /* 0xC89FFC00 STLR */
ldarx, /* 0xC8DFFC00 LDAR */
/* Load register (literal) */
ldrw, /* 0x18000000 LDR */
vldrs, /* 0x1C000000 LDR */
ldrx, /* 0x58000000 LDR */
vldrd, /* 0x5C000000 LDR */
ldrsw, /* 0x98000000 LDRSW */
vldrq, /* 0x9C000000 LDR */
prfm, /* 0xD8000000 PRFM */
/* Load/store no-allocate pair (offset) */
stnpw, /* 0x28000000 STNP */
ldnpw, /* 0x28400000 LDNP */
vstnps, /* 0x2C000000 STNP */
vldnps, /* 0x2C400000 LDNP */
vstnpd, /* 0x6C000000 STNP */
vldnpd, /* 0x6C400000 LDNP */
stnpx, /* 0xA8000000 STNP */
ldnpx, /* 0xA8400000 LDNP */
vstnpq, /* 0xAC000000 STNP */
vldnpq, /* 0xAC400000 LDNP */
/* Load/store register pair (post-indexed) */
stppostw, /* 0x28800000 STP */
ldppostw, /* 0x28C00000 LDP */
vstpposts, /* 0x2C800000 STP */
vldpposts, /* 0x2CC00000 LDP */
ldpswpost, /* 0x68C00000 LDPSW */
vstppostd, /* 0x6C800000 STP */
vldppostd, /* 0x6CC00000 LDP */
stppostx, /* 0xA8800000 STP */
ldppostx, /* 0xA8C00000 LDP */
vstppostq, /* 0xAC800000 STP */
vldppostq, /* 0xACC00000 LDP */
/* Load/store register pair (offset) */
stpoffw, /* 0x29000000 STP */
ldpoffw, /* 0x29400000 LDP */
vstpoffs, /* 0x2D000000 STP */
vldpoffs, /* 0x2D400000 LDP */
ldpswoff, /* 0x69400000 LDPSW */
vstpoffd, /* 0x6D000000 STP */
vldpoffd, /* 0x6D400000 LDP */
stpoffx, /* 0xA9000000 STP */
ldpoffx, /* 0xA9400000 LDP */
vstpoffq, /* 0xAD000000 STP */
vldpoffq, /* 0xAD400000 LDP */
/* Load/store register pair (pre-indexed) */
stpprew, /* 0x29800000 STP */
ldpprew, /* 0x29C00000 LDP */
vstppres, /* 0x2D800000 STP */
vldppres, /* 0x2DC00000 LDP */
ldpswpre, /* 0x69C00000 LDPSW */
vstppred, /* 0x6D800000 STP */
vldppred, /* 0x6DC00000 LDP */
stpprex, /* 0xA9800000 STP */
ldpprex, /* 0xA9C00000 LDP */
vstppreq, /* 0xAD800000 STP */
vldppreq, /* 0xADC00000 LDP */
/* Load/store register (unscaled immediate) */
sturb, /* 0x38000000 STURB */
ldurb, /* 0x38400000 LDURB */
ldursbx, /* 0x38800000 LDURSB */
ldursbw, /* 0x38C00000 LDURSB */
vsturb, /* 0x3C000000 STUR */
vldurb, /* 0x3C400000 LDUR */
vsturq, /* 0x3C800000 STUR */
vldurq, /* 0x3CC00000 LDUR */
sturh, /* 0x78000000 STURH */
ldurh, /* 0x78400000 LDURH */
ldurshx, /* 0x78800000 LDURSH */
ldurshw, /* 0x78C00000 LDURSH */
vsturh, /* 0x7C000000 STUR */
vldurh, /* 0x7C400000 LDUR */
sturw, /* 0xB8000000 STUR */
ldurw, /* 0xB8400000 LDUR */
ldursw, /* 0xB8800000 LDURSW */
vsturs, /* 0xBC000000 STUR */
vldurs, /* 0xBC400000 LDUR */
sturx, /* 0xF8000000 STUR */
ldurx, /* 0xF8400000 LDUR */
prfum, /* 0xF8800000 PRFUM */
vsturd, /* 0xFC000000 STUR */
vldurd, /* 0xFC400000 LDUR */
/* Load/store register (immediate post-indexed) */
strbpost, /* 0x38000400 STRB */
ldrbpost, /* 0x38400400 LDRB */
ldrsbpostx, /* 0x38800400 LDRSB */
ldrsbpostw, /* 0x38C00400 LDRSB */
vstrpostb, /* 0x3C000400 STR */
vldrpostb, /* 0x3C400400 LDR */
vstrpostq, /* 0x3C800400 STR */
vldrpostq, /* 0x3CC00400 LDR */
strhpost, /* 0x78000400 STRH */
ldrhpost, /* 0x78400400 LDRH */
ldrshpostx, /* 0x78800400 LDRSH */
ldrshpostw, /* 0x78C00400 LDRSH */
vstrposth, /* 0x7C000400 STR */
vldrposth, /* 0x7C400400 LDR */
strpostw, /* 0xB8000400 STR */
ldrpostw, /* 0xB8400400 LDR */
ldrswpost, /* 0xB8800400 LDRSW */
vstrposts, /* 0xBC000400 STR */
vldrposts, /* 0xBC400400 LDR */
strpostx, /* 0xF8000400 STR */
ldrpostx, /* 0xF8400400 LDR */
vstrpostd, /* 0xFC000400 STR */
vldrpostd, /* 0xFC400400 LDR */
/* Load/store register (unprivileged) */
sttrb, /* 0x38000800 STTRB */
ldtrb, /* 0x38400800 LDTRB */
ldtrsbx, /* 0x38800800 LDTRSB */
ldtrsbw, /* 0x38C00800 LDTRSB */
sttrh, /* 0x78000800 STTRH */
ldtrh, /* 0x78400800 LDTRH */
ldtrshx, /* 0x78800800 LDTRSH */
ldtrshw, /* 0x78C00800 LDTRSH */
sttrw, /* 0xB8000800 STTR */
ldtrw, /* 0xB8400800 LDTR */
ldtrsw, /* 0xB8800800 LDTRSW */
sttrx, /* 0xF8000800 STTR */
ldtrx, /* 0xF8400800 LDTR */
/* Load/store register (immediate pre-indexed) */
strbpre, /* 0x38000C00 STRB */
ldrbpre, /* 0x38400C00 LDRB */
ldrsbprex, /* 0x38800C00 LDRSB */
ldrsbprew, /* 0x38C00C00 LDRSB */
vstrpreb, /* 0x3C000C00 STR */
vldrpreb, /* 0x3C400C00 LDR */
vstrpreq, /* 0x3C800C00 STR */
vldrpreq, /* 0x3CC00C00 LDR */
strhpre, /* 0x78000C00 STRH */
ldrhpre, /* 0x78400C00 LDRH */
ldrshprex, /* 0x78800C00 LDRSH */
ldrshprew, /* 0x78C00C00 LDRSH */
vstrpreh, /* 0x7C000C00 STR */
vldrpreh, /* 0x7C400C00 LDR */
strprew, /* 0xB8000C00 STR */
ldrprew, /* 0xB8400C00 LDR */
ldrswpre, /* 0xB8800C00 LDRSW */
vstrpres, /* 0xBC000C00 STR */
vldrpres, /* 0xBC400C00 LDR */
strprex, /* 0xF8000C00 STR */
ldrprex, /* 0xF8400C00 LDR */
vstrpred, /* 0xFC000C00 STR */
vldrpred, /* 0xFC400C00 LDR */
/* Load/store register (register offset) */
strboff, /* 0x38200800 STRB */
ldrboff, /* 0x38600800 LDRB */
ldrsboffx, /* 0x38A00800 LDRSB */
ldrsboffw, /* 0x38E00800 LDRSB */
vstroffb, /* 0x3C200800 STR */
vldroffb, /* 0x3C600800 LDR */
vstroffq, /* 0x3CA00800 STR */
vldroffq, /* 0x3CE00800 LDR */
strhoff, /* 0x78200800 STRH */
ldrhoff, /* 0x78600800 LDRH */
ldrshoffx, /* 0x78A00800 LDRSH */
ldrshoffw, /* 0x78E00800 LDRSH */
vstroffh, /* 0x7C200800 STR */
vldroffh, /* 0x7C600800 LDR */
stroffw, /* 0xB8200800 STR */
ldroffw, /* 0xB8600800 LDR */
ldrswoff, /* 0xB8A00800 LDRSW */
vstroffs, /* 0xBC200800 STR */
vldroffs, /* 0xBC600800 LDR */
stroffx, /* 0xF8200800 STR */
ldroffx, /* 0xF8600800 LDR */
vstroffd, /* 0xFC200800 STR */
vldroffd, /* 0xFC600800 LDR */
prfmoff, /* 0xF8A00800 PRFM */
/* Load/store register (unsigned immediate) */
strbimm, /* 0x39000000 STRB */
ldrbimm, /* 0x39400000 LDRB */
ldrsbimmx, /* 0x39800000 LDRSB */
ldrsbimmw, /* 0x39C00000 LDRSB */
vstrimmb, /* 0x3D000000 STR */
vldrimmb, /* 0x3D400000 LDR */
vstrimmq, /* 0x3D800000 STR */
vldrimmq, /* 0x3DC00000 LDR */
strhimm, /* 0x79000000 STRH */
ldrhimm, /* 0x79400000 LDRH */
ldrshimmx, /* 0x79800000 LDRSH */
ldrshimmw, /* 0x79C00000 LDRSH */
vstrimmh, /* 0x7D000000 STR */
vldrimmh, /* 0x7D400000 LDR */
strimmw, /* 0xB9000000 STR */
ldrimmw, /* 0xB9400000 LDR */
ldrswimm, /* 0xB9800000 LDRSW */
vstrimms, /* 0xBD000000 STR */
vldrimms, /* 0xBD400000 LDR */
strimmx, /* 0xF9000000 STR */
ldrimmx, /* 0xF9400000 LDR */
vstrimmd, /* 0xFD000000 STR */
vldrimmd, /* 0xFD400000 LDR */
prfmimm, /* 0xF9800000 PRFM */
/* Atomic instructions introduced by FEAT_LSE */
/* Atomic memory operation instructions */
ldaddx, /* 0xF8200000 LDADD */
ldaddax, /* 0xF8A00000 LDADDA */
ldaddlx, /* 0xF8600000 LDADDL */
ldaddalx, /* 0xF8E00000 LDADDAL */
ldaddw, /* 0xB8200000 LDADD */
ldaddaw, /* 0xB8A00000 LDADDA */
ldaddlw, /* 0xB8600000 LDADDL */
ldaddalw, /* 0xB8E00000 LDADDAL */
ldaddb, /* 0x38200000 LDADDB */
ldaddab, /* 0x38A00000 LDADDAB */
ldaddlb, /* 0x38600000 LDADDLB */
ldaddalb, /* 0x38E00000 LDADDALB */
ldaddh, /* 0x78200000 LDADDH */
ldaddah, /* 0x78A00000 LDADDAH */
ldaddlh, /* 0x78600000 LDADDLH */
ldaddalh, /* 0x78E00000 LDADDALH */
ldclrx, /* 0xF8201000 LDCLR */
ldclrax, /* 0xF8A01000 LDCLRA */
ldclrlx, /* 0xF8601000 LDCLRL */
ldclralx, /* 0xF8E01000 LDCLRAL */
ldclrw, /* 0xB8201000 LDCLR */
ldclraw, /* 0xB8A01000 LDCLRA */
ldclrlw, /* 0xB8601000 LDCLRL */
ldclralw, /* 0xB8E01000 LDCLRAL */
ldclrb, /* 0x38201000 LDCLRB */
ldclrab, /* 0x38A01000 LDCLRAB */
ldclrlb, /* 0x38601000 LDCLRLB */
ldclralb, /* 0x38E01000 LDCLRALB */
ldclrh, /* 0x78201000 LDCLRH */
ldclrah, /* 0x78A01000 LDCLRAH */
ldclrlh, /* 0x78601000 LDCLRLH */
ldclralh, /* 0x78E01000 LDCLRALH */
ldeorx, /* 0xF8202000 LDEOR */
ldeorax, /* 0xF8A02000 LDEORA */
ldeorlx, /* 0xF8602000 LDEORL */
ldeoralx, /* 0xF8E02000 LDEORAL */
ldeorw, /* 0xB8202000 LDEOR */
ldeoraw, /* 0xB8A02000 LDEORA */
ldeorlw, /* 0xB8602000 LDEORL */
ldeoralw, /* 0xB8E02000 LDEORAL */
ldeorb, /* 0x38202000 LDEORB */
ldeorab, /* 0x38A02000 LDEORAB */
ldeorlb, /* 0x38602000 LDEORLB */
ldeoralb, /* 0x38E02000 LDEORALB */
ldeorh, /* 0x78202000 LDEORH */
ldeorah, /* 0x78A02000 LDEORAH */
ldeorlh, /* 0x78602000 LDEORLH */
ldeoralh, /* 0x78E02000 LDEORALH */
ldsetx, /* 0xF8203000 LDSET */
ldsetax, /* 0xF8A03000 LDSETA */
ldsetlx, /* 0xF8603000 LDSETL */
ldsetalx, /* 0xF8E03000 LDSETAL */
ldsetw, /* 0xB8203000 LDSET */
ldsetaw, /* 0xB8A03000 LDSETA */
ldsetlw, /* 0xB8603000 LDSETL */
ldsetalw, /* 0xB8E03000 LDSETAL */
ldsetb, /* 0x38203000 LDSETB */
ldsetab, /* 0x38A03000 LDSETAB */
ldsetlb, /* 0x38603000 LDSETLB */
ldsetalb, /* 0x38E03000 LDSETALB */
ldseth, /* 0x78203000 LDSETH */
ldsetah, /* 0x78A03000 LDSETAH */
ldsetlh, /* 0x78603000 LDSETLH */
ldsetalh, /* 0x78E03000 LDSETALH */
ldsmaxx, /* 0xF8204000 LDSMAX */
ldsmaxax, /* 0xF8A04000 LDSMAXA */
ldsmaxlx, /* 0xF8604000 LDSMAXL */
ldsmaxalx, /* 0xF8E04000 LDSMAXAL */
ldsmaxw, /* 0xB8204000 LDSMAX */
ldsmaxaw, /* 0xB8A04000 LDSMAXA */
ldsmaxlw, /* 0xB8604000 LDSMAXL */
ldsmaxalw, /* 0xB8E04000 LDSMAXAL */
ldsmaxb, /* 0x38204000 LDSMAXB */
ldsmaxab, /* 0x38A04000 LDSMAXAB */
ldsmaxlb, /* 0x38604000 LDSMAXLB */
ldsmaxalb, /* 0x38E04000 LDSMAXALB */
ldsmaxh, /* 0x78204000 LDSMAXH */
ldsmaxah, /* 0x78A04000 LDSMAXAH */
ldsmaxlh, /* 0x78604000 LDSMAXLH */
ldsmaxalh, /* 0x78E04000 LDSMAXALH */
ldsminx, /* 0xF8205000 LDSMIN */
ldsminax, /* 0xF8A05000 LDSMINA */
ldsminlx, /* 0xF8605000 LDSMINL */
ldsminalx, /* 0xF8E05000 LDSMINAL */
ldsminw, /* 0xB8205000 LDSMIN */
ldsminaw, /* 0xB8A05000 LDSMINA */
ldsminlw, /* 0xB8605000 LDSMINL */
ldsminalw, /* 0xB8E05000 LDSMINAL */
ldsminb, /* 0x38205000 LDSMINB */
ldsminab, /* 0x38A05000 LDSMINAB */
ldsminlb, /* 0x38605000 LDSMINLB */
ldsminalb, /* 0x38E05000 LDSMINALB */
ldsminh, /* 0x78205000 LDSMINH */
ldsminah, /* 0x78A05000 LDSMINAH */
ldsminlh, /* 0x78605000 LDSMINLH */
ldsminalh, /* 0x78E05000 LDSMINALH */
ldumaxx, /* 0xF8206000 LDUMAX */
ldumaxax, /* 0xF8A06000 LDUMAXA */
ldumaxlx, /* 0xF8606000 LDUMAXL */
ldumaxalx, /* 0xF8E06000 LDUMAXAL */
ldumaxw, /* 0xB8206000 LDUMAX */
ldumaxaw, /* 0xB8A06000 LDUMAXA */
ldumaxlw, /* 0xB8606000 LDUMAXL */
ldumaxalw, /* 0xB8E06000 LDUMAXAL */
ldumaxb, /* 0x38206000 LDUMAXB */
ldumaxab, /* 0x38A06000 LDUMAXAB */
ldumaxlb, /* 0x38606000 LDUMAXLB */
ldumaxalb, /* 0x38E06000 LDUMAXALB */
ldumaxh, /* 0x78206000 LDUMAXH */
ldumaxah, /* 0x78A06000 LDUMAXAH */
ldumaxlh, /* 0x78606000 LDUMAXLH */
ldumaxalh, /* 0x78E06000 LDUMAXALH */
lduminx, /* 0xF8207000 LDUMIN */
lduminax, /* 0xF8A07000 LDUMINA */
lduminlx, /* 0xF8607000 LDUMINL */
lduminalx, /* 0xF8E07000 LDUMINAL */
lduminw, /* 0xB8207000 LDUMIN */
lduminaw, /* 0xB8A07000 LDUMINA */
lduminlw, /* 0xB8607000 LDUMINL */
lduminalw, /* 0xB8E07000 LDUMINAL */
lduminb, /* 0x38207000 LDUMINB */
lduminab, /* 0x38A07000 LDUMINAB */
lduminlb, /* 0x38607000 LDUMINLB */
lduminalb, /* 0x38E07000 LDUMINALB */
lduminh, /* 0x78207000 LDUMINH */
lduminah, /* 0x78A07000 LDUMINAH */
lduminlh, /* 0x78607000 LDUMINLH */
lduminalh, /* 0x78E07000 LDUMINALH */
staddx, /* 0xF820001F STADD */
staddlx, /* 0xF860001F STADDL */
staddw, /* 0xB820001F STADD */
staddlw, /* 0xB860001F STADDL */
staddb, /* 0x3820001F STADDB */
staddlb, /* 0x3860001F STADDLB */
staddh, /* 0x7820001F STADDH */
staddlh, /* 0x7860001F STADDLH */
stclrx, /* 0xF820101F STCLR */
stclrlx, /* 0xF860101F STCLRL */
stclrw, /* 0xB820101F STCLR */
stclrlw, /* 0xB860101F STCLRL */
stclrb, /* 0x3820101F STCLRB */
stclrlb, /* 0x3860101F STCLRLB */
stclrh, /* 0x7820101F STCLRH */
stclrlh, /* 0x7860101F STCLRLH */
steorx, /* 0xF820201F STEOR */
steorlx, /* 0xF860201F STEORL */
steorw, /* 0xB820201F STEOR */
steorlw, /* 0xB860201F STEORL */
steorb, /* 0x3820201F STEORB */
steorlb, /* 0x3860201F STEORLB */
steorh, /* 0x7820201F STEORH */
steorlh, /* 0x7860201F STEORLH */
stsetx, /* 0xF820301F STSET */
stsetlx, /* 0xF860301F STSETL */
stsetw, /* 0xB820301F STSET */
stsetlw, /* 0xB860301F STSETL */
stsetb, /* 0x3820301F STSETB */
stsetlb, /* 0x3860301F STSETLB */
stseth, /* 0x7820301F STSETH */
stsetlh, /* 0x7860301F STSETLH */
stsmaxx, /* 0xF820401F STSMAX */
stsmaxlx, /* 0xF860401F STSMAXL */
stsmaxw, /* 0xB820401F STSMAX */
stsmaxlw, /* 0xB860401F STSMAXL */
stsmaxb, /* 0x3820401F STSMAXB */
stsmaxlb, /* 0x3860401F STSMAXLB */
stsmaxh, /* 0x7820401F STSMAXH */
stsmaxlh, /* 0x7860401F STSMAXLH */
stsminx, /* 0xF820501F STSMIN */
stsminlx, /* 0xF860501F STSMINL */
stsminw, /* 0xB820501F STSMIN */
stsminlw, /* 0xB860501F STSMINL */
stsminb, /* 0x3820501F STSMINB */
stsminlb, /* 0x3860501F STSMINLB */
stsminh, /* 0x7820501F STSMINH */
stsminlh, /* 0x7860501F STSMINLH */
stumaxx, /* 0xF820601F STUMAX */
stumaxlx, /* 0xF860601F STUMAXL */
stumaxw, /* 0xB820601F STUMAX */
stumaxlw, /* 0xB860601F STUMAXL */
stumaxb, /* 0x3820601F STUMAXB */
stumaxlb, /* 0x3860601F STUMAXLB */
stumaxh, /* 0x7820601F STUMAXH */
stumaxlh, /* 0x7860601F STUMAXLH */
stuminx, /* 0xF820701F STUMIN */
stuminlx, /* 0xF860701F STUMINL */
stuminw, /* 0xB820701F STUMIN */
stuminlw, /* 0xB860701F STUMINL */
stuminb, /* 0x3820701F STUMINB */
stuminlb, /* 0x3860701F STUMINLB */
stuminh, /* 0x7820701F STUMINH */
stuminlh, /* 0x7860701F STUMINLH */
/* Swap instructions */
swpx, /* 0xF8208000 SWP */
swpax, /* 0xF8A08000 SWPA */
swplx, /* 0xF8608000 SWPL */
swpalx, /* 0xF8E08000 SWPAL */
swpw, /* 0xB8208000 SWP */
swpaw, /* 0xB8A08000 SWPA */
swplw, /* 0xB8608000 SWPL */
swpalw, /* 0xB8E08000 SWPAL */
swpb, /* 0x38208000 SWPB */
swpab, /* 0x38A08000 SWPAB */
swplb, /* 0x38608000 SWPLB */
swpalb, /* 0x38E08000 SWPALB */
swph, /* 0x78208000 SWPH */
swpah, /* 0x78A08000 SWPAH */
swplh, /* 0x78608000 SWPLH */
swpalh, /* 0x78E08000 SWPALH */
/* Compare and swap instructions */
casx, /* 0xC8A07C00 CAS */
casax, /* 0xC8E07C00 CASA */
caslx, /* 0xC8A0FC00 CASL */
casalx, /* 0xC8E0FC00 CASAL */
casw, /* 0x88A07C00 CAS */
casaw, /* 0x88E07C00 CASA */
caslw, /* 0x88A0FC00 CASL */
casalw, /* 0x88E0FC00 CASAL */
casb, /* 0x08A07C00 CASB */
casab, /* 0x08E07C00 CASAB */
caslb, /* 0x08A0FC00 CASLB */
casalb, /* 0x08E0FC00 CASALB */
cash, /* 0x48A07C00 CASH */
casah, /* 0x48E07C00 CASAH */
caslh, /* 0x48A0FC00 CASLH */
casalh, /* 0x48E0FC00 CASALH */
/* Data processing - Immediate */
/* PC-rel. addressing */
adr, /* 0x10000000 ADR */
adrp, /* 0x90000000 ADRP */
/* Add/subtract (immediate) */
addimmw, /* 0x11000000 ADD */
addsimmw, /* 0x31000000 ADDS */
subimmw, /* 0x51000000 SUB */
subsimmw, /* 0x71000000 SUBS */
addimmx, /* 0x91000000 ADD */
addsimmx, /* 0xB1000000 ADDS */
subimmx, /* 0xD1000000 SUB */
subsimmx, /* 0xF1000000 SUBS */
/* Logical (immediate) */
andimmw, /* 0x12000000 AND */
orrimmw, /* 0x32000000 ORR */
eorimmw, /* 0x52000000 EOR */
andsimmw, /* 0x72000000 ANDS */
andimmx, /* 0x92000000 AND */
orrimmx, /* 0xB2000000 ORR */
eorimmx, /* 0xD2000000 EOR */
andsimmx, /* 0xF2000000 ANDS */
/* Move wide (immediate) */
movnw, /* 0x12800000 MOVN */
movzw, /* 0x52800000 MOVZ */
movkw, /* 0x72800000 MOVK */
movnx, /* 0x92800000 MOVN */
movzx, /* 0xD2800000 MOVZ */
movkx, /* 0xF2800000 MOVK */
/* Bitfield */
sbfmw, /* 0x13000000 SBFM */
bfmw, /* 0x33000000 BFM */
ubfmw, /* 0x53000000 UBFM */
sbfmx, /* 0x93400000 SBFM */
bfmx, /* 0xB3400000 BFM */
ubfmx, /* 0xD3400000 UBFM */
/* Extract */
extrw, /* 0x13800000 EXTR */
extrx, /* 0x93C00000 EXTR */
/* Data Processing - register */
/* Logical (shifted register) */
andw, /* 0x0A000000 AND */
bicw, /* 0x0A200000 BIC */
orrw, /* 0x2A000000 ORR */
ornw, /* 0x2A200000 ORN */
eorw, /* 0x4A000000 EOR */
eonw, /* 0x4A200000 EON */
andsw, /* 0x6A000000 ANDS */
bicsw, /* 0x6A200000 BICS */
andx, /* 0x8A000000 AND */
bicx, /* 0x8A200000 BIC */
orrx, /* 0xAA000000 ORR */
ornx, /* 0xAA200000 ORN */
eorx, /* 0xCA000000 EOR */
eonx, /* 0xCA200000 EON */
andsx, /* 0xEA000000 ANDS */
bicsx, /* 0xEA200000 BICS */
/* Add/subtract (shifted register) */
addw, /* 0x0B000000 ADD */
addsw, /* 0x2B000000 ADDS */
subw, /* 0x4B000000 SUB */
subsw, /* 0x6B000000 SUBS */
addx, /* 0x8B000000 ADD */
addsx, /* 0xAB000000 ADDS */
subx, /* 0xCB000000 SUB */
subsx, /* 0xEB000000 SUBS */
/* Add/subtract (extended register) */
addextw, /* 0x0B200000 ADD */
addsextw, /* 0x2B200000 ADDS */
subextw, /* 0x4B200000 SUB */
subsextw, /* 0x6B200000 SUBS */
addextx, /* 0x8B200000 ADD */
addsextx, /* 0xAB200000 ADDS */
subextx, /* 0xCB200000 SUB */
subsextx, /* 0xEB200000 SUBS */
/* Add/subtract (with carry) */
adcw, /* 0x1A000000 ADC */
adcsw, /* 0x3A000000 ADCS */
sbcw, /* 0x5A000000 SBC */
sbcsw, /* 0x7A000000 SBCS */
adcx, /* 0x9A000000 ADC */
adcsx, /* 0xBA000000 ADCS */
sbcx, /* 0xDA000000 SBC */
sbcsx, /* 0xFA000000 SBCS */
/* Conditional compare (register) */
ccmnw, /* 0x3A400000 CCMN */
ccmnx, /* 0xBA400000 CCMN */
ccmpw, /* 0x7A400000 CCMP */
ccmpx, /* 0xFA400000 CCMP */
/* Conditional compare (immediate) */
ccmnimmw, /* 0x3A400800 CCMN */
ccmnimmx, /* 0xBA400800 CCMN */
ccmpimmw, /* 0x7A400800 CCMP */
ccmpimmx, /* 0xFA400800 CCMP */
/* Conditional select */
cselw, /* 0x1A800000 CSEL */
csincw, /* 0x1A800400 CSINC */
csinvw, /* 0x5A800000 CSINV */
csnegw, /* 0x5A800400 CSNEG */
cselx, /* 0x9A800000 CSEL */
csincx, /* 0x9A800400 CSINC */
csinvx, /* 0xDA800000 CSINV */
csnegx, /* 0xDA800400 CSNEG */
/* Data-processing (3 source) */
maddw, /* 0x1B000000 MADD */
maddx, /* 0x9B000000 MADD */
smaddl, /* 0x9B200000 SMADDL */
umaddl, /* 0x9BA00000 UMADDL */
msubw, /* 0x1B008000 MSUB */
msubx, /* 0x9B008000 MSUB */
smsubl, /* 0x9B208000 SMSUBL */
umsubl, /* 0x9BA08000 UMSUBL */
smulh, /* 0x9B400000 SMULH */
umulh, /* 0x9BC00000 UMULH */
fmaddd, /* 0X1F000000 FMADD */
fmadds, /* 0X1F400000 FMADD */
/* Data-processing (2 source) */
crc32x, /* 0x9AC04C00 CRC32X */
crc32cx, /* 0x9AC05C00 CRC32CX */
crc32b, /* 0x1AC04000 CRC32B */
crc32cb, /* 0x1AC05000 CRC32CB */
crc32h, /* 0x1AC04400 CRC32H */
crc32ch, /* 0x1AC05400 CRC32CH */
crc32w, /* 0x1AC04800 CRC32W */
crc32cw, /* 0x1AC05800 CRC32CW */
udivw, /* 0x1AC00800 UDIV */
udivx, /* 0x9AC00800 UDIV */
sdivw, /* 0x1AC00C00 SDIV */
sdivx, /* 0x9AC00C00 SDIV */
lslvw, /* 0x1AC02000 LSLV */
lslvx, /* 0x9AC02000 LSLV */
lsrvw, /* 0x1AC02400 LSRV */
lsrvx, /* 0x9AC02400 LSRV */
asrvw, /* 0x1AC02800 ASRV */
asrvx, /* 0x9AC02800 ASRV */
rorvw, /* 0x1AC02C00 RORV */
rorvx, /* 0x9AC02C00 RORV */
/* Data-processing (1 source) */
rbitw, /* 0x5AC00000 RBIT */
rbitx, /* 0xDAC00000 RBIT */
clzw, /* 0x5AC01000 CLZ */
clzx, /* 0xDAC01000 CLZ */
clsw, /* 0x5AC01400 CLS */
clsx, /* 0xDAC01400 CLS */
revw, /* 0x5AC00800 REV */
revx, /* 0xDAC00C00 REV */
rev16w, /* 0xDAC00400 REV16 */
rev16x, /* 0x5AC00400 REV16 */
rev32, /* 0xDAC00800 REV32 */
/* VFP instructions */
/* Floating-Point Conversion */
fmov_stow, /* 0x1E260000 FMOV */
fmov_wtos, /* 0x1E270000 FMOV */
fmov_dtox, /* 0x9E660000 FMOV */
fmov_xtod, /* 0x9E670000 FMOV */
fcvt_stod, /* 0x1E22C000 FCVT */
fcvt_dtos, /* 0x1E624000 FCVT */
fcvtzs_stow, /* 0x1E380000 FCVTZS */
fcvtzs_dtow, /* 0x1E780000 FCVTZS */
fcvtzs_stox, /* 0x9E380000 FCVTZS */
fcvtzs_dtox, /* 0x9E780000 FCVTZS */
scvtf_wtos, /* 0x1E220000 SCVTF */
scvtf_wtod, /* 0x1E620000 SCVTF */
scvtf_xtos, /* 0x9E220000 SCVTF */
scvtf_xtod, /* 0x9E620000 SCVTF */
/* Floating-Point Immediate */
fmovimms, /* 0x1E201000 FMOV */
fmovimmd, /* 0x1E601000 FMOV */
/* Move Immediate */
movi0s, /* 0x0F000400 MOVI */
movi0d, /* 0x2F00E400 MOVI */
/* Floating-Point Compare */
fcmps, /* 0x1E202000 FCMP */
fcmps_zero, /* 0x1E202008 FCMP */
fcmpd, /* 0x1E602000 FCMP */
fcmpd_zero, /* 0x1E602008 FCMP */
/* Floating-point conditional select */
fcsels, /* 0x1E200C00 FCSEL */
fcseld, /* 0x1E600C00 FCSEL */
/* Floating-Point Data-processing (1 source) */
fmovs, /* 0x1E204000 FMOV */
fmovd, /* 0x1E604000 FMOV */
fabss, /* 0x1E20C000 FABS */
fabsd, /* 0x1E60C000 FABS */
fnegs, /* 0x1E214000 FNEG */
fnegd, /* 0x1E614000 FNEG */
fsqrts, /* 0x1E21C000 FSQRT */
fsqrtd, /* 0x1E61C000 FSQRT */
/* Floating-Point Data-processing (2 source) */
fadds, /* 0x1E202800 FADD */
faddd, /* 0x1E602800 FADD */
fsubs, /* 0x1E203800 FSUB */
fsubd, /* 0x1E603800 FSUB */
fmuls, /* 0x1E200800 FMUL */
fmuld, /* 0x1E600800 FMUL */
fdivs, /* 0x1E201800 FDIV */
fdivd, /* 0x1E601800 FDIV */
fmaxs, /* 0x1E204800 FMAX */
fmaxd, /* 0x1E604800 FMAX */
fmins, /* 0x1E205800 FMIN */
fmind, /* 0x1E605800 FMIN */
/* Vector Data-processing (2 source) */
vorr2d, /* 0x4EA01C00 ORR */
vadd16b, /* 0x4E208400 ADD */
vadd8h, /* 0x4E608400 ADD */
vadd4s, /* 0x4EA08400 ADD */
vadd2d, /* 0x4EE08400 ADD */
vfadd4s, /* 0x4E20D400 FADD */
vfadd2d, /* 0x4E60D400 FADD */
vsub16b, /* 0x6E208400 SUB */
vsub8h, /* 0x6E608400 SUB */
vsub4s, /* 0x6EA08400 SUB */
vsub2d, /* 0x6EE08400 SUB */
vfsub4s, /* 0x4EA0D400 FSUB */
vfsub2d, /* 0x4EE0D400 FSUB */
vmul16b, /* 0x4E209C00 MUL */
vmul8h, /* 0x4E609C00 MUL */
vmul4s, /* 0x4EA09C00 MUL */
vfmul4s, /* 0x6E20DC00 FMUL */
vfmul2d, /* 0x6E60DC00 FMUL */
vfdiv4s, /* 0x6E20FC00 FDIV */
vfdiv2d, /* 0x6E60FC00 FDIV */
vand16b, /* 0x4E201C00 AND */
vorr16b, /* 0x4EA01C00 ORR */
veor16b, /* 0x6E201C00 EOR */
/* Vector Data-processing (1 source) */
vneg16b, /* 0x6E20B800 NEG */
vneg8h, /* 0x6E60B800 NEG */
vfneg4s, /* 0x6EA0F800 FNEG */
vfneg2d, /* 0x6EE0F800 FNEG */
vnot16b, /* 0x6E205800 NOT */
vdup16b, /* 0x4E010C00 DUP */
vdup8h, /* 0x4E020C00 DUP */
vdup4s, /* 0x4E040C00 DUP */
vdup2d, /* 0x4E080C00 DUP */
vfdup4s, /* 0x4E040400 DUP */
vfdup2d, /* 0x4E080400 DUP */
/* Hint instructions */
nop, /* 0xD503201F NOP */
/* Internal OpCodes */
ARM64LastOp = nop,
ARM64NumOpCodes = ARM64LastOp+1,