/
OMRCodeGenerator.cpp
6160 lines (5376 loc) · 223 KB
/
OMRCodeGenerator.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*******************************************************************************
* Copyright (c) 2000, 2019 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
// On zOS XLC linker can't handle files with same name at link time.
// This workaround with pragma is needed. What this does is essentially
// give a different name to the codesection (csect) for this file. So it
// doesn't conflict with another file with the same name.
#pragma csect(CODE,"TRZCGBase#C")
#pragma csect(STATIC,"TRZCGBase#S")
#pragma csect(TEST,"TRZCGBase#T")
#include <algorithm>
#include <limits.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "codegen/BackingStore.hpp"
#include "codegen/CodeGenPhase.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/CodeGenerator_inlines.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "codegen/FrontEnd.hpp"
#include "codegen/GCStackAtlas.hpp"
#include "codegen/GCStackMap.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LinkageConventionsEnum.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/RecognizedMethods.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/RegisterIterator.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/Snippet.hpp"
#include "codegen/StorageInfo.hpp"
#include "codegen/SystemLinkage.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "compile/Compilation.hpp"
#include "compile/Method.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "compile/VirtualGuard.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "control/Recompilation.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "control/RecompilationInfo.hpp"
#endif
#include "cs2/arrayof.h"
#include "cs2/hashtab.h"
#include "cs2/sparsrbit.h"
#include "env/CompilerEnv.hpp"
#include "env/IO.hpp"
#include "env/Processors.hpp"
#include "env/StackMemoryRegion.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/AliasSetInterface.hpp"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "il/symbol/AutomaticSymbol.hpp"
#include "il/symbol/LabelSymbol.hpp"
#include "il/symbol/MethodSymbol.hpp"
#include "il/symbol/ParameterSymbol.hpp"
#include "il/symbol/ResolvedMethodSymbol.hpp"
#include "il/symbol/StaticSymbol.hpp"
#include "infra/Array.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "infra/BitVector.hpp"
#include "infra/Cfg.hpp"
#include "infra/Flags.hpp"
#include "infra/HashTab.hpp"
#include "infra/List.hpp"
#include "infra/Random.hpp"
#include "infra/SimpleRegex.hpp"
#include "infra/Stack.hpp"
#include "infra/CfgEdge.hpp"
#include "optimizer/OptimizationManager.hpp"
#include "optimizer/Optimizations.hpp"
#include "optimizer/Optimizer.hpp"
#include "optimizer/RegisterCandidate.hpp"
#include "optimizer/Structure.hpp"
#include "optimizer/DataFlowAnalysis.hpp"
#include "ras/Debug.hpp"
#include "ras/DebugCounter.hpp"
#include "ras/Delimiter.hpp"
#include "runtime/CodeCache.hpp"
#include "runtime/Runtime.hpp"
#include "z/codegen/CallSnippet.hpp"
#include "z/codegen/EndianConversion.hpp"
#include "z/codegen/OpMemToMem.hpp"
#include "z/codegen/S390Evaluator.hpp"
#include "z/codegen/S390GenerateInstructions.hpp"
#include "z/codegen/S390Instruction.hpp"
#include "z/codegen/S390Peephole.hpp"
#include "z/codegen/S390OutOfLineCodeSection.hpp"
#include "z/codegen/SystemLinkageLinux.hpp"
#include "z/codegen/SystemLinkagezOS.hpp"
#if J9_PROJECT_SPECIFIC
#include "z/codegen/S390Recompilation.hpp"
#include "z/codegen/S390Register.hpp"
#include "z/codegen/J9S390PrivateLinkage.hpp"
#endif
class TR_IGNode;
namespace TR { class DebugCounterBase; }
namespace TR { class S390PrivateLinkage; }
namespace TR { class SimpleRegex; }
#define OPT_DETAILS "O^O CODE GENERATION: "
bool compareNodes(TR::Node * node1, TR::Node * node2, TR::CodeGenerator *cg);
bool isMatchingStoreRestore(TR::Instruction *cursorLoad, TR::Instruction *cursorStore, TR::CodeGenerator *cg);
void handleLoadWithRegRanges(TR::Instruction *inst, TR::CodeGenerator *cg);
void
OMR::Z::CodeGenerator::preLowerTrees()
{
OMR::CodeGenerator::preLowerTrees();
_ialoadUnneeded.init();
}
void
OMR::Z::CodeGenerator::lowerTreesWalk(TR::Node * parent, TR::TreeTop * treeTop, vcount_t visitCount)
{
parent->setVisitCount(visitCount);
self()->lowerTreesPreChildrenVisit(parent, treeTop, visitCount);
// Go through the subtrees and lower any nodes that need to be lowered. This
// involves a call to the VM to replace the trees with other trees.
//
for (int32_t childCount = 0; childCount < parent->getNumChildren(); childCount++)
{
TR::Node *child = parent->getChild(childCount);
// If the subtree needs to be lowered, call the VM to lower it
//
if (child->getVisitCount() != visitCount)
{
self()->lowerTreesWalk(child, treeTop, visitCount);
self()->lowerTreeIfNeeded(child, childCount, parent, treeTop);
}
self()->checkIsUnneededIALoad(parent, child, treeTop);
}
self()->lowerTreesPostChildrenVisit(parent, treeTop, visitCount);
}
void
OMR::Z::CodeGenerator::checkIsUnneededIALoad(TR::Node *parent, TR::Node *node, TR::TreeTop *tt)
{
ListIterator<TR_Pair<TR::Node, int32_t> > listIter(&_ialoadUnneeded);
bool inList = false;
if (node->getOpCodeValue() == TR::aloadi)
{
TR_Pair<TR::Node, int32_t> *ptr;
for (ptr = listIter.getFirst(); ptr; ptr = listIter.getNext())
{
if (ptr->getKey() == node)
{
inList = true;
break;
}
}
if (inList)
{
uintptrj_t temp = (uintptrj_t)ptr->getValue();
int32_t updatedTemp = (int32_t)temp + 1;
ptr->setValue((int32_t*)(intptr_t)updatedTemp);
}
else // Not in list
{
// We only need to track future references to this iaload if refcount > 1
if (node->getReferenceCount() > 1)
{
uint32_t *temp ;
TR_Pair<TR::Node, int32_t> *newEntry = new (self()->trStackMemory()) TR_Pair<TR::Node, int32_t> (node, (int32_t *)1);
_ialoadUnneeded.add(newEntry);
}
node->setUnneededIALoad (true);
}
}
if (node->isUnneededIALoad())
{
if (parent->getOpCodeValue() == TR::ifacmpne || parent->getOpCodeValue() == TR::ificmpeq || parent->getOpCodeValue() == TR::ificmpne || parent->getOpCodeValue() == TR::ifacmpeq)
{
if (!parent->isNopableInlineGuard() || !self()->getSupportsVirtualGuardNOPing())
{
node->setUnneededIALoad(false);
}
else
{
TR_VirtualGuard * virtualGuard = self()->comp()->findVirtualGuardInfo(parent);
if (!parent->isHCRGuard() && !parent->isOSRGuard() && !self()->comp()->performVirtualGuardNOPing() &&
self()->comp()->isVirtualGuardNOPingRequired(virtualGuard) &&
virtualGuard->canBeRemoved())
{
node->setUnneededIALoad(false);
}
}
}
else if (parent->getOpCode().isNullCheck())
{
traceMsg(self()->comp(), "parent %p appears to be a nullcheck over node: %p\n", parent, node);
}
else if (node->getOpCodeValue() == TR::aloadi && !(node->isClassPointerConstant() || node->isMethodPointerConstant()) || parent->getOpCode().isNullCheck())
{
node->setUnneededIALoad(false);
}
else if ((parent->getOpCodeValue() != TR::ifacmpne || tt->getNode()->getOpCodeValue() != TR::ifacmpne))
{
node->setUnneededIALoad(false);
}
}
}
void
OMR::Z::CodeGenerator::lowerTreesPropagateBlockToNode(TR::Node *node)
{
#ifdef J9_PROJECT_SPECIFIC
if (!node->getType().isBCD())
#endif
{
OMR::CodeGenerator::lowerTreesPropagateBlockToNode(node);
}
}
void
OMR::Z::CodeGenerator::lowerTreeIfNeeded(
TR::Node *node,
int32_t childNumberOfNode,
TR::Node *parent,
TR::TreeTop *tt)
{
OMR::CodeGenerator::lowerTreeIfNeeded(node, childNumberOfNode, parent, tt);
// Z
if (TR::Compiler->target.cpu.isZ() &&
(node->getOpCode().isLoadVar() || node->getOpCode().isStore()) &&
node->getOpCode().isIndirect())
{
TR::Node* add1 = NULL;
TR::Node* add2 = NULL;
TR::Node* sub = NULL;
TR::Node* const1 = NULL;
TR::Node* const2 = NULL;
TR::Node* base = NULL;
TR::Node* index = NULL;
TR::ILOpCodes addOp, subOp, constOp;
if (TR::Compiler->target.is64Bit())
{
addOp = TR::aladd;
subOp = TR::lsub;
constOp = TR::lconst;
}
else
{
addOp = TR::aiadd;
subOp = TR::isub;
constOp = TR::iconst;
}
if (node->getFirstChild()->getOpCodeValue() == addOp)
add1 = node->getFirstChild();
if (add1 && add1->getFirstChild()->getOpCodeValue() == addOp)
{
add2 = add1->getFirstChild();
base = add2->getFirstChild();
}
if (add1 && add1->getSecondChild()->getOpCodeValue() == subOp)
sub = add1->getSecondChild();
if (add2 && add2->getSecondChild()->getOpCode().isLoadConst())
{
const1 = add2->getSecondChild();
index = add1->getSecondChild();
}
if (sub && sub->getSecondChild()->getOpCode().isLoadConst())
{
const2 = sub->getSecondChild();
index = sub->getFirstChild();
}
if (add1 && add2 && const1 == NULL && const2 == NULL)
{
if (add2->getFirstChild()->getOpCodeValue() == addOp)
{
index = add2->getSecondChild();
add2 = add2->getFirstChild();
base = add2->getFirstChild();
if (add2->getSecondChild()->getOpCode().isLoadConst())
const2 = add2->getSecondChild();
if (const2 && add1->getSecondChild()->getOpCode().isLoadConst())
const1 = add1->getSecondChild();
}
}
if (add1 && add2 && const1 && performTransformation(self()->comp(), "%sBase/index/displacement form addressing prep for node [%p]\n", OPT_DETAILS, node))
{
// traceMsg(comp(), "&&& Found pattern root=%llx add1=%llx add2=%llx const1=%llx sub=%llx const2=%llx\n", node, add1, add2, const1, sub, const2);
intptrj_t offset = 0;
if (TR::Compiler->target.is64Bit())
{
offset = const1->getLongInt();
if (const2)
if (sub)
offset -= const2->getLongInt();
else
offset += const2->getLongInt();
}
else
{
offset = const1->getInt();
if (const2)
if (sub)
offset -= const2->getInt();
else
offset += const2->getInt();
}
TR::Node* newAdd2 = TR::Node::create(addOp, 2, base, index);
TR::Node* newConst = TR::Node::create(constOp, 0);
if (TR::Compiler->target.is64Bit())
newConst->setLongInt(offset);
else
newConst->setInt(offset);
TR::Node* newAdd1 = TR::Node::create(addOp, 2, newAdd2, newConst);
node->setAndIncChild(0, newAdd1);
add1->recursivelyDecReferenceCount();
}
}
}
bool OMR::Z::CodeGenerator::supportsInliningOfIsInstance()
{
return !self()->comp()->getOption(TR_DisableInlineIsInstance);
}
bool OMR::Z::CodeGenerator::canTransformUnsafeCopyToArrayCopy()
{
static char *disableTran = feGetEnv("TR_DISABLEUnsafeCopy");
return (!disableTran && !self()->comp()->getCurrentMethod()->isJNINative() && !self()->comp()->getOption(TR_DisableArrayCopyOpts));
}
bool OMR::Z::CodeGenerator::supportsDirectIntegralLoadStoresFromLiteralPool()
{
return TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z10);
}
OMR::Z::CodeGenerator::CodeGenerator()
: OMR::CodeGenerator(),
_extentOfLitPool(-1),
_recompPatchInsnList(getTypedAllocator<TR::Instruction*>(self()->comp()->allocator())),
_constantHash(self()->comp()->allocator()),
_constantHashCur(_constantHash),
_constantList(getTypedAllocator<TR::S390ConstantDataSnippet*>(self()->comp()->allocator())),
_writableList(getTypedAllocator<TR::S390WritableDataSnippet*>(self()->comp()->allocator())),
_transientLongRegisters(self()->trMemory()),
_snippetDataList(getTypedAllocator<TR::S390ConstantDataSnippet*>(self()->comp()->allocator())),
_outOfLineCodeSectionList(getTypedAllocator<TR_S390OutOfLineCodeSection*>(self()->comp()->allocator())),
_returnTypeInfoInstruction(NULL),
_interfaceSnippetToPICsListHashTab(NULL),
_currentCheckNode(NULL),
_currentBCDCHKHandlerLabel(NULL),
_nodesToBeEvaluatedInRegPairs(self()->comp()->allocator()),
_ccInstruction(NULL),
_previouslyAssignedTo(self()->comp()->allocator("LocalRA")),
_firstTimeLiveOOLRegisterList(NULL),
_methodBegin(NULL),
_methodEnd(NULL),
_afterRA(false)
{
TR::Compilation *comp = self()->comp();
_cgFlags = 0;
// Initialize Linkage for Code Generator
self()->initializeLinkage();
_unlatchedRegisterList = (TR::RealRegister**)self()->trMemory()->allocateHeapMemory(sizeof(TR::RealRegister*)*(TR::RealRegister::NumRegisters));
_unlatchedRegisterList[0] = 0; // mark that list is empty
bool enableBranchPreload = comp->getOption(TR_EnableBranchPreload);
bool disableBranchPreload = comp->getOption(TR_DisableBranchPreload);
if (enableBranchPreload || (!disableBranchPreload && comp->isOptServer() && TR::Compiler->target.cpu.getSupportsArch(TR::CPU::zEC12)))
self()->setEnableBranchPreload();
else
self()->setDisableBranchPreload();
static bool bpp = (feGetEnv("TR_BPRP")!=NULL);
if ((enableBranchPreload && bpp) || (bpp && !disableBranchPreload && comp->isOptServer() && TR::Compiler->target.cpu.getSupportsArch(TR::CPU::zEC12)))
self()->setEnableBranchPreloadForCalls();
else
self()->setDisableBranchPreloadForCalls();
if (self()->supportsBranchPreloadForCalls())
{
_callsForPreloadList = new (self()->trHeapMemory()) TR::list<TR_BranchPreloadCallData*>(getTypedAllocator<TR_BranchPreloadCallData*>(comp->allocator()));
}
self()->setOnDemandLiteralPoolRun(true);
self()->setGlobalStaticBaseRegisterOn(false);
self()->setGlobalPrivateStaticBaseRegisterOn(false);
self()->setMultiplyIsDestructive();
self()->setIsOutOfLineHotPath(false);
self()->setUsesRegisterPairsForLongs();
self()->setSupportsDivCheck();
self()->setSupportsLoweringConstIDiv();
self()->setSupportsTestUnderMask();
// Initialize preprologue offset to be 8 bytes for bodyInfo / methodInfo
self()->setPreprologueOffset(8);
// Support divided by power of 2 logic in ldivSimplifier
self()->setSupportsLoweringConstLDivPower2();
//enable LM/STM for volatile longs in 32 bit
self()->setSupportsInlinedAtomicLongVolatiles();
self()->setSupportsConstantOffsetInAddressing();
static char * noVGNOP = feGetEnv("TR_NOVGNOP");
if (noVGNOP == NULL)
{
self()->setSupportsVirtualGuardNOPing();
}
if (!comp->getOption(TR_DisableArraySetOpts))
{
self()->setSupportsArraySet();
}
self()->setSupportsArrayCmp();
self()->setSupportsArrayCmpSign();
if (!comp->compileRelocatableCode())
{
self()->setSupportsArrayTranslateTRxx();
}
self()->setSupportsTestCharComparisonControl(); // TRXX instructions on Danu have mask to disable test char comparison.
self()->setSupportsReverseLoadAndStore();
self()->setSupportsSearchCharString(); // CISC Transformation into SRSTU loop - only on z9.
self()->setSupportsTranslateAndTestCharString(); // CISC Transformation into TRTE loop - only on z6.
if (TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z10))
{
self()->setSupportsTranslateAndTestCharString();
if (!comp->getOption(TR_DisableTraps) && TR::Compiler->vm.hasResumableTrapHandler(comp))
{
self()->setHasResumableTrapHandler();
}
}
else
{
comp->setOption(TR_DisableCompareAndBranchInstruction);
// No trap instructions available for z10 and below.
// Set disable traps so that the optimizations and codegen can avoid generating
// trap-specific nodes or instructions.
comp->setOption(TR_DisableTraps);
}
if (TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z196))
{
self()->setSupportsAtomicLoadAndAdd();
}
else
{
// Max min optimization uses the maxMinHelper evaluator which
// requires conditional loads that are not supported below z196
comp->setOption(TR_DisableMaxMinOptimization);
}
if (TR::Compiler->target.cpu.getSupportsArch(TR::CPU::zEC12))
{
self()->setSupportsZonedDFPConversions();
if (TR::Compiler->target.cpu.getSupportsTransactionalMemoryFacility() && !comp->getOption(TR_DisableTM))
self()->setSupportsTM();
}
if (TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z13) && !comp->getOption(TR_DisableArch11PackedToDFP))
self()->setSupportsFastPackedDFPConversions();
if (!TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z14))
{
comp->setOption(TR_DisableVectorBCD);
}
// Be pessimistic until we can prove we don't exit after doing code-generation
self()->setExitPointsInMethod(true);
#ifdef DEBUG
// Clear internal counters for internal profiling of
// register allocation
self()->clearTotalSpills();
self()->clearTotalRegisterXfers();
self()->clearTotalRegisterMoves();
#endif
// Set up vector register support for machine after zEC12.
// This should also happen before prepareForGRA
if(!(TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z13) && !comp->getOption(TR_DisableZ13)))
{
comp->setOption(TR_DisableZ13LoadAndMask);
comp->setOption(TR_DisableZ13LoadImmediateOnCond);
}
if (comp->getOption(TR_DisableSIMD))
{
comp->setOption(TR_DisableAutoSIMD);
comp->setOption(TR_DisableSIMDArrayCompare);
comp->setOption(TR_DisableSIMDArrayTranslate);
comp->setOption(TR_DisableSIMDUTF16BEEncoder);
comp->setOption(TR_DisableSIMDUTF16LEEncoder);
comp->setOption(TR_DisableSIMDStringHashCode);
comp->setOption(TR_DisableVectorRegGRA);
}
// This enables the tactical GRA
self()->setSupportsGlRegDeps();
self()->addSupportedLiveRegisterKind(TR_GPR);
self()->addSupportedLiveRegisterKind(TR_FPR);
self()->addSupportedLiveRegisterKind(TR_VRF);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(comp), TR_GPR);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(comp), TR_FPR);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(comp), TR_VRF);
self()->setSupportsPrimitiveArrayCopy();
self()->setSupportsReferenceArrayCopy();
self()->setSupportsPartialInlineOfMethodHooks();
self()->setSupportsInliningOfTypeCoersionMethods();
self()->setPerformsChecksExplicitly();
_numberBytesReadInaccessible = 4096;
_numberBytesWriteInaccessible = 4096;
// zLinux sTR requires this as well, otherwise cp00f054.C testcase fails in TR_FPStoreReloadElimination.
self()->setSupportsJavaFloatSemantics();
_localF2ISpill = NULL;
_localD2LSpill = NULL;
_nextAvailableBlockIndex = -1;
_currentBlockIndex = -1;
if (comp->getOptions()->getRegisterAssignmentTraceOption(TR_TraceRARegisterStates))
{
self()->setGPRegisterIterator(new (self()->trHeapMemory()) TR::RegisterIterator(self()->machine(), TR::RealRegister::FirstGPR, TR::RealRegister::LastAssignableGPR));
self()->setFPRegisterIterator(new (self()->trHeapMemory()) TR::RegisterIterator(self()->machine(), TR::RealRegister::FirstFPR, TR::RealRegister::LastFPR));
self()->setVRFRegisterIterator(new (self()->trHeapMemory()) TR::RegisterIterator(self()->machine(), TR::RealRegister::FirstVRF, TR::RealRegister::LastVRF));
}
if (!comp->getOption(TR_DisableTLHPrefetch) && !comp->compileRelocatableCode())
{
self()->setEnableTLHPrefetching();
}
_reusableTempSlot = NULL;
self()->freeReusableTempSlot();
self()->setSupportsProfiledInlining();
self()->getS390Linkage()->setParameterLinkageRegisterIndex(comp->getJittedMethodSymbol());
self()->getS390Linkage()->initS390RealRegisterLinkage();
self()->setAccessStaticsIndirectly(true);
}
bool
OMR::Z::CodeGenerator::getSupportsBitPermute()
{
return true;
}
bool OMR::Z::CodeGenerator::prepareForGRA()
{
bool enableVectorGRA = self()->getSupportsVectorRegisters() && !self()->comp()->getOption(TR_DisableVectorRegGRA);
if (!_globalRegisterTable)
{
self()->machine()->initializeGlobalRegisterTable();
self()->setGlobalRegisterTable(self()->machine()->getGlobalRegisterTable());
self()->setLastGlobalGPR(self()->machine()->getLastGlobalGPRRegisterNumber());
self()->setLast8BitGlobalGPR(self()->machine()->getLast8BitGlobalGPRRegisterNumber());
self()->setFirstGlobalFPR(self()->machine()->getFirstGlobalFPRRegisterNumber());
self()->setLastGlobalFPR(self()->machine()->getLastGlobalFPRRegisterNumber());
self()->setFirstGlobalVRF(self()->machine()->getFirstGlobalVRFRegisterNumber());
self()->setLastGlobalVRF(self()->machine()->getLastGlobalVRFRegisterNumber());
if (enableVectorGRA)
{
static char * traceVecGRN = feGetEnv("TR_traceVectorGRA");
if (traceVecGRN)
{
printf("Java func: %s func: %s\n", self()->comp()->getCurrentMethod()->nameChars(), __FUNCTION__);
printf("ff %d\t", self()->machine()->getFirstGlobalFPRRegisterNumber());
printf("lf %d\t", self()->machine()->getLastGlobalFPRRegisterNumber());
printf("fof %d\t", self()->machine()->getFirstOverlappedGlobalFPRRegisterNumber());
printf("lof %d\t", self()->machine()->getLastOverlappedGlobalFPRRegisterNumber());
printf("fv %d\t", self()->machine()->getFirstGlobalVRFRegisterNumber());
printf("lv %d\t", self()->machine()->getLastGlobalVRFRegisterNumber());
printf("fov %d\t", self()->machine()->getFirstOverlappedGlobalVRFRegisterNumber());
printf("lov %d\t", self()->machine()->getLastOverlappedGlobalVRFRegisterNumber());
printf("\n--------------------\n");
}
self()->setFirstOverlappedGlobalFPR(self()->machine()->getFirstOverlappedGlobalFPRRegisterNumber());
self()->setLastOverlappedGlobalFPR (self()->machine()->getLastOverlappedGlobalFPRRegisterNumber());
self()->setFirstOverlappedGlobalVRF(self()->machine()->getFirstOverlappedGlobalVRFRegisterNumber());
self()->setLastOverlappedGlobalVRF (self()->machine()->getLastOverlappedGlobalVRFRegisterNumber());
self()->setOverlapOffsetBetweenAliasedGRNs(self()->getFirstOverlappedGlobalVRF() - self()->getFirstOverlappedGlobalFPR());
}
self()->setSupportsGlRegDepOnFirstBlock();
self()->setConsiderAllAutosAsTacticalGlobalRegisterCandidates();
static char * disableLongGRAOn31Bit = feGetEnv("TR390LONGGRA31BIT");
// Only enable Long Globals on 64bit pltfrms
if (disableLongGRAOn31Bit)
{
self()->setDisableLongGRA();
}
// Initialize _globalGPRsPreservedAcrossCalls and _globalFPRsPreservedAcrossCalls
// We call init here because getNumberOfGlobal[FG]PRs() is initialized during the call to initialize() above.
//
_globalGPRsPreservedAcrossCalls.init(NUM_S390_GPR + NUM_S390_FPR, self()->trMemory());
_globalFPRsPreservedAcrossCalls.init(NUM_S390_GPR + NUM_S390_FPR, self()->trMemory());
TR_GlobalRegisterNumber grn;
for (grn = self()->getFirstGlobalGPR(); grn <= self()->getLastGlobalGPR(); grn++)
{
uint32_t globalReg = self()->getGlobalRegister(grn);
if (globalReg != -1 && self()->getS390Linkage()->getPreserved((TR::RealRegister::RegNum) globalReg))
{
_globalGPRsPreservedAcrossCalls.set(grn);
}
}
for (grn = self()->getFirstGlobalFPR(); grn <= self()->getLastGlobalFPR(); grn++)
{
uint32_t globalReg = self()->getGlobalRegister(grn);
if (globalReg != -1 && self()->getS390Linkage()->getPreserved((TR::RealRegister::RegNum) globalReg))
{
_globalFPRsPreservedAcrossCalls.set(grn);
}
}
TR::Linkage *linkage = self()->getS390Linkage();
if (!self()->comp()->getOption(TR_DisableRegisterPressureSimulation))
{
for (int32_t i = 0; i < TR_numSpillKinds; i++)
_globalRegisterBitVectors[i].init(self()->getNumberOfGlobalRegisters(), self()->trMemory());
for (grn=0; grn < self()->getNumberOfGlobalRegisters(); grn++)
{
TR::RealRegister::RegNum reg = (TR::RealRegister::RegNum)self()->getGlobalRegister(grn);
TR_ASSERT(reg != -1, "Register pressure simulator doesn't support gaps in the global register table; reg %d must be removed", grn);
if (self()->getFirstGlobalGPR() <= grn && grn <= self()->getLastGlobalGPR())
{
_globalRegisterBitVectors[ TR_gprSpill ].set(grn);
}
else if (self()->getFirstGlobalFPR() <= grn && grn <= self()->getLastGlobalFPR())
{
_globalRegisterBitVectors[TR_fprSpill].set(grn);
}
else if (self()->getFirstGlobalVRF() <= grn && grn <= self()->getLastGlobalVRF())
{
_globalRegisterBitVectors[TR_vrfSpill].set(grn);
}
if (!linkage->getPreserved(reg))
_globalRegisterBitVectors[ TR_volatileSpill ].set(grn);
if (linkage->getIntegerArgument(reg) || linkage->getFloatArgument(reg))
{
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
}
if (reg == linkage->getMethodMetaDataRegister())
_globalRegisterBitVectors[ TR_vmThreadSpill ].set(grn);
if (reg == linkage->getLitPoolRegister())
_globalRegisterBitVectors[ TR_litPoolSpill ].set(grn);
if (reg == linkage->getStaticBaseRegister() && self()->isGlobalStaticBaseRegisterOn())
_globalRegisterBitVectors[ TR_staticBaseSpill ].set(grn);
if (reg == TR::RealRegister::GPR0)
_globalRegisterBitVectors[ TR_gpr0Spill ].set(grn);
if (reg == TR::RealRegister::GPR1)
_globalRegisterBitVectors[ TR_gpr1Spill ].set(grn);
if (reg == TR::RealRegister::GPR2)
_globalRegisterBitVectors[ TR_gpr2Spill ].set(grn);
if (reg == TR::RealRegister::GPR3)
_globalRegisterBitVectors[ TR_gpr3Spill ].set(grn);
if (reg == TR::RealRegister::GPR4)
_globalRegisterBitVectors[ TR_gpr4Spill ].set(grn);
if (reg == TR::RealRegister::GPR5)
_globalRegisterBitVectors[ TR_gpr5Spill ].set(grn);
if (reg == TR::RealRegister::GPR6)
_globalRegisterBitVectors[ TR_gpr6Spill ].set(grn);
if (reg == TR::RealRegister::GPR7)
_globalRegisterBitVectors[ TR_gpr7Spill ].set(grn);
if (reg == TR::RealRegister::GPR8)
_globalRegisterBitVectors[ TR_gpr8Spill ].set(grn);
if (reg == TR::RealRegister::GPR9)
_globalRegisterBitVectors[ TR_gpr9Spill ].set(grn);
if (reg == TR::RealRegister::GPR10)
_globalRegisterBitVectors[ TR_gpr10Spill ].set(grn);
if (reg == TR::RealRegister::GPR11)
_globalRegisterBitVectors[ TR_gpr11Spill ].set(grn);
if (reg == TR::RealRegister::GPR12)
_globalRegisterBitVectors[ TR_gpr12Spill ].set(grn);
if (reg == TR::RealRegister::GPR13)
_globalRegisterBitVectors[ TR_gpr13Spill ].set(grn);
if (reg == TR::RealRegister::GPR14)
_globalRegisterBitVectors[ TR_gpr14Spill ].set(grn);
if (reg == TR::RealRegister::GPR15)
_globalRegisterBitVectors[ TR_gpr15Spill ].set(grn);
}
if ((grn = self()->machine()->getGlobalCAARegisterNumber()) != -1)
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
if ((grn = self()->machine()->getGlobalEnvironmentRegisterNumber()) != -1)
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
if ((grn = self()->machine()->getGlobalParentDSARegisterNumber()) != -1)
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
if ((grn = self()->machine()->getGlobalReturnAddressRegisterNumber()) != -1)
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
if ((grn = self()->machine()->getGlobalEntryPointRegisterNumber()) != -1)
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
}
return OMR::CodeGenerator::prepareForGRA();
}
else
{
return true;
}
}
TR::Linkage * OMR::Z::CodeGenerator::getS390Linkage() {return (self()->getLinkage());}
TR::S390PrivateLinkage * OMR::Z::CodeGenerator::getS390PrivateLinkage() {return TR::toS390PrivateLinkage(self()->getLinkage());}
TR::RealRegister * OMR::Z::CodeGenerator::getStackPointerRealRegister(TR::Symbol *symbol)
{
TR::Linkage *linkage = self()->getS390Linkage();
TR::RealRegister *spReg = linkage->getStackPointerRealRegister();
return spReg;
}
TR::RealRegister * OMR::Z::CodeGenerator::getEntryPointRealRegister()
{return self()->getS390Linkage()->getEntryPointRealRegister();}
TR::RealRegister * OMR::Z::CodeGenerator::getReturnAddressRealRegister()
{return self()->getS390Linkage()->getReturnAddressRealRegister();}
TR::RealRegister * OMR::Z::CodeGenerator::getLitPoolRealRegister()
{return self()->getS390Linkage()->getLitPoolRealRegister();}
TR::RealRegister::RegNum OMR::Z::CodeGenerator::getEntryPointRegister()
{return self()->getS390Linkage()->getEntryPointRegister();}
TR::RealRegister::RegNum OMR::Z::CodeGenerator::getReturnAddressRegister()
{return self()->getS390Linkage()->getReturnAddressRegister();}
TR::RealRegister * OMR::Z::CodeGenerator::getMethodMetaDataRealRegister()
{
return self()->getS390Linkage()->getMethodMetaDataRealRegister();
}
bool
OMR::Z::CodeGenerator::internalPointerSupportImplemented()
{
return true;
}
bool
OMR::Z::CodeGenerator::mulDecompositionCostIsJustified(int32_t numOfOperations, char bitPosition[], char operationType[], int64_t value)
{
bool trace = self()->comp()->getOptions()->getTraceSimplifier(TR_TraceMulDecomposition);
if (TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z196))
{
int32_t numCycles = 0;
numCycles = numOfOperations+1;
if (value & (int64_t) CONSTANT64(0x0000000000000001))
{
numCycles = numCycles-1;
}
if (trace)
if (numCycles <= 3)
traceMsg(self()->comp(), "MulDecomp cost is justified\n");
else
traceMsg(self()->comp(), "MulDecomp cost is too high. numCycle=%i(max:3)\n", numCycles);
return numCycles <= 3;
}
else if (TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z10))
{
int32_t numCycles = 0;
numCycles = numOfOperations+1;
if (value & (int64_t) CONSTANT64(0x0000000000000001))
{
numCycles = numCycles-1;
}
if (trace)
if (numCycles <= 9)
traceMsg(self()->comp(), "MulDecomp cost is justified\n");
else
traceMsg(self()->comp(), "MulDecomp cost is too high. numCycle=%i(max:10)\n", numCycles);
return numCycles <= 9;
}
else
{
if (value > MAX_IMMEDIATE_VAL || value < MIN_IMMEDIATE_VAL)
{
// If more than 16 bits, then justify the shift / subtract
return OMR::CodeGenerator::mulDecompositionCostIsJustified(numOfOperations, bitPosition, operationType, value);
}
return false;
}
}
/**
* BCD types and aggregates of some eizes are not going to end up in machine registers so do not
* consider them for global register allocation
*/
bool OMR::Z::CodeGenerator::considerAggregateSizeForGRA(int32_t size)
{
switch (size)
{
case 1:
case 2:
case 4:
case 8: return true;
default: return false;
}
}
bool
OMR::Z::CodeGenerator::considerTypeForGRA(TR::Node *node)
{
#ifdef J9_PROJECT_SPECIFIC
if (node->getType().isBCD())
return false;
#endif
if (node->getDataType() == TR::Aggregate)
return self()->considerAggregateSizeForGRA(0);
else if (node->getSymbol()&& node->getSymbol()->isMethodMetaData())
return !node->getSymbol()->getType().isFloatingPoint();
else
return true;
}
bool
OMR::Z::CodeGenerator::considerTypeForGRA(TR::DataType dt)
{
if (
#ifdef J9_PROJECT_SPECIFIC
dt.isBCD() ||
#endif
dt == TR::Aggregate)
return false;
else
return true;
}
bool
OMR::Z::CodeGenerator::considerTypeForGRA(TR::SymbolReference *symRef)
{
if (symRef &&
symRef->getSymbol())
{
#ifdef J9_PROJECT_SPECIFIC
if (symRef->getSymbol()->getDataType().isBCD())
return false;
else
#endif
if (symRef->getSymbol()->getDataType() == TR::Aggregate)
return self()->considerAggregateSizeForGRA(symRef->getSymbol()->getSize());
else
return true;
}
else
{
return true;
}
}
void
OMR::Z::CodeGenerator::enableLiteralPoolRegisterForGRA ()
{
if (self()->comp()->getOption(TR_DisableRegisterPressureSimulation))
{
self()->machine()->releaseLiteralPoolRegister();
static char * noGraFIX= feGetEnv("TR_NOGRAFIX");
if (!noGraFIX)
{
_globalGPRsPreservedAcrossCalls.set(GLOBAL_REG_FOR_LITPOOL);
}
}
}
bool
OMR::Z::CodeGenerator::canUseImmedInstruction( int64_t value )
{
if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL)
return true;
else
return false;
}
bool
OMR::Z::CodeGenerator::isAddMemoryUpdate(TR::Node * node, TR::Node * valueChild)
{
static char * disableASI = feGetEnv("TR_DISABLEASI");
if (TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z10))
{
if (!disableASI && self()->isMemoryUpdate(node) && valueChild->getSecondChild()->getOpCode().isLoadConst())
{
if (valueChild->getOpCodeValue() == TR::iadd || valueChild->getOpCodeValue() == TR::isub)
{
int32_t value = valueChild->getSecondChild()->getInt();
if (value < (int32_t) 0x7F && value > (int32_t) 0xFFFFFF80)
{
return true;
}
}