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BinaryEvaluator.cpp
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BinaryEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <math.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/StorageInfo.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/AliasSetInterface.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "ras/Debug.hpp"
#include "ras/Delimiter.hpp"
#include "runtime/Runtime.hpp"
#include "z/codegen/BinaryAnalyser.hpp"
#include "z/codegen/BinaryCommutativeAnalyser.hpp"
#include "z/codegen/S390Evaluator.hpp"
#include "z/codegen/S390GenerateInstructions.hpp"
#include "z/codegen/S390Instruction.hpp"
/**
* lnegFor32bit - 32 bit code generation to negate a long integer
*/
TR::RegisterPair * lnegFor32Bit(TR::Node * node, TR::CodeGenerator * cg, TR::RegisterPair * targetRegisterPair, TR::RegisterDependencyConditions * dep = 0)
{
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol(cg);
TR::LabelSymbol * cFlowRegionEnd = generateLabelSymbol(cg);
TR::RegisterDependencyConditions * localDeps = NULL;
// If deps are passed in, we assume that there is a wider scoped set of deps that are
// handled by the caller. If the deps are null, we must handle deps for internal control
// flow ourselves here.
//
if (!dep)
{
localDeps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
localDeps->addPostCondition(targetRegisterPair->getHighOrder(), TR::RealRegister::AssignAny);
}
else
{
dep->addPostConditionIfNotAlreadyInserted(targetRegisterPair->getHighOrder(), TR::RealRegister::AssignAny);
}
// Do complements on reg pair
generateRRInstruction(cg, TR::InstOpCode::LCR, node, targetRegisterPair->getHighOrder(), targetRegisterPair->getHighOrder());
generateRRInstruction(cg, TR::InstOpCode::LCR, node, targetRegisterPair->getLowOrder(), targetRegisterPair->getLowOrder());
// Check to see if we need to propagate an overflow bit from LS int to MS int.
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BE, node, cFlowRegionEnd);
// Increment MS int due to overflow in LS int
generateRIInstruction(cg, TR::InstOpCode::AHI, node, targetRegisterPair->getHighOrder(), -1);
// Not equal, straight through
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionEnd, localDeps);
cFlowRegionEnd->setEndInternalControlFlow();
return targetRegisterPair;
}
/**
* lnegFor128Bit - negate a 128bit integer in 64-bit register pairs
*/
TR::RegisterPair * lnegFor128Bit(TR::Node * node, TR::CodeGenerator * cg, TR::RegisterPair * targetRegisterPair, TR::RegisterDependencyConditions * dep = 0)
{
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol(cg);
TR::LabelSymbol * cFlowRegionEnd = generateLabelSymbol(cg);
TR::RegisterDependencyConditions * localDeps = NULL;
// If deps are passed in, we assume that there is a wider scoped set of deps that are
// handled by the caller. If the deps are null, we must handle deps for internal control
// flow ourselves here.
//
if (!dep)
{
localDeps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
localDeps->addPostCondition(targetRegisterPair->getHighOrder(), TR::RealRegister::AssignAny);
}
else
{
dep->addPostConditionIfNotAlreadyInserted(targetRegisterPair->getHighOrder(), TR::RealRegister::AssignAny);
}
// Do complements on reg pair
generateRRInstruction(cg, TR::InstOpCode::LCGR, node, targetRegisterPair->getHighOrder(), targetRegisterPair->getHighOrder());
generateRRInstruction(cg, TR::InstOpCode::LCGR, node, targetRegisterPair->getLowOrder(), targetRegisterPair->getLowOrder());
// Check to see if we need to propagate an overflow bit from low word long to high word long.
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BE, node, cFlowRegionEnd);
// Subtract 1 from high word that was added in first LCGR if low word is not 0, i.e.
generateRIInstruction(cg, TR::InstOpCode::AGHI, node, targetRegisterPair->getHighOrder(), -1);
// Not equal, straight through
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionEnd, localDeps);
cFlowRegionEnd->setEndInternalControlFlow();
return targetRegisterPair;
}
/**
* laddConst - adds the long value in targetRegisterPair with the constant value
*/
inline TR::RegisterPair *
laddConst(TR::Node * node, TR::CodeGenerator * cg, TR::RegisterPair * targetRegisterPair, int64_t value, TR::RegisterDependencyConditions * deps)
{
TR::Compilation *comp = cg->comp();
int32_t h_value = (int32_t)(value>>32);
int32_t l_value = (int32_t)value;
TR::Register * lowOrder = targetRegisterPair->getLowOrder();
TR::Register * highOrder = targetRegisterPair->getHighOrder();
if (performTransformation(comp, "O^O Use AL/ALC to perform long add.\n"))
{ // wrong carry bit to be set
if ( l_value != 0 )
{
// tempReg is used to hold the immediate on GoldenEagle or better.
// On other hardware, we use highOrder
//
TR::Register * tempReg = cg->allocateRegister();
generateS390ImmOp(cg, TR::InstOpCode::AL, node, tempReg, lowOrder, l_value, deps);
generateS390ImmOp(cg, TR::InstOpCode::ALC, node, tempReg, highOrder, h_value, deps);
if(deps) deps->addPostCondition(tempReg, TR::RealRegister::AssignAny);
cg->stopUsingRegister(tempReg);
}
else
{
generateS390ImmOp(cg, TR::InstOpCode::A, node, highOrder, highOrder, h_value);
}
}
else
{
// Add high value
generateS390ImmOp(cg, TR::InstOpCode::A, node, highOrder, highOrder, h_value);
// Add low value
if ( l_value != 0 )
{
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol(cg);
TR::LabelSymbol * cFlowRegionEnd = generateLabelSymbol(cg);
TR::RegisterDependencyConditions * dependencies = NULL;
// tempReg is used to hold the immediate on GoldenEagle or better.
// On other hardware, we use highOrder
//
TR::Register * tempReg = cg->allocateRegister();
dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 2, cg);
dependencies->addPostCondition(tempReg, TR::RealRegister::AssignAny);
dependencies->addPostCondition(highOrder, TR::RealRegister::AssignAny);
generateS390ImmOp(cg, TR::InstOpCode::AL, node, tempReg, lowOrder, l_value);
// Check for overflow in LS(h_value) int. If overflow, increment MS(l_value) int.
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_MASK12, node, cFlowRegionEnd);
// Increment MS int due to overflow in LS int
generateRIInstruction(cg, TR::InstOpCode::AHI, node, highOrder, 1);
cg->stopUsingRegister(tempReg);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionEnd, dependencies);
cFlowRegionEnd->setEndInternalControlFlow();
}
}
return targetRegisterPair;
}
static bool
genNullTestForCompressedPointers(TR::Node *node, TR::CodeGenerator *cg, TR::Register *targetRegister, TR::LabelSymbol * &skipAdd)
{
TR::Compilation *comp = cg->comp();
bool hasCompressedPointers = false;
if (cg->comp()->target().is64Bit() &&
comp->useCompressedPointers() &&
node->containsCompressionSequence() /* &&
!node->isNonZero() */ )
{
hasCompressedPointers = true;
// TR::ILOpCodes loadOp = comp->il.opCodeForIndirectLoad(TR_SInt32);
TR::Node *n = node;
bool isNonZero = false;
if (n->isNonZero())
isNonZero = true;
if ((n->getOpCodeValue() == TR::lshl) ||
(n->getOpCodeValue() == TR::lushr))
n = n->getFirstChild();
TR::Node *addOrSubNode = NULL;
if (n->getOpCodeValue() == TR::ladd)
{
addOrSubNode = n;
if (n->getFirstChild()->isNonZero())
isNonZero = true;
if (n->getFirstChild()->getOpCodeValue() == TR::iu2l || n->getFirstChild()->getOpCode().isShift())
{
if (n->getFirstChild()->getFirstChild()->isNonZero())
isNonZero = true;
}
}
else if (n->getOpCodeValue() == TR::lsub)
{
addOrSubNode = n;
if (n->getFirstChild()->isNonZero())
isNonZero = true;
if (n->getFirstChild()->getOpCodeValue() == TR::a2l || n->getFirstChild()->getOpCode().isShift())
{
if (n->getFirstChild()->getFirstChild()->isNonNull())
isNonZero = true;
}
}
if (!isNonZero)
{
TR::Instruction *current = cg->getAppendInstruction();
TR_ASSERT( current != NULL, "Could not get current instruction");
if (!targetRegister)
{
targetRegister = cg->gprClobberEvaluate(addOrSubNode->getFirstChild());
//targetRegister->incReferenceCount();
//node->setRegister(targetRegister);
}
skipAdd = generateLabelSymbol(cg);
skipAdd->setEndInternalControlFlow();
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol( cg);
if (addOrSubNode->getFirstChild()->getOpCode().isShift() && addOrSubNode->getFirstChild()->getRegister())
{
TR::Register* r = addOrSubNode->getFirstChild()->getRegister();
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
generateS390CompareAndBranchInstruction(cg, TR::InstOpCode::getCmpOpCode(), node, r, 0, TR::InstOpCode::COND_BE, skipAdd);
}
else
{
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
generateS390CompareAndBranchInstruction(cg, TR::InstOpCode::getCmpOpCode(), node, targetRegister, 0, TR::InstOpCode::COND_BE, skipAdd);
}
cFlowRegionStart->setStartInternalControlFlow();
}
}
return hasCompressedPointers;
}
/**
* laddHelper64- add 2 long integers for 64bit platform
*/
TR::Register *
laddHelper64(TR::Node * node, TR::CodeGenerator * cg)
{
TR::Compilation *comp = cg->comp();
TR::Node * secondChild = node->getSecondChild();
TR::Node * firstChild = node->getFirstChild();
TR::Register * targetRegister = NULL;
TR::LabelSymbol *skipAdd = NULL;
TR::Node *curTreeNode = cg->getCurrentEvaluationTreeTop()->getNode();
bool bumpedRefCount = false;
bool isCompressionSequence = cg->comp()->target().is64Bit() &&
comp->useCompressedPointers() &&
node->containsCompressionSequence();
if (NEED_CC(node) || (node->getOpCodeValue() == TR::luaddc))
{
TR_ASSERT( !isCompressionSequence, "CC computation not supported with compression sequence.\n");
TR_ASSERT(node->getOpCodeValue() == TR::ladd || node->getOpCodeValue() == TR::luaddc,
"CC computation not supported for this node %p\n", node);
// we need the carry from integerAddAnalyser for the CC sequence, thus we use logical add instead of add
// we assume that the analyser will use the opcodes provided and does not generate alternative instructions
// which do not produce a carry.
TR_S390BinaryCommutativeAnalyser(cg).integerAddAnalyser(node, TR::InstOpCode::ALGR, TR::InstOpCode::ALG, TR::InstOpCode::LGR);
targetRegister = node->getRegister();
return targetRegister;
}
if (isCompressionSequence &&
curTreeNode->getOpCode().isNullCheck() &&
(curTreeNode->getNullCheckReference()->getOpCodeValue() == TR::l2a) &&
(curTreeNode->getNullCheckReference()->getFirstChild() == node) )
{
bumpedRefCount = true;
firstChild->incReferenceCount();
}
if (isCompressionSequence && !firstChild->isNonZero())
{
targetRegister = cg->gprClobberEvaluate(firstChild);
}
TR::Register *secondRegister = NULL;
if (isCompressionSequence)
{
if (isCompressionSequence &&
(secondChild->getReferenceCount() > 1))
secondRegister = cg->evaluate(secondChild);
}
bool hasCompressedPointers = genNullTestForCompressedPointers(node, cg, targetRegister, skipAdd);
if (hasCompressedPointers &&
((secondChild->getOpCodeValue() != TR::lconst) ||
(secondChild->getRegister() != NULL)))
{
secondRegister = cg->evaluate(secondChild);
bool addDepForCompressedValue = false;
TR::MemoryReference * laddMR = generateS390MemoryReference(cg);
laddMR->populateMemoryReference(firstChild, cg);
laddMR->populateMemoryReference(secondChild, cg);
if (!targetRegister)
targetRegister = cg->allocateRegister();
if (firstChild->getReferenceCount() > 1 &&
firstChild->getRegister() &&
targetRegister != firstChild->getRegister())
addDepForCompressedValue = true;
generateRXInstruction(cg, TR::InstOpCode::LA, node, targetRegister, laddMR);
node->setRegister(targetRegister);
if (skipAdd)
{
TR::RegisterDependencyConditions *conditions;
conditions = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 2, cg);
conditions->addPostCondition(targetRegister, TR::RealRegister::AssignAny);
conditions->addPostCondition(secondRegister, TR::RealRegister::AssignAny);
if (addDepForCompressedValue)
conditions->addPostCondition(firstChild->getRegister(), TR::RealRegister::AssignAny);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, skipAdd, conditions);
}
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
}
else if (secondChild->getOpCodeValue() == TR::lconst && secondChild->getRegister() == NULL)
{
int64_t long_value = secondChild->getLongInt();
if (!targetRegister)
{
targetRegister = cg->gprClobberEvaluate(firstChild);
}
generateS390ImmOp(cg, TR::InstOpCode::AG, node, targetRegister, targetRegister, long_value);
node->setRegister(targetRegister);
if (hasCompressedPointers && skipAdd)
{
TR::RegisterDependencyConditions *conditions = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
conditions->addPostCondition(targetRegister, TR::RealRegister::AssignAny);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, skipAdd, conditions);
}
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
}
else
{
TR_S390BinaryCommutativeAnalyser temp(cg);
temp.integerAddAnalyser(node, TR::InstOpCode::AGR, TR::InstOpCode::AG, TR::InstOpCode::LGR);
targetRegister = node->getRegister();
if (hasCompressedPointers && skipAdd)
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, skipAdd);
}
if (bumpedRefCount)
firstChild->decReferenceCount();
return targetRegister;
}
/**
* Check if opcode does not affect AGI
*/
static bool noAGI(TR::InstOpCode & op)
{
return (op.isStore() || op.isLoad() ||op.isBranchOp() ||
op.getOpCodeValue() == TR::InstOpCode::CHI||
op.getOpCodeValue() == TR::InstOpCode::CLR||
op.getOpCodeValue() == TR::InstOpCode::CLGR||
op.getOpCodeValue() == TR::InstOpCode::CHI||
op.getOpCodeValue() == TR::InstOpCode::CGHI);
}
/**
* Search backwards looking for any preceeding definition of the specified registers.
* Look backwards iat at most searchLimit instructions.
* @return Defining instruction if found, NULL if none found
*/
static TR::Instruction *
findPreviousAGIDef(TR::Instruction* prev,uint32_t searchLimit,TR::Register *useA, TR::Compilation * comp)
{
bool trace=false;
static char * skipit = feGetEnv("TR_NOLAYOPT");
if(skipit) return prev;
TR::Instruction *curInsn = prev;
TR_ASSERT(useA ,"null\n");
TR_ASSERT(prev,"prev is null\n");
if(trace)traceMsg(comp, "in find at %p, looking for %p for %d\n",prev,useA,searchLimit);
while(searchLimit-- && curInsn)
{
if(trace)traceMsg(comp, "Looking at %p %d\n",curInsn,searchLimit);
TR::InstOpCode op = curInsn->getOpCode();
if(op.isAdmin() || op.isLabel())
{
++searchLimit;//skip this guy
}
else if(!op.hasBypass() && !noAGI(op) &&
(useA && curInsn->defsRegister(useA)))
{
if(trace)traceMsg(comp, "Def found:%p\n",curInsn);
return curInsn;
}
curInsn = curInsn->getPrev();
}
//traceMsg(comp, "none found\n");
return NULL;
}
/**
* Generic addition of 32bits
* Handles all int types (byte,char,short, and int)
*/
TR::Register *
generic32BitAddEvaluator(TR::Node * node, TR::CodeGenerator * cg)
{
TR::Compilation *comp = cg->comp();
TR::Register * targetRegister = NULL;
TR::Node * secondChild = node->getSecondChild();
TR::Node * firstChild = node->getFirstChild();
if (secondChild->getOpCode().isLoadConst())
{
rcount_t refCnt = firstChild->getReferenceCount();
int32_t value;
switch (secondChild->getDataType())
{
case TR::Int8:
{
value = (int32_t) secondChild->getByte();
break;
}
case TR::Int16:
{
value = (int32_t) secondChild->getShortInt();
break;
}
case TR::Int32:
{
value = secondChild->getInt();
break;
}
default:
TR_ASSERT_FATAL(false, "Unexpected data type (%s) in generic32BitAddEvaluator", secondChild->getDataType().toString());
break;
}
int32_t delay = cg->machine()->getAGIDelay();
if (refCnt> 1)
{
--delay;
}
delay = 2 * delay; // dual issue
// AHIK available on z196
bool useAHIK = false;
// If negative or large enough range we must use LAY. LA has more restrictions.
bool useLA = cg->comp()->target().is64Bit() && node->isNonNegative()
&& ((value < MAXLONGDISP && value > MINLONGDISP) || (value >= 0 && value <= MAXDISP));
TR::Register * childTargetReg = cg->evaluate(firstChild);
bool canClobberReg = cg->canClobberNodesRegister(firstChild);
if (!canClobberReg)
{
// Make sure all reg props are correctly propagated
//
targetRegister = cg->allocateClobberableRegister(childTargetReg);
}
else
{
targetRegister = childTargetReg;
}
if (!findPreviousAGIDef(cg->getAppendInstruction(), delay, childTargetReg, comp))
{
useLA = false;
}
if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z196))
{
if (!canClobberReg && (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL))
{
useAHIK = true;
}
}
if (useAHIK)
{
generateRIEInstruction(cg, TR::InstOpCode::AHIK, node, targetRegister, childTargetReg, value);
}
else if (useLA && performTransformation(comp, "O^O Use LA/LAY instead of AHI for %p.\n",node))
{
TR::MemoryReference * memRef = generateS390MemoryReference(childTargetReg, value, cg);
generateRXInstruction(cg, TR::InstOpCode::LA, node, targetRegister, memRef);
}
else
{
if (!canClobberReg)
{
generateRRInstruction(cg, TR::InstOpCode::getLoadRegOpCode(), node, targetRegister, childTargetReg);
}
generateS390ImmOp(cg, TR::InstOpCode::A, node, targetRegister, targetRegister, value);
}
node->setRegister(targetRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
}
else
{
TR_S390BinaryCommutativeAnalyser temp(cg);
TR::DataType type = node->getDataType();
temp.integerAddAnalyser(node, TR::InstOpCode::AR, type == TR::Int16 ? TR::InstOpCode::AH : TR::InstOpCode::A, TR::InstOpCode::LR);
targetRegister = node->getRegister();
}
return targetRegister;
}
/**
* Generic subtraction of 32bits
* This generic subtrac evaluator is invoked from different evaluator functions and handles all subtract types shorter than an int
* (i.e. byte-bsub, short-ssub, and int-isub)
*
* It does not handle long type.
*/
inline TR::Register *
generic32BitSubEvaluator(TR::Node * node, TR::CodeGenerator * cg)
{
TR::Register * targetRegister = NULL;
TR::Node * secondChild = node->getSecondChild();
if (secondChild->getOpCode().isLoadConst())
{
TR::Node * firstChild = node->getFirstChild();
int32_t value;
switch (secondChild->getDataType())
{
case TR::Int8:
{
value = (int32_t) secondChild->getByte();
break;
}
case TR::Int16:
{
value = (int32_t) secondChild->getShortInt();
break;
}
case TR::Int32:
{
value = secondChild->getInt();
break;
}
default:
TR_ASSERT_FATAL(false, "Unexpected data type (%s) in generic32BitSubEvaluator", secondChild->getDataType().toString());
break;
}
if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z196) &&
firstChild->getRegister() && !cg->canClobberNodesRegister(firstChild) &&
((-value) >= MIN_IMMEDIATE_VAL && (-value) <= MAX_IMMEDIATE_VAL))
{
TR::Register * sourceRegister = cg->evaluate(firstChild);
targetRegister = cg->allocateClobberableRegister(sourceRegister);
generateRIEInstruction(cg, TR::InstOpCode::AHIK, node, targetRegister, sourceRegister, -value);
}
else
{
targetRegister = cg->gprClobberEvaluate(firstChild);
generateS390ImmOp(cg, TR::InstOpCode::A, node, targetRegister, targetRegister, -value);
}
node->setRegister(targetRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
}
else // The second child of the sub node isn't a loadConstant type.
{
TR_S390BinaryAnalyser temp(cg);
TR::DataType type = node->getDataType();
temp.intBinaryAnalyser(node, TR::InstOpCode::SR, type == TR::Int16 ? TR::InstOpCode::SH : TR::InstOpCode::S);
targetRegister = node->getRegister();
}
return targetRegister;
}
//////////////////////////////////////////////////////////////////////////////////
#define DIVISION true
#define REMAINDER false
/**
* Generate code for lDiv or lRem for 64bit platforms
* If isDivision = true we return the quotient register.
* = false we return the remainder register.
* algorithm is the same as 32bit iDivRemGenericEvaluator() except the opcodes
*/
inline TR::Register *
lDivRemGenericEvaluator64(TR::Node * node, TR::CodeGenerator * cg, bool isDivision)
{
TR::LabelSymbol * doDiv = generateLabelSymbol(cg);
TR::LabelSymbol * skipDiv = NULL;
TR::Node * firstChild = node->getFirstChild();
TR::Node * secondChild = node->getSecondChild();
int32_t shiftAmnt;
// A/A, return 1 (div) or 0 (rem).
if (firstChild == secondChild)
{
TR::Register * sourceRegister = cg->evaluate(firstChild);
TR::Register * returnRegister = cg->allocateRegister();
int32_t retValue = 0; // default REM
if (isDivision)
{
retValue = 1;
}
generateRIInstruction(cg, TR::InstOpCode::LGHI, node, returnRegister, retValue);
node->setRegister(returnRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return returnRegister;
}
// Constant denoninator:
// - unsigned case: handle subset of cases (1, 2**x)
// - signed case: all cases
bool isUnsigned = node->getOpCode().isUnsigned();
bool isConstDenominator = secondChild->getOpCode().isLoadConst();
bool handleConstDenominator = isConstDenominator;
if (isUnsigned && isConstDenominator)
{
int64_t denominator = secondChild->getLongInt();
handleConstDenominator = (denominator == 1) ||
// use denoninator > 0 test to bypass the code
(denominator > 0 && TR::TreeEvaluator::checkPositiveOrNegativePowerOfTwo(denominator) && isDivision);
}
if (handleConstDenominator)
{
int64_t denominator = secondChild->getLongInt();
//case A/-1 Q=-A, R=0
if (denominator == -1)
{
TR::Register * firstRegister = cg->gprClobberEvaluate(firstChild);
if (!isDivision) //remainder
{
generateLoad32BitConstant(cg, node, 0, firstRegister, true);
}
else
{
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol(cg);
TR::LabelSymbol * cFlowRegionEnd = generateLabelSymbol(cg);
TR::LabelSymbol * doDiv = generateLabelSymbol(cg);
//special case, need to check if dividend is 0x8000000000000000 - but need to check it in 2 steps
generateS390ImmOp(cg, TR::InstOpCode::CG, node, firstRegister, firstRegister, (int64_t) CONSTANT64(0x8000000000000000));
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BE, node, cFlowRegionEnd);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, doDiv);
// Do complements on reg
generateRRInstruction(cg, TR::InstOpCode::LCGR, node, firstRegister, firstRegister);
TR::RegisterDependencyConditions *deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
deps->addPostCondition(firstRegister, TR::RealRegister::AssignAny);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionEnd, deps);
cFlowRegionEnd->setEndInternalControlFlow();
}
node->setRegister(firstRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return firstRegister;
}
//case A/1 Q=A, R=0
else if (denominator == 1)
{
TR::Register * firstRegister = cg->gprClobberEvaluate(firstChild);
if (!isDivision) //remainder
{
generateLoad32BitConstant(cg, node, 0, firstRegister, true);
}
node->setRegister(firstRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return firstRegister;
}
//case A/(+-)2^x - division is done using shifts
else if ((shiftAmnt = TR::TreeEvaluator::checkPositiveOrNegativePowerOfTwo(denominator)) > 0)
{
TR::Register * firstRegister = NULL;
int64_t absValueOfDenominator = denominator>0 ? denominator : -denominator;
if (isDivision)
{
firstRegister = cg->gprClobberEvaluate(firstChild);
// This adjustment only applies to signed division as we are effectively trying to skirt the sign bit during
// the shift operation below
if (!isUnsigned && !firstChild->isNonNegative())
{
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol(cg);
TR::LabelSymbol * skipSet = generateLabelSymbol(cg);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateS390CompareAndBranchInstruction(cg, TR::InstOpCode::CG, node, firstRegister, 0,TR::InstOpCode::COND_BNL, skipSet);
//adjustment to dividend if dividend is negative
TR::RegisterDependencyConditions *deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 2, cg);
deps->addPostCondition(firstRegister, TR::RealRegister::AssignAny);
generateS390ImmOp(cg, TR::InstOpCode::AG, node, firstRegister, firstRegister, absValueOfDenominator-1, deps);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, skipSet, deps);
skipSet->setEndInternalControlFlow();
}
//divide
if (isUnsigned)
generateRSInstruction(cg, TR::InstOpCode::SRLG, node, firstRegister, firstRegister, shiftAmnt );
else
generateRSInstruction(cg, TR::InstOpCode::SRAG, node, firstRegister, firstRegister, shiftAmnt );
//fix sign of quotient if necessary
if (denominator < 0)
generateRRInstruction(cg, TR::InstOpCode::LCGR, node, firstRegister, firstRegister);
}
else //remainder
{
firstRegister = cg->gprClobberEvaluate(firstChild);
TR::LabelSymbol * done = generateLabelSymbol(cg);
TR::RegisterDependencyConditions *deps = NULL;
// This adjustment only applies to signed division as we are effectively trying to skirt the sign bit during
// the shift operation below
if (!isUnsigned && !firstChild->isNonNegative())
{
TR::Register * tempRegister1 = cg->allocateRegister();
TR::Register * tempRegister2 = cg->allocateRegister();
generateRSInstruction(cg, TR::InstOpCode::SRAG, node, tempRegister2, firstRegister, 63);
generateRRInstruction(cg, TR::InstOpCode::LGR, node, tempRegister1, firstRegister);
generateRILInstruction(cg, TR::InstOpCode::NIHF, node, tempRegister2, static_cast<int32_t>((absValueOfDenominator-1)>>32) );
generateRILInstruction(cg, TR::InstOpCode::NILF, node, tempRegister2, static_cast<int32_t>(absValueOfDenominator-1));
generateRRInstruction(cg, TR::InstOpCode::AGR, node, firstRegister, tempRegister2);
if (denominator != static_cast<int32_t>(absValueOfDenominator))
generateRILInstruction(cg, TR::InstOpCode::NIHF, node, firstRegister, static_cast<int32_t>(( CONSTANT64(0xFFFFFFFFFFFFFFFF) - absValueOfDenominator +1)>>32));
generateRILInstruction(cg, TR::InstOpCode::NILF, node, firstRegister, static_cast<int32_t>( CONSTANT64(0xFFFFFFFFFFFFFFFF) - absValueOfDenominator +1));
generateRRInstruction(cg, TR::InstOpCode::SGR, node, tempRegister1, firstRegister);
generateRRInstruction(cg, TR::InstOpCode::LGR, node, firstRegister, tempRegister1);
cg->stopUsingRegister(tempRegister1);
cg->stopUsingRegister(tempRegister2);
}
else
{
generateShiftThenKeepSelected64Bit(node, cg, firstRegister, firstRegister, 64-shiftAmnt, 63, 0);
}
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, done, deps);
}
node->setRegister(firstRegister);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return firstRegister;
}
}
// DSGR R1,R2 & DSG R1,D(Rx,Rb)
// R1 represents a reg pair (eve,odd)=(r1,r1+1)
// The divisor goes in R1+1
// After the op is executed,
// R1 -> Remainder
// R1+1 -> Quotient
//
// Note: D and DR require that R1=0 before executing the division
// is this requirement true for DSGR or DSG? -- not mentioned in POP
uint8_t numPostConditions = 5;
bool doConditionalRemainder = false;
TR::Register * sourceRegister = cg->evaluate(secondChild);
TR::Register *remRegister = NULL;
TR::Register *quoRegister = NULL;
if (doConditionalRemainder)
{
numPostConditions++; // for sourceRegister (the divisor)
remRegister = cg->gprClobberEvaluate(firstChild);
quoRegister = cg->allocateRegister();
}
else
{
remRegister = cg->allocateRegister();
quoRegister = cg->gprClobberEvaluate(firstChild);
}
// Choose return register based on isDivision flag
TR::Register * returnRegister = isDivision ? quoRegister : remRegister;
// Setup dependency for reg pairs
TR::RegisterPair * targetRegisterPair = cg->allocateConsecutiveRegisterPair(quoRegister, remRegister);
TR::RegisterDependencyConditions * dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, numPostConditions, cg);
dependencies->addPostCondition(targetRegisterPair, TR::RealRegister::EvenOddPair);
dependencies->addPostCondition(remRegister, TR::RealRegister::LegalEvenOfPair);
dependencies->addPostCondition(quoRegister, TR::RealRegister::LegalOddOfPair);
// TODO(#3685): Remove this Java-ism from OMR and push it into OpenJ9
if (!doConditionalRemainder &&
!node->isSimpleDivCheck() &&
!isUnsigned &&
!firstChild->isNonNegative() &&
!secondChild->isNonNegative() &&
!(secondChild->getOpCodeValue() == TR::lconst &&
secondChild->getLongInt() != CONSTANT64(0xFFFFFFFFFFFFFFFF)))
{
// We have to check for a special case where we do 0x8000000000000000/0xffffffffffffffff
// JAVA requires we return 0x8000000000000000 rem 0x00000000
generateS390ImmOp(cg, TR::InstOpCode::CG, node, quoRegister, quoRegister, (int64_t) CONSTANT64(0x8000000000000000));
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BNE, node, doDiv);
generateS390ImmOp(cg, TR::InstOpCode::CG, node, sourceRegister, sourceRegister, -1);
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BNE, node, doDiv);
genLoadLongConstant(cg, node, 0, remRegister);
skipDiv = generateLabelSymbol(cg);
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BRC, node, skipDiv);
// Label to do the division
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, doDiv);
}
TR::LabelSymbol *doneLabel = NULL;
TR::Register *absDividendReg = NULL;
bool absDividendRegIsTemp = false;
if (doConditionalRemainder)
{
TR_ASSERT(secondChild->getOpCode().isLoadConst() && secondChild->getType().isInt64(),"secondChild %s (%p) of rem should be int64 constant\n",
secondChild->getOpCode().getName(),secondChild);
if (skipDiv == NULL)
skipDiv = generateLabelSymbol(cg);
skipDiv->setEndInternalControlFlow();
dependencies->addPostCondition(sourceRegister, TR::RealRegister::AssignAny);
if (firstChild->isNonNegative())
{
absDividendReg = remRegister;
}
else
{
absDividendRegIsTemp = true;
absDividendReg = cg->allocateRegister();
// LGPR is needed so negative numbers do not always take the slow path after the logical compare (but functionally it is not needed)
generateRRInstruction(cg, TR::InstOpCode::LPGR, node, absDividendReg, remRegister);
}
int64_t value = secondChild->getLongInt();
if (value <= TR::getMaxSigned<TR::Int32>())
{
generateRILInstruction(cg, TR::InstOpCode::CLGFI, node, absDividendReg, static_cast<int32_t>(value));
}
else
{
generateRRInstruction(cg, TR::InstOpCode::CLGR, node, absDividendReg, sourceRegister);
}
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol(cg);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_MASK4, node, skipDiv); // branch to done on <
}
// Do division
if (isUnsigned)
{
if (doConditionalRemainder)
generateRRInstruction(cg, TR::InstOpCode::LGR, node, quoRegister, remRegister); // in doConditionalRemainder case this is the slow path so do move here
generateRIInstruction(cg, TR::InstOpCode::LGHI, node, remRegister, 0);
generateRRInstruction(cg, TR::InstOpCode::DLGR, node, targetRegisterPair, sourceRegister);
}
else
{
if (doConditionalRemainder)
generateRRInstruction(cg, TR::InstOpCode::LGR, node, quoRegister, remRegister); // in doConditionalRemainder case this is the slow path so do move here
generateRRInstruction(cg, TR::InstOpCode::DSGR, node, targetRegisterPair, sourceRegister);
}
// Label to skip the division
if (skipDiv != NULL)
{
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, skipDiv, dependencies);
}
else
{
generateS390PseudoInstruction(cg, TR::InstOpCode::DEPEND, node, dependencies);
}
if (absDividendRegIsTemp && absDividendReg)
cg->stopUsingRegister(absDividendReg);