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S390Instruction.cpp
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S390Instruction.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <assert.h>
#include <limits.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <algorithm>
#include "codegen/CodeGenerator.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/Relocation.hpp"
#include "codegen/Snippet.hpp"
#include "codegen/S390Snippets.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "env/CHTable.hpp"
#endif
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/Block.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/StaticSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "infra/List.hpp"
#include "infra/CfgEdge.hpp"
#include "optimizer/Structure.hpp"
#include "ras/Debug.hpp"
#include "runtime/CodeCacheManager.hpp"
#include "runtime/Runtime.hpp"
#include "z/codegen/EndianConversion.hpp"
#include "z/codegen/S390GenerateInstructions.hpp"
#include "z/codegen/S390Instruction.hpp"
#include "z/codegen/S390OutOfLineCodeSection.hpp"
void
TR::S390RSInstruction::generateAdditionalSourceRegisters(TR::Register * fReg, TR::Register *lReg)
{
int32_t firstRegNum = toRealRegister(fReg)->getRegisterNumber();
int32_t lastRegNum = toRealRegister(lReg)->getRegisterNumber();
if (firstRegNum != lastRegNum &&
lastRegNum - firstRegNum > 1)
{
TR::Machine *machine = cg()->machine();
int8_t numRegsToAdd = lastRegNum - firstRegNum - 1;
// _additionalRegisters = new (cg()->trHeapMemory(),TR_MemoryBase::Array) TR_Array<TR::Register *>(cg()->trMemory(), numRegsToAdd, false);
int8_t curReg = firstRegNum+1;
for (int8_t i=0; i < numRegsToAdd; i++)
{
// (*_additionalRegisters)[i] = machine->getRealRegister(((TR::RealRegister::RegNum)curReg));
TR::Register *temp = machine->getRealRegister(((TR::RealRegister::RegNum)curReg));
useSourceRegister(temp);
curReg++;
}
}
}
uint8_t *
TR::S390EInstruction::generateBinaryEncoding()
{
uint8_t * instructionStart = cg()->getBinaryBufferCursor();
uint8_t * cursor = instructionStart;
memset( (void*)cursor,0,getEstimatedBinaryLength());
int32_t instructionLength = getOpCode().getInstructionLength();
getOpCode().copyBinaryToBuffer(instructionStart);
cursor += getOpCode().getInstructionLength();
setBinaryLength(cursor - instructionStart);
setBinaryEncoding(instructionStart);
cg()->addAccumulatedInstructionLengthError(getEstimatedBinaryLength() - getBinaryLength());
return cursor;
}
uint8_t *
TR::S390IEInstruction::generateBinaryEncoding()
{
uint8_t * instructionStart = cg()->getBinaryBufferCursor();
uint8_t * cursor = instructionStart;
memset( (void*)cursor,0,getEstimatedBinaryLength());
int32_t instructionLength = getOpCode().getInstructionLength();
getOpCode().copyBinaryToBuffer(instructionStart);
*(cursor + 3) = getImmediateField1() << 4 | getImmediateField2();
cursor += getOpCode().getInstructionLength();
setBinaryLength(cursor - instructionStart);
setBinaryEncoding(instructionStart);
cg()->addAccumulatedInstructionLengthError(getEstimatedBinaryLength() - getBinaryLength());
return cursor;
}
bool isLoopEntryAlignmentEnabled(TR::Compilation *comp)
{
if(comp->getOption(TR_DisableLoopEntryAlignment))
return false;
if(comp->getOption(TR_EnableLoopEntryAlignment))
return true;
// Loop alignment not worth the extra bytes for <= warm compilations because if a loop at warm would have
// exhibited benefit from alignment then the loop must have been hot enough for us to recompile the method
// to > warm in the first place.
if(comp->getOptLevel() <= warm)
return false;
return true;
}
/**
* Determines whether the given instruction should be aligned with NOPs.
* Currently, it supports alignment of loop entry blocks.
*/
bool TR::S390LabeledInstruction::isNopCandidate()
{
TR::Compilation *comp = cg()->comp();
if (!isLoopEntryAlignmentEnabled(comp))
return false;
bool isNopCandidate = false;
TR::Node * node = getNode();
// Re: node->getLabel() == getLabelSymbol()
// Make sure the label is the one that corresponds with BBStart
// An example where this is not the case is labels in the pre-
// prologue where they take on the node of the first BB.
if (node != NULL && node->getOpCodeValue() == TR::BBStart &&
node->getLabel() == getLabelSymbol())
{
TR::Block * block = node->getBlock();
// Frequency 6 is "Don't Know". Do not bother aligning.
if (block->firstBlockInLoop() && !block->isCold() && block->getFrequency() > 1000)
{
TR_BlockStructure* blockStructure = block->getStructureOf();
if (blockStructure)
{
TR_RegionStructure *region = (TR_RegionStructure*)blockStructure->getContainingLoop();
if (region)
{
// make sure block == entry, so that you're doing stuff for loop entry
//
TR::Block *entry = region->getEntryBlock();
assert(entry==block);
uint32_t loopLength = 0;
for (auto e = entry->getPredecessors().begin(); e != entry->getPredecessors().end(); ++e)
{
TR::Block *predBlock = toBlock((*e)->getFrom());
if (!region->contains(predBlock->getStructureOf(), region->getParent()))
continue;
// Backedge found.
TR::Instruction* lastInstr = predBlock->getLastInstruction();
// Find the branch instruction.
int32_t window = 4; // limit search distance.
while(window >= 0 && !lastInstr->getOpCode().isBranchOp())
{
window--;
lastInstr = lastInstr->getPrev();
}
// Determine Length of Loop.
TR::Instruction * firstInstr = block->getFirstInstruction();
TR::Instruction * currInstr;
for(currInstr=firstInstr; ; currInstr=currInstr->getNext())
{
if(currInstr==NULL)
{
// We might be here if the loop structure isn't consecutive in memory
return false;
}
loopLength += currInstr->getOpCode().getInstructionLength();
if(loopLength>256)
return false;
if(currInstr==lastInstr)
break;
}
// Determine if the loop will cross cache line boundry
uint8_t * cursor = cg()->getBinaryBufferCursor();
if( loopLength <= 256 && (((uint64_t)cursor+loopLength)&0xffffff00) > ((uint64_t)cursor&0xffffff00) )
{
isNopCandidate = true;
traceMsg(comp, "Insert NOP instructions for loop alignment\n");
break;
}
else
{
isNopCandidate = false;
break;
}
}
}
}
}
}
return isNopCandidate;
}
////////////////////////////////////////////////////////
// TR::S390LabelInstruction:: member functions
////////////////////////////////////////////////////////
/**
* LabelInstruction is a pseudo instruction that generates a label or constant (with a label)
*
* Currently, this pseudo instruction handles the following 2 scenarios:
*
* 1. emit a label
*
* 2. emit a snippet label
*
*/
uint8_t *
TR::S390LabelInstruction::generateBinaryEncoding()
{
uint8_t * instructionStart = cg()->getBinaryBufferCursor();
TR::Compilation *comp = cg()->comp();
TR::LabelSymbol * label = getLabelSymbol();
TR::Snippet * snippet = getCallSnippet();
uint8_t * cursor = instructionStart;
memset( (void*)cursor,0,getEstimatedBinaryLength());
uint16_t binOpCode = *(uint16_t *) (getOpCode().getOpCodeBinaryRepresentation());
if (getOpCode().getOpCodeValue() == TR::InstOpCode::DC)
{
AOTcgDiag1(comp, "add TR_AbsoluteMethodAddress cursor=%x\n", cursor);
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelAbsoluteRelocation(cursor, label));
cg()->addProjectSpecializedRelocation(cursor, NULL, NULL, TR_AbsoluteMethodAddress,
__FILE__, __LINE__, getNode());
if (label->getCodeLocation() != NULL)
{
*((uintptr_t *) cursor) = boa((uintptr_t) label->getCodeLocation());
}
cursor += sizeof(uintptr_t);
}
else // must be real LABEL instruction
{
// Insert Padding if necessary.
if (_alignment != 0)
{
int32_t padding = _alignment - (((uintptr_t)instructionStart) % _alignment);
for (int i = padding / 6; i > 0; i--)
{
(*(uint16_t *) cursor) = 0xC004;
cursor += sizeof(uint16_t);
(*(uint32_t *) cursor) = 0xDEADBEEF;
cursor += sizeof(uint32_t);
}
padding = padding % 6;
for (int i = padding / 4; i > 0; i--)
{
(*(uint32_t *) cursor) = 0xA704BEEF;
cursor += sizeof(uint32_t);
}
padding = padding % 4;
if (padding == 2)
{
(*(uint16_t *) cursor) = 0x1800;
cursor += sizeof(uint16_t);
}
}
getLabelSymbol()->setCodeLocation(instructionStart);
TR_ASSERT(getOpCode().getOpCodeValue() == TR::InstOpCode::LABEL, "LabelInstr not DC or LABEL, what is it??");
}
// Insert NOPs for loop alignment if possible
uint64_t offset = 0;
uint8_t * newInstructionStart = NULL;
int32_t labelTargetBytesInserted = 0;
offset = (uint64_t)cursor&(0xff);
newInstructionStart = (uint8_t *) (((uintptr_t)cursor+256)/256*256);
if (offset && isNopCandidate())
{
setEstimatedBinaryLength(getEstimatedBinaryLength()+256-offset);
getLabelSymbol()->setCodeLocation(newInstructionStart); // Label location need to be updated
assert(offset%2==0);
TR::Instruction * prevInstr = getPrev();
TR::Instruction * instr;
TR_Debug * debugObj = cg()->getDebug();
// Insert a BRC instruction to skip NOP instructions if there're more than 3 NOPs to insert
if(offset<238)
{
uint8_t *curBeforeJump = cursor;
instr = generateS390BranchInstruction(cg(), TR::InstOpCode::BRC, TR::InstOpCode::COND_MASK15, getNode(), getLabelSymbol(), prevInstr);
instr->setEstimatedBinaryLength(10);
cg()->setBinaryBufferCursor(cursor = instr->generateBinaryEncoding());
if (debugObj)
debugObj->addInstructionComment(instr, "Skip NOP instructions for loop alignment");
offset = (uint64_t)cursor&0xff;
prevInstr = instr;
}
// Insert NOP instructions until cursor is aligned
for(; offset;)
{
uint8_t *curBeforeNOPs = cursor;
if(offset<=250)
{
instr = new (cg()->trHeapMemory()) TR::S390NOPInstruction(TR::InstOpCode::NOP, 6, getNode(), prevInstr, cg());
instr->setEstimatedBinaryLength(6);
}
else if(offset<=252)
{
instr = new (cg()->trHeapMemory()) TR::S390NOPInstruction(TR::InstOpCode::NOP, 4, getNode(), prevInstr, cg());
instr->setEstimatedBinaryLength(4);
}
else if(offset<=254)
{
instr = new (cg()->trHeapMemory()) TR::S390NOPInstruction(TR::InstOpCode::NOP, 2, getNode(), prevInstr, cg());
instr->setEstimatedBinaryLength(2);
}
cg()->setBinaryBufferCursor(cursor = instr->generateBinaryEncoding());
offset = (uint64_t)cursor&0xff;
prevInstr = instr;
}
instructionStart = cursor;
}
setBinaryLength(cursor - instructionStart);
cg()->addAccumulatedInstructionLengthError(getEstimatedBinaryLength() - getBinaryLength());
setBinaryEncoding(instructionStart);
return cursor;
}
int32_t
TR::S390LabelInstruction::estimateBinaryLength(int32_t currentEstimate)
{
if (getLabelSymbol() != NULL)
{
getLabelSymbol()->setEstimatedCodeLocation(currentEstimate);
}
TR::Compilation *comp = cg()->comp();
uint8_t estimatedSize = 0;
if (getOpCode().getOpCodeValue() == TR::InstOpCode::DC)
{
estimatedSize = sizeof(uintptr_t);
}
else
{
estimatedSize = 0;
}
if (isLoopEntryAlignmentEnabled(comp))
{
// increase estimate by 256 if it's a loop alignment candidate
TR::Node * node = getNode();
if(node != NULL && node->getOpCodeValue() == TR::BBStart &&
node->getLabel() == getLabelSymbol() && node->getBlock()->firstBlockInLoop() &&
!node->getBlock()->isCold() && node->getBlock()->getFrequency() > 1000)
{
setEstimatedBinaryLength(estimatedSize+256);
return currentEstimate + estimatedSize + 256;
}
}
setEstimatedBinaryLength(estimatedSize);
return currentEstimate + estimatedSize;
}
void
TR::S390LabelInstruction::assignRegistersAndDependencies(TR_RegisterKinds kindToBeAssigned)
{
//
TR::Register **_sourceReg = sourceRegBase();
TR::Register **_targetReg = targetRegBase();
TR::MemoryReference **_sourceMem = sourceMemBase();
TR::MemoryReference **_targetMem = targetMemBase();
TR::Compilation *comp = cg()->comp();
//
// If there are any dependency conditions on this instruction, apply them.
// Any register or memory references must be blocked before the condition
// is applied, then they must be subsequently unblocked.
//
if (getDependencyConditions())
{
block(_sourceReg, _sourceRegSize, _targetReg, _targetRegSize, _targetMem, _sourceMem);
getDependencyConditions()->assignPostConditionRegisters(this, kindToBeAssigned, cg());
unblock(_sourceReg, _sourceRegSize, _targetReg, _targetRegSize, _targetMem, _sourceMem);
}
assignOrderedRegisters(kindToBeAssigned);
// Compute bit vector of free regs
// if none found, find best spill register
assignFreeRegBitVector();
// this is the return label from OOL
if (getLabelSymbol()->isEndOfColdInstructionStream())
{
TR::Machine *machine = cg()->machine();
if (comp->getOption(TR_TraceRA))
traceMsg (comp,"\nOOL: taking register state snap shot\n");
cg()->setIsOutOfLineHotPath(true);
machine->takeRegisterStateSnapShot();
}
}
////////////////////////////////////////////////////////
// TR::S390BranchInstruction:: member functions
////////////////////////////////////////////////////////
void
TR::S390BranchInstruction::assignRegistersAndDependencies(TR_RegisterKinds kindToBeAssigned)
{
//
// If there are any dependency conditions on this instruction, apply them.
// Any register or memory references must be blocked before the condition
// is applied, then they must be subsequently unblocked.
//
TR::Register **_sourceReg = sourceRegBase();
TR::Register **_targetReg = targetRegBase();
TR::MemoryReference **_sourceMem = sourceMemBase();
TR::MemoryReference **_targetMem = targetMemBase();
TR::Compilation *comp = cg()->comp();
if (getDependencyConditions())
{
block(_sourceReg, _sourceRegSize, _targetReg, _targetRegSize, _targetMem, _sourceMem);
getDependencyConditions()->assignPostConditionRegisters(this, kindToBeAssigned, cg());
unblock(_sourceReg, _sourceRegSize, _targetReg, _targetRegSize, _targetMem, _sourceMem);
}
assignOrderedRegisters(kindToBeAssigned);
// Compute bit vector of free regs
// if none found, find best spill register
assignFreeRegBitVector();
cg()->freeUnlatchedRegisters();
if (getOpCode().isBranchOp() && getLabelSymbol()->isStartOfColdInstructionStream())
{
// Switch to the outlined instruction stream and assign registers.
//
TR_S390OutOfLineCodeSection *oi = cg()->findS390OutOfLineCodeSectionFromLabel(getLabelSymbol());
TR_ASSERT(oi, "Could not find S390OutOfLineCodeSection stream from label. instr=%p, label=%p\n", this, getLabelSymbol());
if (!oi->hasBeenRegisterAssigned())
oi->assignRegisters(kindToBeAssigned);
}
if (getOpCode().getOpCodeValue() == TR::InstOpCode::AP /*&& toS390SS2Instruction(this)->getLabel()*/ )
{
TR_S390OutOfLineCodeSection *oi = cg()->findS390OutOfLineCodeSectionFromLabel(toS390SS2Instruction(this)->getLabel());
TR_ASSERT(oi, "Could not find S390OutOfLineCodeSection stream from label. instr=%p, label=%p\n", this, toS390SS2Instruction(this)->getLabel());
if (!oi->hasBeenRegisterAssigned())
oi->assignRegisters(kindToBeAssigned);
}
if (getOpCode().isBranchOp() && getLabelSymbol()->isEndOfColdInstructionStream())
{
// This if statement prevents RA to restore register snapshot on regular branches to the
// OOL section merging point. Register snapshot is a snapshot of register states taken at
// OOL merge label. Using this snapshot RA can enforce the similarity of register states
// at the end of main-stream code and OOL path.
// Generally the safer option is to not reuse OOL merge label for any other purpose. This
// can be done by creating an extra label right after merge point label.
if (cg()->getIsInOOLSection())
{
// Branches from inside an OOL section to the merge-points are not allowed. Branches
// in the OOL section can jump to the end of section and then only one branch (the
// last instruction of an OOL section) jumps to the merge-point. In other words, OOL
// section must contain exactly one exit point.
TR_ASSERT(cg()->getAppendInstruction() == this, "OOL section must have only one branch to the merge point\n");
// Start RA for OOL cold path, restore register state from snap shot
TR::Machine *machine = cg()->machine();
if (comp->getOption(TR_TraceRA))
traceMsg (comp, "\nOOL: Restoring Register state from snap shot\n");
cg()->setIsOutOfLineHotPath(false);
machine->restoreRegisterStateFromSnapShot();
}
// Reusing the OOL Section merge label for other branches might be unsafe.
else if(comp->getOption(TR_TraceRA))
traceMsg (comp, "\nOOL: Reusing the OOL Section merge label for other branches might be unsafe.\n");
}
}
/**
*
* BranchInstruction is a pseudo instruction that generates instructions to branch to a symbol.
*
* Currently, this pseudo instruction handles the following 2 scenarios:
*
* 1. emit branch instruction to a label.
* 2. emit branch instruction to a snippet.
*
* On G5, the instruction will be a branch relative or branch on condition instruction.
* If the branch distance is within +/- 2**16, it will be done with a relative branch.
* Otherwise, it will be done with the following (horrible) sequence:
* BRAS r7, 4
* DC branching target address
* L r7,0(,r7)
* BCR r7
* Subtle note: since 64-bit is running on a Freeway or above (by definition), slow muck
* will not be generated. Note this is different than BranchOnCount and BranchOnIndex
* since they don't have long branch equivalents for themselves.
*/
uint8_t *
TR::S390BranchInstruction::generateBinaryEncoding()
{
uint8_t * instructionStart = cg()->getBinaryBufferCursor();
TR::LabelSymbol * label = getLabelSymbol();
TR::Snippet * snippet = getCallSnippet();
uint8_t * cursor = instructionStart;
memset(static_cast<void*>(cursor), 0, getEstimatedBinaryLength());
TR::Compilation *comp = cg()->comp();
intptr_t distance;
uint8_t * relocationPoint = NULL;
bool doRelocation;
bool shortRelocation = false;
bool longRelocation = false;
// msf - commented out since it does not work in cross-compile mode - TR_ASSERT(((binOpCode & 0xFF0F)== 0xA704),"Only TR::InstOpCode::BRC is handled here\n");
if (label->getCodeLocation() != NULL)
{
// Label location is known
// calculate the relative branch distance
distance = (label->getCodeLocation() - cursor)/2;
doRelocation = false;
}
else if (label->isRelativeLabel())
{
distance = label->getDistance();
doRelocation = false;
}
else
{
// Label location is unknown
// estimate the relative branch distance
distance = (cg()->getBinaryBufferStart() + label->getEstimatedCodeLocation()) -
(cursor + cg()->getAccumulatedInstructionLengthError());
distance /= 2;
doRelocation = true;
}
if (distance >= MIN_IMMEDIATE_VAL && distance <= MAX_IMMEDIATE_VAL)
{
// if distance is within 32K limit, generate short instruction
getOpCode().copyBinaryToBuffer(cursor);
if (getOpCode().isBranchOp() && (getBranchCondition() != TR::InstOpCode::COND_NOP))
{
*(cursor + 1) &= (uint8_t) 0x0F;
*(cursor + 1) |= (uint8_t) getMask();
}
*(int16_t *) (cursor + 2) |= bos(distance);
relocationPoint = cursor + 2;
shortRelocation = true;
cursor += getOpCode().getInstructionLength();
}
else
{
// Since N3 and up, generate BRCL instruction
getOpCode().copyBinaryToBuffer(cursor);
*(uint8_t *) cursor = 0xC0; // change to BRCL,keep the mask
setOpCodeValue(TR::InstOpCode::BRCL);
if (getOpCode().isBranchOp() && (getBranchCondition() != TR::InstOpCode::COND_NOP))
{
*(cursor + 1) &= (uint8_t) 0x0F;
*(cursor + 1) |= (uint8_t) getMask();
}
*(int32_t *) (cursor + 2) |= boi(distance);
longRelocation = true;
relocationPoint = cursor;
cursor += 6;
}
if (doRelocation)
{
if (shortRelocation)
{
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelRelative16BitRelocation(relocationPoint, label));
}
else if (longRelocation)
{
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelRelative32BitRelocation(relocationPoint, label));
}
else
{
AOTcgDiag1(comp, "add TR_AbsoluteMethodAddress cursor=%x\n", cursor);
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelAbsoluteRelocation(relocationPoint, label));
cg()->addProjectSpecializedRelocation(relocationPoint, NULL, NULL, TR_AbsoluteMethodAddress,
__FILE__, __LINE__, getNode());
}
}
setBinaryLength(cursor - instructionStart);
cg()->addAccumulatedInstructionLengthError(getEstimatedBinaryLength() - getBinaryLength());
setBinaryEncoding(instructionStart);
return cursor;
}
int32_t
TR::S390BranchInstruction::estimateBinaryLength(int32_t currentEstimate)
{
int32_t length = 6;
TR::Compilation *comp = cg()->comp();
setEstimatedBinaryLength(length);
return currentEstimate + getEstimatedBinaryLength();
}
////////////////////////////////////////////////////////
// TR::S390BranchOnCountInstruction:: member functions
////////////////////////////////////////////////////////
/**
* BranchOnCountInstruction is a pseudo instruction that generates instructions to branch on count to a symbol.
*
* Currently, this pseudo instruction handles the following scenario:
*
* 1. emit branch instruction to a label.
* On G5, the instruction will be a branch relative or branch on condition instruction.
* If the branch distance is within +/- 2**16, it will be done with a relative branch.
* Otherwise, it will be done with the following (horrible) sequence:
* BRAS r7, 4
* DC branching target address
* L r7,0(,r7)
* BCT Rx,R7
* MSF:: NB::: 64-bit support needs to be added
*
* For W-Code, we generate
* BRCT Rx,*+8
* BRC 0xf, *+10
* BCRL 0xf, label
*/
uint8_t *
TR::S390BranchOnCountInstruction::generateBinaryEncoding()
{
uint8_t * instructionStart = cg()->getBinaryBufferCursor();
TR::LabelSymbol * label = getLabelSymbol();
TR::Snippet * snippet = getCallSnippet();
uint8_t * cursor = instructionStart;
memset( (void*)cursor,0,getEstimatedBinaryLength());
uint16_t binOpCode = *(uint16_t *) (getOpCode().getOpCodeBinaryRepresentation());
TR::Compilation *comp = cg()->comp();
intptr_t distance;
uint8_t * relocationPoint = NULL;
bool doRelocation;
bool shortRelocation = false;
if (label->getCodeLocation() != NULL)
{
// Label location is known
// calculate the relative branch distance
distance = (label->getCodeLocation() - cursor) / 2;
doRelocation = false;
}
else if (label->isRelativeLabel())
{
distance = label->getDistance();
doRelocation = false;
}
else
{
// Label location is unknown
// estimate the relative branch distance
distance = (cg()->getBinaryBufferStart() + label->getEstimatedCodeLocation()) -
cursor -
cg()->getAccumulatedInstructionLengthError();
distance /= 2;
doRelocation = true;
}
if ((binOpCode & 0xFF0F) == 0xCC06) //BRCTH
{
getOpCode().copyBinaryToBuffer(instructionStart);
*(int32_t *) (cursor + 2) |= boi(distance);
relocationPoint = cursor + 2;
cursor += getOpCode().getInstructionLength();
toRealRegister(getRegisterOperand(1))->setRegisterField((uint32_t *) instructionStart);
if (doRelocation)
{
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelRelative32BitRelocation(relocationPoint, label));
}
}
else
{
// if distance is within 32K limit on G5
if (distance >= MIN_IMMEDIATE_VAL && distance <= MAX_IMMEDIATE_VAL)
{
getOpCode().copyBinaryToBuffer(instructionStart);
*(int16_t *) (cursor + 2) |= bos(distance);
relocationPoint = cursor + 2;
shortRelocation = true;
cursor += getOpCode().getInstructionLength();
toRealRegister(getRegisterOperand(1))->setRegisterField((uint32_t *) instructionStart);
}
else
{
TR_ASSERT(((binOpCode & 0xFF0F) == 0xA706), "Only TR::InstOpCode::BRCT is handled here\n");
TR::LabelSymbol *relLabel = TR::LabelSymbol::createRelativeLabel(cg()->trHeapMemory(),
cg(),
+4);
setLabelSymbol(relLabel);
relLabel = TR::LabelSymbol::createRelativeLabel(cg()->trHeapMemory(),
cg(),
+5);
TR::Instruction *instr;
instr = generateS390BranchInstruction(cg(), TR::InstOpCode::BRC, TR::InstOpCode::COND_MASK15, getNode(), relLabel, this);
instr->setEstimatedBinaryLength(4);
instr = generateS390BranchInstruction(cg(), TR::InstOpCode::BRC, TR::InstOpCode::COND_MASK15, getNode(), label, instr);
instr->setEstimatedBinaryLength(8);
return generateBinaryEncoding();
}
if (doRelocation)
{
if (shortRelocation)
{
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelRelative16BitRelocation(relocationPoint, label));
}
else
{
AOTcgDiag1(comp, "add TR_AbsoluteMethodAddress cursor=%x\n", relocationPoint);
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelAbsoluteRelocation(relocationPoint, label));
cg()->addProjectSpecializedRelocation(relocationPoint, NULL, NULL, TR_AbsoluteMethodAddress,
__FILE__, __LINE__, getNode());
}
}
}
toRealRegister(getRegisterOperand(1))->setRegisterField((uint32_t *) instructionStart);
setBinaryLength(cursor - instructionStart);
cg()->addAccumulatedInstructionLengthError(getEstimatedBinaryLength() - getBinaryLength());
setBinaryEncoding(instructionStart);
return cursor;
}
int32_t
TR::S390BranchOnCountInstruction::estimateBinaryLength(int32_t currentEstimate)
{
setEstimatedBinaryLength(getOpCode().getInstructionLength());
//code could be expanded into BRAS(4)+DC(4)+L(4)+BCT(4) sequence
setEstimatedBinaryLength(16);
return currentEstimate + getEstimatedBinaryLength();
}
bool
TR::S390BranchOnCountInstruction::refsRegister(TR::Register * reg)
{
if (matchesAnyRegister(reg, getRegisterOperand(1)))
{
return true;
}
else if (getDependencyConditions())
{
return getDependencyConditions()->refsRegister(reg);
}
else
{
return false;
}
}
/**
* BranchOnIndexInstruction is a pseudo instruction that generates instructions to branch to a symbol.
*
* Currently, this pseudo instruction handles the following scenario:
*
* 1. emit branch instruction to a label.
* On G5, the instruction will be a branch relative or branch on condition instruction.
* If the branch distance is within +/- 2**16, it will be done with a relative branch.
* Otherwise, it will be done with the following (horrible) sequence:
* BRAS r7, 4
* DC branching target address
* L r7,0(,r7)
* BXL/BXH rx,ry,r7
* MSF:: NB::: 64-bit support needs to be added -- Done: LD
* LD: could do better for long displacement on N3 and 64bit--TODO
*/
uint8_t *
TR::S390BranchOnIndexInstruction::generateBinaryEncoding()
{
uint8_t * instructionStart = cg()->getBinaryBufferCursor();
TR::LabelSymbol * label = getLabelSymbol();
TR::Snippet * snippet = getCallSnippet();
uint8_t * cursor = instructionStart;
memset( (void*)cursor,0,getEstimatedBinaryLength());
uint16_t binOpCode = *(uint16_t *) (getOpCode().getOpCodeBinaryRepresentation());
bool shortRelocation = false;
intptr_t distance;
uint8_t * relocationPoint = NULL;
bool doRelocation;
if (label->getCodeLocation() != NULL)
{
// Label location is known
// calculate the relative branch distance
distance = (label->getCodeLocation() - cursor) / 2;
doRelocation = false;
}
else
{
// Label location is unknown
// estimate the relative branch distance
distance = (cg()->getBinaryBufferStart() + label->getEstimatedCodeLocation()) -
cursor -
cg()->getAccumulatedInstructionLengthError();
distance /= 2;
doRelocation = true;
}
// if distance is within 32K limit on G5
if (distance >= MIN_IMMEDIATE_VAL && distance <= MAX_IMMEDIATE_VAL)
{
getOpCode().copyBinaryToBuffer(instructionStart);
TR::Register * srcReg = getRegForBinaryEncoding(getRegisterOperand(2));
*(int16_t *) (cursor + 2) |= bos(distance);
relocationPoint = cursor + 2;
shortRelocation = true;
cursor += getOpCode().getInstructionLength();
toRealRegister(getRegisterOperand(1))->setRegisterField((uint32_t *) instructionStart);
toRealRegister(srcReg)->setRegister2Field((uint32_t *) instructionStart);
}
else
{
TR_ASSERT_FATAL(false, "Cannot encode branch on index instruction because distance (%d) is out of range", distance);
}
if (doRelocation)
{
if (shortRelocation)
{
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelRelative16BitRelocation(relocationPoint, label));
}
else
{
AOTcgDiag1(cg()->comp(), "add TR_AbsoluteMethodAddress cursor=%x\n", relocationPoint);
cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelAbsoluteRelocation(relocationPoint, label));
cg()->addProjectSpecializedRelocation(relocationPoint, NULL, NULL, TR_AbsoluteMethodAddress,
__FILE__, __LINE__, getNode());
}
}
toRealRegister(getRegisterOperand(1))->setRegisterField((uint32_t *) instructionStart);
setBinaryLength(cursor - instructionStart);
cg()->addAccumulatedInstructionLengthError(getEstimatedBinaryLength() - getBinaryLength());
setBinaryEncoding(instructionStart);
return cursor;
}
int32_t
TR::S390BranchOnIndexInstruction::estimateBinaryLength(int32_t currentEstimate)
{
setEstimatedBinaryLength(getOpCode().getInstructionLength());
//code could be expanded into BRAS(4)+DC(4)+L(4)+BXLE(4) sequence
//or BRAS(4)+DC(8)+LG(6)+BXLG(6) sequence
if (sizeof(intptr_t) == 8)
{
setEstimatedBinaryLength(24);
}
else
{
setEstimatedBinaryLength(16);
}
return currentEstimate + getEstimatedBinaryLength();
}
bool
TR::S390BranchOnIndexInstruction::refsRegister(TR::Register * reg)
{
if (matchesAnyRegister(reg, getRegisterOperand(1), getRegisterOperand(2)))
{
return true;
}
else if (getDependencyConditions())
{
return getDependencyConditions()->refsRegister(reg);
}
return false;
}
////////////////////////////////////////////////////////////////////////////////
// TR::S390FenceInstruction:: member functions
////////////////////////////////////////////////////////////////////////////////
uint8_t *
TR::S390PseudoInstruction::generateBinaryEncoding()
{
uint8_t * instructionStart = cg()->getBinaryBufferCursor();
uint8_t * cursor = instructionStart;
TR::Compilation *comp = cg()->comp();
if (_fenceNode != NULL) // must be fence node
{
if (_fenceNode->getRelocationType() == TR_AbsoluteAddress)
{
for (int32_t i = 0; i < _fenceNode->getNumRelocations(); ++i)
{
*(uint8_t * *) (_fenceNode->getRelocationDestination(i)) = instructionStart;
}
}
else if (_fenceNode->getRelocationType() == TR_EntryRelative32Bit)
{
for (int32_t i = 0; i < _fenceNode->getNumRelocations(); ++i)
{
*(uint32_t *) (_fenceNode->getRelocationDestination(i)) = boi(cg()->getCodeLength());
}
}
else // entryrelative16bit
{
for (int32_t i = 0; i < _fenceNode->getNumRelocations(); ++i)
{
*(uint16_t *) (_fenceNode->getRelocationDestination(i)) = bos((uint16_t) cg()->getCodeLength());
}
}
}
setBinaryLength(0);
if (_callDescLabel != NULL) // We have to emit a branch around a 8-byte aligned call descriptor.
{
// For zOS-31 XPLINK, if the call descriptor is too far away from the native call NOP, we have
// to manually emit a branch around the call descriptor in the main line code.
// BRC 4 + Padding
// <Padding>
// DC <call Descriptor> // 8-bytes aligned.
_padbytes = ((intptr_t)(cursor + 4) + 7) / 8 * 8 - (intptr_t)(cursor + 4);
// BRC 4 + padding.
*((uint32_t *) cursor) = boi(0xA7F40000 + 6 + _padbytes / 2);
cursor += sizeof(uint32_t);
// Add Padding to make sure Call Descriptor is aligned.
if (_padbytes == 2)
{
*(int16_t *) cursor = bos(0x0000); // padding 2-bytes
cursor += 2;
}
else if (_padbytes == 4)
{
*(int32_t *) cursor = boi(0x00000000);
cursor += 4;
}
else if (_padbytes == 6)