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OMRMachine.cpp
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OMRMachine.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
//On zOS XLC linker can't handle files with same name at link time
//This workaround with pragma is needed. What this does is essentially
//give a different name to the codesection (csect) for this file. So it
//doesn't conflict with another file with same name.
#pragma csect(CODE,"OMRZMachine#C")
#pragma csect(STATIC,"OMRZMachine#S")
#pragma csect(TEST,"OMRZMachine#T")
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "codegen/BackingStore.hpp"
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/Machine.hpp"
#include "codegen/Machine_inlines.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterPair.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/ObjectModel.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/Block.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "infra/Assert.hpp"
#include "infra/Flags.hpp"
#include "infra/List.hpp"
#include "infra/Random.hpp"
#include "infra/Stack.hpp"
#include "codegen/SystemLinkage.hpp"
#include "ras/Debug.hpp"
#include "z/codegen/S390GenerateInstructions.hpp"
#include "z/codegen/S390Instruction.hpp"
// Register Association
#define S390_REGISTER_HEAVIEST_WEIGHT 0x0000ffff
#define S390_REGISTER_INTERFERENCE_WEIGHT 0x00008000
#define S390_REGISTER_INITIAL_PRESERVED_WEIGHT 0x00001000
#define S390_REGISTER_ASSOCIATED_WEIGHT 0x00000800
#define S390_REGISTER_PLACEHOLDER_WEIGHT 0x00000100
#define S390_REGISTER_LOW_PRIORITY_WEIGHT 0x000000C0
#define S390_REGISTER_BASIC_WEIGHT 0x00000080
#define S390_REGISTER_PRESERVED_WEIGHT 0x00000002
#define S390_REGISTER_PAIR_SIBLING 0x00008000
////////////////////////////////////////////////////////////////////////////////
// OMR::Z::Machine memeber functions
////////////////////////////////////////////////////////////////////////////////
TR_Debug *
OMR::Z::Machine::getDebug()
{
return self()->cg()->getDebug();
}
static const char *
getRegisterName(TR::Register * reg, TR::CodeGenerator * cg)
{
if (cg->getDebug() && reg)
return cg->getDebug()->getName(reg);
else
return "NULL";
}
#define regName(reg) getRegisterName(reg,cg())
///////////////////////////////////////////////////////////////////////////////
// Copy Register by moving source register to target register
///////////////////////////////////////////////////////////////////////////////
TR::Instruction *
OMR::Z::Machine::registerCopy(TR::CodeGenerator* cg,
TR_RegisterKinds rk,
TR::RealRegister* targetReg,
TR::RealRegister* sourceReg,
TR::Instruction* precedingInstruction)
{
// TODO: In reality we should be validating that the the source is NULL and target is non-NULL however we cannot
// currently do this because the registerCopy and registerExchange APIs are not updating the register states as
// registers are shuffled around.
//
// A typical example of when this assert would fire is when attempting a register exchange (which uses this API)
// via a spare reigster. We will generate 3 register shuffles but the register state is only updated later, thus
// during the second shuffle the spare register will the the target in the above parameter and as such we would
// assert since the spare register presumably did not have any virtual register associated with it.
TR_ASSERT_FATAL(sourceReg->getAssignedRegister() != NULL || targetReg->getAssignedRegister() != NULL, "Attempting register copy with source (%s) and target (%s) real registers not corresponding to any virtual register", getRegisterName(sourceReg, cg), getRegisterName(targetReg, cg));
TR::Node* node = precedingInstruction->getNode();
TR::Instruction* cursor = NULL;
switch (rk)
{
case TR_GPR:
{
// TODO: Once above is fixed we can always rely on targetReg->getAssignedRegister()
auto nonNullAssignedReg = targetReg->getAssignedRegister() != NULL ?
targetReg->getAssignedRegister() :
sourceReg->getAssignedRegister();
auto mnemonic = nonNullAssignedReg->is64BitReg() ?
TR::InstOpCode::LGR :
TR::InstOpCode::LR;
cursor = generateRRInstruction(cg, mnemonic, node, targetReg, sourceReg, precedingInstruction);
break;
}
case TR_FPR:
cursor = generateRRInstruction(cg, TR::InstOpCode::LDR, node, targetReg, sourceReg, precedingInstruction);
break;
case TR_VRF:
cursor = generateVRRaInstruction(cg, TR::InstOpCode::VLR, node, targetReg, sourceReg, precedingInstruction);
break;
}
cg->traceRAInstruction(cursor);
TR_Debug* debug = cg->getDebug();
if (debug)
{
debug->addInstructionComment(cursor, "Register copy");
}
return cursor;
}
/**
* Exchange the contents of two registers
*/
TR::Instruction *
OMR::Z::Machine::registerExchange(TR::CodeGenerator* cg,
TR_RegisterKinds rk,
TR::RealRegister* targetReg,
TR::RealRegister* sourceReg,
TR::RealRegister* middleReg,
TR::Instruction* precedingInstruction)
{
TR_ASSERT_FATAL(sourceReg->getAssignedRegister() != NULL, "Attempting register exchange with source real register (%s) not corresponding to any virtual register", getRegisterName(sourceReg, cg));
TR_ASSERT_FATAL(targetReg->getAssignedRegister() != NULL, "Attempting register exchange with target real register (%s) not corresponding to any virtual register", getRegisterName(targetReg, cg));
// middleReg is not used if rk==TR_GPR.
TR::Compilation *comp = cg->comp();
TR::Node * currentNode = precedingInstruction->getNode();
TR::Instruction * currentInstruction = NULL;
char * REG_EXCHANGE = "LR=Reg_exchg";
char * REG_PAIR = "LR=Reg_pair";
TR_Debug * debugObj = cg->getDebug();
TR::Machine *machine = cg->machine();
// exchange floating point registers
if (rk == TR_FPR)
{
if (middleReg != NULL)
{
middleReg->setHasBeenAssignedInMethod(true);
currentInstruction = machine->registerCopy(cg, rk, sourceReg, middleReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
currentInstruction = machine->registerCopy(cg, rk, targetReg, sourceReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
currentInstruction = machine->registerCopy(cg, rk, middleReg, targetReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
}
else
{
TR::Instruction * currentInstruction = precedingInstruction;
TR_BackingStore * location;
location = cg->allocateSpill(8, false, NULL);
TR::MemoryReference * tempMR = generateS390MemoryReference(currentNode, location->getSymbolReference(), cg);
location->getSymbolReference()->getSymbol()->setSpillTempLoaded();
currentInstruction = generateRXInstruction(cg, TR::InstOpCode::STD, currentNode, targetReg, tempMR, currentInstruction);
cg->traceRAInstruction(currentInstruction);
currentInstruction = generateRRInstruction(cg, TR::InstOpCode::LDR, currentNode, targetReg, sourceReg, currentInstruction);
cg->traceRAInstruction(currentInstruction);
TR::MemoryReference * tempMR2 = generateS390MemoryReference(*tempMR, 0, cg);
currentInstruction = generateRXInstruction(cg, TR::InstOpCode::LD, currentNode, sourceReg, tempMR2, currentInstruction);
cg->traceRAInstruction(currentInstruction);
cg->freeSpill(location, 8, 0);
}
cg->generateDebugCounter("RegisterAllocator/Exchange/FPR", 1, TR::DebugCounter::Free);
}
// exchange vector registers
else if (rk == TR_VRF)
{
// Uses naive temp move and if none available, uses memory.
if (middleReg != NULL)
{
middleReg->setHasBeenAssignedInMethod(true);
currentInstruction = machine->registerCopy(cg, rk, sourceReg, middleReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
currentInstruction = machine->registerCopy(cg, rk, targetReg, sourceReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
currentInstruction = machine->registerCopy(cg, rk, middleReg, targetReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
}
else
{
TR_BackingStore * location;
location = cg->allocateSpill(16, false, NULL);
TR::MemoryReference * tempMR = generateS390MemoryReference(currentNode, location->getSymbolReference(), cg);
location->getSymbolReference()->getSymbol()->setSpillTempLoaded();
currentInstruction = generateVRXInstruction(cg, TR::InstOpCode::VST, currentNode, targetReg, tempMR, 0, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
currentInstruction = generateVRRaInstruction(cg, TR::InstOpCode::VLR, currentNode, targetReg, sourceReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
TR::MemoryReference * tempMR2 = generateS390MemoryReference(*tempMR, 0, cg);
currentInstruction = generateVRXInstruction(cg, TR::InstOpCode::VL, currentNode, sourceReg, tempMR2, 0, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
cg->freeSpill(location, 16, 0);
}
cg->generateDebugCounter("RegisterAllocator/Exchange/VRF", 1, TR::DebugCounter::Free);
}
else
{
TR::InstOpCode::Mnemonic opLoadReg = TR::InstOpCode::bad;
TR::InstOpCode::Mnemonic opLoad = TR::InstOpCode::bad;
TR::InstOpCode::Mnemonic opStore = TR::InstOpCode::bad;
if (targetReg->getAssignedRegister()->is64BitReg() || sourceReg->getAssignedRegister()->is64BitReg())
{
opLoadReg = TR::InstOpCode::LGR;
opLoad = TR::InstOpCode::LG;
opStore = TR::InstOpCode::STG;
}
else
{
opLoadReg = TR::InstOpCode::LR;
opLoad = TR::InstOpCode::L;
opStore = TR::InstOpCode::ST;
}
// exchange general purpose registers
//
if (middleReg == NULL)
{
// Nasty OSC... should happen very rarely. Only in cases where deps reach critical mass in reg table
// and last dep resolution requires a regexch from 'blocked' state.
//
TR::Instruction * currentInstruction = precedingInstruction;
TR_BackingStore * location;
if (targetReg->getAssignedRegister()->is64BitReg() || sourceReg->getAssignedRegister()->is64BitReg())
{
location = cg->allocateSpill(8, false, NULL);
}
else
{
location = cg->allocateSpill(4, false, NULL);
}
TR::MemoryReference * tempMR = generateS390MemoryReference(currentNode, location->getSymbolReference(), cg);
location->getSymbolReference()->getSymbol()->setSpillTempLoaded();
currentInstruction = generateRXInstruction(cg, opLoad, currentNode, sourceReg, tempMR, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
currentInstruction = generateRRInstruction(cg, opLoadReg, currentNode, targetReg, sourceReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
TR::MemoryReference * tempMR2 = generateS390MemoryReference(*tempMR, 0, cg);
currentInstruction = generateRXInstruction(cg, opStore, currentNode, targetReg, tempMR2, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
cg->freeSpill(location, TR::Compiler->om.sizeofReferenceAddress(), 0);
}
else
{
middleReg->setHasBeenAssignedInMethod(true);
currentInstruction =
generateRRInstruction(cg, opLoadReg, currentNode, sourceReg, middleReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
if (debugObj)
{
debugObj->addInstructionComment(toS390RRInstruction(currentInstruction), REG_EXCHANGE);
}
currentInstruction =
generateRRInstruction(cg, opLoadReg, currentNode, targetReg, sourceReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
if (debugObj)
{
debugObj->addInstructionComment(toS390RRInstruction(currentInstruction), REG_EXCHANGE);
}
currentInstruction =
generateRRInstruction(cg, opLoadReg, currentNode, middleReg, targetReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
if (debugObj)
{
debugObj->addInstructionComment(toS390RRInstruction(currentInstruction), REG_EXCHANGE);
}
}
cg->generateDebugCounter(precedingInstruction, "RegisterAllocator/Exchange/GPR", 1, TR::DebugCounter::Free);
}
if (middleReg)
{
cg->traceRegisterAssignment("registerExchange: %R and %R via %R", targetReg, sourceReg, middleReg);
}
else
{
cg->traceRegisterAssignment("registerExchange: %R and %R via memory", targetReg, sourceReg);
}
return currentInstruction;
}
static bool
boundNext(TR::Instruction * currentInstruction, int32_t realNum, TR::Register * virtReg)
{
TR::Instruction * cursor = currentInstruction;
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum) realNum;
TR::Node * nodeBBStart = NULL;
while (cursor->getOpCodeValue() != TR::InstOpCode::proc)
{
TR::RegisterDependencyConditions * conditions;
if ((conditions = cursor->getDependencyConditions()) != NULL)
{
TR::Register * boundReg = conditions->searchPostConditionRegister(realReg);
if (boundReg == NULL)
{
boundReg = conditions->searchPreConditionRegister(realReg);
}
if (boundReg != NULL)
{
if (boundReg == virtReg)
{
return true;
}
return false;
}
}
TR::Node * node = cursor->getNode();
if (nodeBBStart != NULL && node != nodeBBStart)
{
return true;
}
if (node != NULL && node->getOpCodeValue() == TR::BBStart)
{
TR::Block * block = node->getBlock();
if (!block->isExtensionOfPreviousBlock())
{
nodeBBStart = node;
}
}
cursor = cursor->getPrev();
// OOL entry label could cause this
if (!cursor)
return true;
}
return true;
}
uint8_t
OMR::Z::Machine::getGPRSize()
{
return self()->cg()->comp()->target().is64Bit() ? 8 : 4;
}
///////////////////////////////////////////////////////////////////////////////
// Constructor
OMR::Z::Machine::Machine(TR::CodeGenerator * cg)
: OMR::Machine(cg), _lastGlobalGPRRegisterNumber(-1), _last8BitGlobalGPRRegisterNumber(-1),
_lastGlobalFPRRegisterNumber(-1), _lastGlobalCCRRegisterNumber(-1), _lastVolatileNonLinkGPR(-1), _lastLinkageGPR(-1),
_lastVolatileNonLinkFPR(-1), _lastLinkageFPR(-1), _globalEnvironmentRegisterNumber(-1), _globalCAARegisterNumber(-1), _globalParentDSARegisterNumber(-1),
_globalReturnAddressRegisterNumber(-1),_globalEntryPointRegisterNumber(-1)
{
self()->initializeRegisterFile();
self()->initializeFPRegPairTable();
self()->clearRegisterAssociations();
}
/**
* This method implements a policy for finding the best swap register to be used
* when performing register exchange.
* It looks for blocked regs that are assigned dummy virt regs or for free regs.
* It is possible for this method to return NULL.
*/
TR::RealRegister *
OMR::Z::Machine::findBestSwapRegister(TR::Register* reg1, TR::Register* reg2)
{
TR_RegisterKinds rk = reg1->getKind();
int32_t first, last;
if (rk == TR_GPR)
{
first = TR::RealRegister::FirstGPR;
last = TR::RealRegister::LastAssignableGPR;
}
else if (rk == TR_FPR)
{
first = TR::RealRegister::FirstFPR;
last = TR::RealRegister::LastFPR;
}
else
{
first = TR::RealRegister::FirstVRF;
last = TR::RealRegister::LastVRF;
}
TR::RealRegister* realReg1 = toRealRegister(reg1->getAssignedRegister());
TR::RealRegister* realReg2 = toRealRegister(reg2->getAssignedRegister());
for (int32_t i = first; i <= last; i++)
{
if (
_registerFile[i]->getState() == TR::RealRegister::Blocked &&
_registerFile[i]->getAssignedRegister() != NULL &&
_registerFile[i]->getAssignedRegister()->isPlaceholderReg() &&
_registerFile[i] != realReg1 &&
_registerFile[i] != realReg2
)
{
return _registerFile[i];
}
}
// No luck. No use-able dummy reg found.
return NULL;
}
/**
* @return a bit map identifying assignable regs as 1's.
*/
uint32_t
OMR::Z::Machine::genBitMapOfAssignableGPRs()
{
uint32_t availRegMask = 0x0;
for (int32_t i = TR::RealRegister::FirstGPR; i <= TR::RealRegister::LastAssignableGPR; ++i)
{
if (_registerFile[i]->getState() != TR::RealRegister::Locked)
{
availRegMask |= _registerFile[i]->getRealRegisterMask();
}
}
return availRegMask;
}
/**
* @return a bit vector identifying live regs pairs as 1's.
*/
uint8_t
OMR::Z::Machine::genBitVectOfLiveGPRPairs()
{
uint8_t liveRegMask = 0x0;
for (int32_t i = TR::RealRegister::FirstGPR, j = 8; i <= TR::RealRegister::LastAssignableGPR; i += 2, --j)
{
if (_registerFile[i + 0]->getState() != TR::RealRegister::Free ||
_registerFile[i + 1]->getState() != TR::RealRegister::Free)
{
// MSB = GPR0/GPR1, LSB = GPR14/GPR15
liveRegMask |= _registerFile[j]->getRealRegisterMask();
}
}
return liveRegMask;
}
///////////////////////////////////////////////////////////////////////////////
// REGISTER PAIR assignment methods
///////////////////////////////////////////////////////////////////////////////
bool
OMR::Z::Machine::isLegalEvenOddPair(TR::RealRegister * evenReg, TR::RealRegister * oddReg, uint64_t availRegMask)
{
if (evenReg == NULL || oddReg == NULL)
{
return false;
}
else if (toRealRegister(evenReg)->getRegisterNumber() + 1 == toRealRegister(oddReg)->getRegisterNumber())
{
return self()->isLegalEvenRegister(evenReg, ALLOWBLOCKED, availRegMask) && self()->isLegalOddRegister(oddReg, ALLOWBLOCKED, availRegMask);
}
else
{
return false;
}
}
bool
OMR::Z::Machine::isLegalEvenRegister(TR::RealRegister * reg, bool allowBlocked, uint64_t availRegMask, bool allowLocked)
{
// Is the register assigned
if (reg == NULL)
{
return false;
}
// The reg num types are actually +1 off real reg due to NoReg taking
// up slot 0 in enumeration
int32_t regNum = toRealRegister(reg)->getRegisterNumber() - 1;
// Not a legal Even reg if 1) not even or 2) reg+1 is locked/blocked with non-sibling 3) using GPR0 when we shouldn't
if (regNum %
2 !=
0 ||
(toRealRegister(reg)->getRealRegisterMask() & availRegMask) ==
0 ||
_registerFile[toRealRegister(reg)->getRegisterNumber() + 1]->getState() ==
TR::RealRegister::Locked && allowLocked == false ||
(_registerFile[toRealRegister(reg)->getRegisterNumber() + 1]->getState() == TR::RealRegister::Blocked &&
allowBlocked == false))
{
return false;
}
else
{
return true;
}
}
bool
OMR::Z::Machine::isLegalFPPair(TR::RealRegister * firstReg, TR::RealRegister * secondReg, uint64_t availRegMask)
{
if (firstReg == NULL || secondReg == NULL)
{
return false;
}
else if (toRealRegister(firstReg)->getRegisterNumber() + 2 == toRealRegister(secondReg)->getRegisterNumber())
{
return self()->isLegalFirstOfFPRegister(firstReg, ALLOWBLOCKED, availRegMask) && self()->isLegalSecondOfFPRegister(secondReg, ALLOWBLOCKED, availRegMask);
}
else
{
return false;
}
}
bool
OMR::Z::Machine::isLegalFirstOfFPRegister(TR::RealRegister * reg, bool allowBlocked, uint64_t availRegMask, bool allowLocked)
{
// Is the register assigned
if (reg == NULL)
{
return false;
}
// The reg num types are actually +1 off real reg due to NoReg taking
// up slot 0 in enumeration
int32_t regNum = toRealRegister(reg)->getRegisterNumber() - 1;
// 1) must be one of FPR0, FPR4, FPR8, FPR12, FPR1, FPR5, FPR9, FPR13
// 2) its sibling FP Reg is NOT locked/blocked
if ((regNum % 4 != 0 && regNum % 4 != 1 ) ||
(toRealRegister(reg)->getRealRegisterMask() & availRegMask) == 0 ||
_registerFile[toRealRegister(reg)->getRegisterNumber() + 2]->getState() ==
TR::RealRegister::Locked && allowLocked == false ||
(_registerFile[toRealRegister(reg)->getRegisterNumber() + 2]->getState() == TR::RealRegister::Blocked &&
allowBlocked == false))
{
return false;
}
else
{
return true;
}
}
bool
OMR::Z::Machine::isLegalSecondOfFPRegister(TR::RealRegister * reg, bool allowBlocked, uint64_t availRegMask, bool allowLocked)
{
// Is the register assigned
if (reg == NULL)
{
return false;
}
// The reg num types are actually +1 off real reg due to NoReg taking
// up slot 0 in enumeration
int32_t regNum = toRealRegister(reg)->getRegisterNumber() - 1;
// Not a legal Even reg if 1) not even or 2) reg+1 is locked/blocked with non-sibling 3) using GPR0 when we shouldn't
// 1) must be one of FPR2, FPR6, FPR10, FPR14, FPR3, FPR7, FPR11, FPR15
// 2) its sibling FP Reg is NOT locked/blocked
if ((regNum % 4 != 2 && regNum % 4 != 3 ) ||
(toRealRegister(reg)->getRealRegisterMask() & availRegMask) == 0 ||
_registerFile[toRealRegister(reg)->getRegisterNumber() - 2]->getState() ==
TR::RealRegister::Locked && allowLocked == false ||
(_registerFile[toRealRegister(reg)->getRegisterNumber() - 2]->getState() == TR::RealRegister::Blocked &&
allowBlocked == false))
{
return false;
}
else
{
return true;
}
}
/**
* Try to grab an ODD register who's EVEN pred is unlocked and free.
* If this fails, return the last ODD reg who's EVEN pred is not locked.
*/
TR::RealRegister *
OMR::Z::Machine::findBestLegalOddRegister(uint64_t availRegMask)
{
uint32_t bestWeightSoFar = 0xFFFFFFFF;
TR::RealRegister * freeRegister = NULL;
TR::RealRegister * lastOddReg = NULL;
bool foundFreePair = false;
for (int32_t i = TR::RealRegister::FirstGPR + 1; i <= TR::RealRegister::LastAssignableGPR; i += 2)
{
// Don't consider registers that can't be assigned
if (_registerFile[i - 1]->getState() == TR::RealRegister::Locked ||
_registerFile[i - 0]->getState() == TR::RealRegister::Locked ||
_registerFile[i - 1]->getState() == TR::RealRegister::Blocked ||
_registerFile[i - 0]->getState() == TR::RealRegister::Blocked ||
(_registerFile[i - 0]->getRealRegisterMask() & availRegMask) == 0 ||
(_registerFile[i - 1]->getRealRegisterMask() & availRegMask) == 0)
{
continue;
}
lastOddReg = _registerFile[i];
if ((_registerFile[i - 0]->getState() == TR::RealRegister::Free || _registerFile[i - 0]->getState() == TR::RealRegister::Unlatched) &&
(_registerFile[i - 1]->getState() == TR::RealRegister::Free || _registerFile[i - 1]->getState() == TR::RealRegister::Unlatched) &&
_registerFile[i - 0]->getWeight() < bestWeightSoFar)
{
// Always prioritize a free pair
foundFreePair = true;
freeRegister = _registerFile[i];
bestWeightSoFar = _registerFile[i]->getWeight();
}
else if (foundFreePair == false &&
(_registerFile[i]->getState() == TR::RealRegister::Free || _registerFile[i]->getState() == TR::RealRegister::Unlatched) &&
_registerFile[i]->getWeight() < bestWeightSoFar)
{
freeRegister = _registerFile[i];
bestWeightSoFar = freeRegister->getWeight();
}
}
if (freeRegister == NULL)
{
if (lastOddReg)
self()->cg()->traceRegisterAssignment("BEST LEGAL ODD: %R", lastOddReg);
return lastOddReg;
}
else
{
self()->cg()->traceRegisterAssignment("BEST LEGAL ODD: %R", freeRegister);
return freeRegister;
}
}
bool
OMR::Z::Machine::isLegalOddRegister(TR::RealRegister * reg, bool allowBlocked, uint64_t availRegMask, bool allowLocked)
{
// Is the register assigned
if (reg == NULL)
{
return false;
}
// The reg num types are actually +1 off real reg due to NoReg taking
// up slot 0 in enumeration
int32_t regNum = toRealRegister(reg)->getRegisterNumber() - 1;
// Not a legal Even reg if 1) not odd or 2) reg+1 is locked
if (regNum % 2 != 1 ||
(toRealRegister(reg)->getRealRegisterMask() & availRegMask) == 0 ||
_registerFile[toRealRegister(reg)->getRegisterNumber() - 1]->getState() == TR::RealRegister::Locked && allowLocked == false ||
(_registerFile[toRealRegister(reg)->getRegisterNumber() - 1]->getState() == TR::RealRegister::Blocked &&
allowBlocked == false))
{
return false;
}
else
{
return true;
}
}
/**
* Try to grab an EVEN register who's ODD succ is unlocked and free.
* If this fails, return the last EVEN reg who's ODD pred is not locked.
*/
TR::RealRegister *
OMR::Z::Machine::findBestLegalEvenRegister(uint64_t availRegMask)
{
uint32_t bestWeightSoFar = 0xFFFFFFFF;
TR::RealRegister * freeRegister = NULL;
TR::RealRegister * lastEvenReg = NULL;
bool foundFreePair = false;
for (int32_t i = TR::RealRegister::FirstGPR; i <= TR::RealRegister::LastAssignableGPR; i += 2)
{
// Don't consider registers that can't be assigned.
if (_registerFile[i + 0]->getState() == TR::RealRegister::Locked ||
_registerFile[i + 1]->getState() == TR::RealRegister::Locked ||
_registerFile[i + 0]->getState() == TR::RealRegister::Blocked ||
_registerFile[i + 1]->getState() == TR::RealRegister::Blocked ||
(_registerFile[i + 0]->getRealRegisterMask() & availRegMask) == 0 ||
(_registerFile[i + 1]->getRealRegisterMask() & availRegMask) == 0)
{
continue;
}
lastEvenReg = _registerFile[i];
//self()->cg()->traceRegWeight(lastEvenReg, lastEvenReg->getWeight());
if ((_registerFile[i + 0]->getState() == TR::RealRegister::Free || _registerFile[i + 0]->getState() == TR::RealRegister::Unlatched) &&
(_registerFile[i + 1]->getState() == TR::RealRegister::Free || _registerFile[i + 1]->getState() == TR::RealRegister::Unlatched) &&
_registerFile[i + 0]->getWeight() < bestWeightSoFar)
{
// Always prioritize a free pair
foundFreePair = true;
freeRegister = _registerFile[i];
bestWeightSoFar = _registerFile[i]->getWeight();
}
else if (foundFreePair == false &&
(_registerFile[i]->getState() == TR::RealRegister::Free || _registerFile[i]->getState() == TR::RealRegister::Unlatched) &&
_registerFile[i]->getWeight() < bestWeightSoFar)
{
freeRegister = _registerFile[i];
bestWeightSoFar = freeRegister->getWeight();
}
}
if (freeRegister == NULL)
{
if (lastEvenReg)
self()->cg()->traceRegisterAssignment("BEST LAST LEGAL EVEN: %R", lastEvenReg);
return lastEvenReg;
}
else
{
self()->cg()->traceRegisterAssignment("BEST LEGAL EVEN: %R", freeRegister);
return freeRegister;
}
}
/**
* Try to grab a legal high/low FP register who's sibling is unlocked and free.
* If this fails, return the last high/low reg whose sibling pred is not locked.
*/
TR::RealRegister *
OMR::Z::Machine::findBestLegalSiblingFPRegister(bool isFirst, uint64_t availRegMask)
{
uint32_t bestWeightSoFar = 0xFFFFFFFF;
TR::RealRegister * freeRegister = NULL;
TR::RealRegister * lastFirstOfPair = NULL;
TR::RealRegister * lastSecondOfPair = NULL;
TR::RealRegister * lastSiblingFPReg = NULL;
bool foundFreePair = false;
for (int32_t i = 0; i < NUM_S390_FPR_PAIRS; i++)
{
TR::RealRegister::RegNum firstReg = _S390FirstOfFPRegisterPairs[i];
TR::RealRegister::RegNum secondReg = _S390SecondOfFPRegisterPairs[i];
// Don't consider registers that can't be assigned.
if (_registerFile[firstReg]->getState() == TR::RealRegister::Locked
|| _registerFile[secondReg]->getState() == TR::RealRegister::Locked
|| _registerFile[firstReg]->getState() == TR::RealRegister::Blocked
|| _registerFile[secondReg]->getState() == TR::RealRegister::Blocked
|| (_registerFile[firstReg]->getRealRegisterMask() & availRegMask) == 0
|| (_registerFile[secondReg]->getRealRegisterMask() & availRegMask) == 0)
{
continue;
}
lastFirstOfPair = _registerFile[firstReg];
lastSecondOfPair = _registerFile[secondReg];
lastSiblingFPReg = isFirst ? lastFirstOfPair : lastSecondOfPair;
//self()->cg()->traceRegWeight(lastSiblingFPReg, lastSiblingFPReg->getWeight());
if ((lastFirstOfPair->getState() == TR::RealRegister::Free || lastFirstOfPair->getState() == TR::RealRegister::Unlatched)
&& (lastSecondOfPair->getState() == TR::RealRegister::Free || lastSecondOfPair->getState() == TR::RealRegister::Unlatched)
&& (lastSiblingFPReg->getWeight() < bestWeightSoFar))
{
foundFreePair = true; // Always prioritize a free pair
freeRegister = lastSiblingFPReg;
bestWeightSoFar = lastSiblingFPReg->getWeight();
}
else if (foundFreePair == false &&
(lastSiblingFPReg->getState() == TR::RealRegister::Free || lastSiblingFPReg->getState() == TR::RealRegister::Unlatched)
&& lastSiblingFPReg->getWeight() < bestWeightSoFar)
{
freeRegister = lastSiblingFPReg;
bestWeightSoFar = freeRegister->getWeight();
}
}
if (freeRegister == NULL)
{
self()->cg()->traceRegisterAssignment("BEST LEGAL sibling FP Reg: %R", lastSiblingFPReg);
return lastSiblingFPReg;
}
else
{
self()->cg()->traceRegisterAssignment("BEST LEGAL sibling FP Reg: %R", freeRegister);
return freeRegister;
}
}
/**
* Register Assignment Interface
*
* We assign any type of register (pair).
* Assign the best register to the virt target register
* @return the real reg that gets assigned. For a pair, it returns a new placeholder for
* the pair. The real regs are double linked to associated virt regs.
*/
TR::Register *
OMR::Z::Machine::assignBestRegister(TR::Register *targetRegister,
TR::Instruction *currInst,
bool doBookKeeping,
uint64_t availRegMask)
{
TR::Register * returnRegister = 0;
TR::RegisterPair *rp=targetRegister->getRegisterPair();
if (rp)
{
returnRegister = self()->assignBestRegisterPair(targetRegister, currInst, doBookKeeping, availRegMask);
}
else
{
returnRegister = self()->assignBestRegisterSingle(targetRegister, currInst, doBookKeeping, availRegMask);
}
return returnRegister;
}
TR::RealRegister *
OMR::Z::Machine::findBestRegisterForShuffle(TR::Instruction *currentInstruction,
TR::Register *currentAssignedRegister,
uint64_t availRegMask)
{
TR_ASSERT(currentAssignedRegister, "Register shuffling at instruction %P, but the register is not currently assigned?\n",currentInstruction);
TR_RegisterKinds kindOfRegister = currentAssignedRegister->getKind();
TR::RealRegister *newRegister = NULL;
// we need to make sure we do not use same register that is assigned to this instruction for shuffling
// Usually, other real registers assigned to the current instruction are block, except in situation where
// we have exact one, non-pair target register. So temporary block it if it is not blocked already
bool blockingRegister = false;
TR::Register * targetRegister = currentInstruction->getRegisterOperand(1);
if (targetRegister &&
targetRegister->getRealRegister() &&
targetRegister->getRealRegister()->getState() != TR::RealRegister::Blocked)
{
targetRegister->getRealRegister()->block();
blockingRegister = true;
}
// find a free register
if ((newRegister = self()->findBestFreeRegister(currentInstruction, kindOfRegister, currentAssignedRegister, availRegMask)) == NULL)
{
newRegister = self()->freeBestRegister(currentInstruction, currentAssignedRegister, kindOfRegister);
}
// unblock if we blocked target reg of the instruction
if (blockingRegister)
targetRegister->getRealRegister()->unblock();
self()->cg()->traceRegisterAssignment("%R is assigned to invalid register in this instruction. Shuffling %R => %R...",
currentAssignedRegister, currentAssignedRegister->getAssignedRegister(), newRegister);
return newRegister;
}
/**
* try to shuffle the virt reg to another real reg or spill that virtual register
@return if the virtual reg was shuffled, the real reg that it was shuffled to, otherwise NULL
*/
TR::RealRegister *
OMR::Z::Machine::shuffleOrSpillRegister(TR::Instruction *currInst,
TR::Register *toFreeReg,
uint64_t availRegMask)
{
TR::RealRegister * assignedRegister = toFreeReg->getAssignedRealRegister();
if (toFreeReg->isUsedInMemRef())
{
availRegMask &= ~TR::RealRegister::GPR0Mask;
}
TR::RealRegister * bestRegister = self()->findBestFreeRegister(currInst, toFreeReg->getKind(), toFreeReg, availRegMask);
if (bestRegister == NULL)
self()->spillRegister(currInst, toFreeReg);
else
{
TR::Instruction * cursor = self()->registerCopy(self()->cg(), toFreeReg->getKind(), assignedRegister, bestRegister, currInst);
toFreeReg->setAssignedRegister(bestRegister);
bestRegister->setAssignedRegister(toFreeReg);
bestRegister->setState(TR::RealRegister::Assigned);
assignedRegister->setAssignedRegister(NULL);
assignedRegister->setState(TR::RealRegister::Unlatched);
}
return bestRegister;
}
/**
* Assign the best register to the virt target register
* @return the real reg that gets assigned
*/
TR::Register *
OMR::Z::Machine::assignBestRegisterSingle(TR::Register *targetRegister,
TR::Instruction *currInst,
bool doBookKeeping,
uint64_t availRegMask)
{
TR_RegisterKinds kindOfRegister = targetRegister->getKind();
TR::RealRegister * assignedRegister = targetRegister->getAssignedRealRegister();
TR::Compilation *comp = self()->cg()->comp();
bool reverseSpilled = false;
bool defsRegister=currInst->defsRegister(targetRegister);
if (assignedRegister == NULL)
{
if (self()->cg()->insideInternalControlFlow())
{
TR_ASSERT_FATAL(false, "Attempting to assign a register (%s) inside ICF", getRegisterName(targetRegister, self()->cg()));
}
}
if (kindOfRegister != TR_FPR && kindOfRegister != TR_VRF && assignedRegister != NULL)
{
if ((assignedRegister->getRealRegisterMask() & availRegMask) == 0)
{
// Oh no.. targetRegister is assigned something it shouldn't be assigned to. Do some shuffling
// find a new register to shuffle to
TR::RealRegister * newAssignedRegister = self()->findBestRegisterForShuffle(currInst, targetRegister, availRegMask);
TR::Instruction *cursor = self()->registerCopy(self()->cg(), kindOfRegister, toRealRegister(assignedRegister), newAssignedRegister, currInst);
targetRegister->setAssignedRegister(newAssignedRegister);
newAssignedRegister->setAssignedRegister(targetRegister);
newAssignedRegister->setState(TR::RealRegister::Assigned);
assignedRegister->setAssignedRegister(NULL);
assignedRegister->setState(TR::RealRegister::Free);
assignedRegister = newAssignedRegister;
}
}
else if (assignedRegister != NULL && (assignedRegister->getRealRegisterMask() & availRegMask) == 0)
{
// Oh no.. targetRegister is assigned something it shouldn't be assigned to
// Do some shuffling
// find a new register to shuffle to
assignedRegister->block();
TR::RealRegister * newAssignedRegister = self()->findBestRegisterForShuffle(currInst, targetRegister, availRegMask);
assignedRegister->unblock();
TR::Instruction *cursor=self()->registerCopy(self()->cg(), kindOfRegister, assignedRegister, newAssignedRegister, currInst);