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FPTreeEvaluator.cpp
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FPTreeEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include "arm/codegen/ARMInstruction.hpp"
#include "codegen/BackingStore.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/CodeGeneratorUtils.hpp"
#include "codegen/GenerateInstructions.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Machine.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "env/CompilerEnv.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
// Helpers
static bool noFPRA = false; // The current RA *does* seem to assign FP regs. Shall we change this to false?
static TR::Register *moveToFloatRegister(TR::Node *node, TR::Register *srcReg, TR::CodeGenerator *cg)
{
// Move from regular registers to single floating point register
if (srcReg->getKind() == TR_FPR)
{
TR_ASSERT(srcReg->isSinglePrecision(), "Expecting a single precision register\n");
return srcReg;
}
else // GPR
{
TR::Register *trgReg = cg->allocateSinglePrecisionRegister();
generateTrg1Src1Instruction(cg, ARMOp_fmsr, node, trgReg, srcReg);
return trgReg;
}
}
static TR::Register *moveToDoubleRegister(TR::Node *node, TR::Register *srcReg, TR::CodeGenerator *cg)
{
if (srcReg->getKind() == TR_FPR)
{
TR_ASSERT(!srcReg->isSinglePrecision(), "Expecting a double precision register\n");
return srcReg;
}
else // GPR
{
TR::Register *trgReg = cg->allocateRegister(TR_FPR);
TR::RegisterPair *pair = srcReg->getRegisterPair();
generateTrg1Src2Instruction(cg, ARMOp_fmdrr, node, trgReg, pair->getLowOrder(), pair->getHighOrder());
return trgReg;
}
}
static TR::Register *moveFromFloatRegister(TR::Node *node, TR::Register *srcReg, TR::CodeGenerator *cg)
{
TR::Register *trgReg = cg->allocateRegister();
generateTrg1Src1Instruction(cg, ARMOp_fmrs, node, trgReg, srcReg);
return trgReg;
}
static TR::Register *moveFromDoubleRegister(TR::Node *node, TR::Register *srcReg, TR::CodeGenerator *cg)
{
TR::Register *lowReg = cg->allocateRegister();
TR::Register *highReg = cg->allocateRegister();
TR::RegisterPair *trgReg = cg->allocateRegisterPair(lowReg, highReg);
generateTrg2Src1Instruction(cg, ARMOp_fmrrd, node, lowReg, highReg, srcReg);
return trgReg;
}
static bool resultCanStayInFloatRegister(TR::Node *checkNode, TR::Node *node)
{
bool result = true;
TR::Node *child= NULL;
static bool disableVFPOpt = (feGetEnv("TR_DisableVFPOpt") != NULL);
if (disableVFPOpt)
return false;
/* TODO: Memo - Below may hurt GRA when regassign for FP/Double is enabled in future. */
if (node->getReferenceCount() > 1)
result = false;
for (uint16_t i = 0; i < checkNode->getNumChildren() && result; i++)
{
child = checkNode->getChild(i);
if (child->getOpCode().isCall())
result = false;
else if (checkNode->getOpCodeValue() == TR::fstore && node->getOpCodeValue() == TR::fload)
result = false;
/*
else if (checkNode->getOpCodeValue() == TR::dstore && node->getOpCodeValue() == TR::dload)
result = false;
*/
else
result = resultCanStayInFloatRegister(child, node);
if (!result || child == node)
break;
}
return result;
}
static TR::Register *singlePrecisionEvaluator(TR::Node *node, TR_ARMOpCodes opCode, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = NULL;
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = NULL;
TR::Register *floatTrgReg = cg->allocateSinglePrecisionRegister();
TR::Register *trgReg = NULL;
TR_ASSERT(node->getNumChildren() <= 2, "Not expecting more than 2 children in this node\n");
if (node->getNumChildren() == 2)
{
secondChild = node->getSecondChild();
src2Reg = cg->evaluate(secondChild);
generateTrg1Src2Instruction(cg, opCode, node, floatTrgReg, moveToFloatRegister(node, src1Reg, cg), moveToFloatRegister(node, src2Reg, cg));
}
else // 1 child
{
generateTrg1Src1Instruction(cg, opCode, node, floatTrgReg, moveToFloatRegister(node, src1Reg, cg));
}
// Test with no RA, put values back in general registers, conforming to ABI
if (noFPRA)
{
if (resultCanStayInFloatRegister(cg->getCurrentEvaluationTreeTop()->getNode(), node))
{
traceMsg(cg->comp(), "Result of node %p can stay in FP reg.\n", node);
trgReg = floatTrgReg;
}
else
{
trgReg = moveFromFloatRegister(node, floatTrgReg, cg);
cg->stopUsingRegister(floatTrgReg);
}
}
else
trgReg = floatTrgReg;
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
if (node->getNumChildren() == 2)
cg->decReferenceCount(secondChild);
return trgReg;
}
static TR::Register *doublePrecisionEvaluator(TR::Node *node, TR_ARMOpCodes opCode, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = NULL;
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = NULL;
TR::Register *doubleTrgReg = cg->allocateRegister(TR_FPR);
TR::Register *trgReg = NULL;
TR_ASSERT(node->getNumChildren() <= 2, "Not expecting more than 2 children in this node\n");
//TR_ASSERT(src1Reg->getRegisterPair(), "Expecting double value in a register pair\n");
if (node->getNumChildren() == 2)
{
secondChild = node->getSecondChild();
src2Reg = cg->evaluate(secondChild);
//TR_ASSERT(src2Reg->getRegisterPair(), "Expecting double value in a register pair\n");
generateTrg1Src2Instruction(cg, opCode, node, doubleTrgReg, moveToDoubleRegister(node, src1Reg, cg), moveToDoubleRegister(node, src2Reg, cg));
}
else // 1 child
{
generateTrg1Src1Instruction(cg, opCode, node, doubleTrgReg, moveToDoubleRegister(node, src1Reg, cg));
}
// Test with no RA, put values back in general registers, conforming to ABI
if (noFPRA)
{
if (resultCanStayInFloatRegister(cg->getCurrentEvaluationTreeTop()->getNode(), node))
{
traceMsg(cg->comp(), "Result of node %p can stay in FP reg.\n", node);
trgReg = doubleTrgReg;
}
else
{
trgReg = moveFromDoubleRegister(node, doubleTrgReg, cg);
cg->stopUsingRegister(doubleTrgReg);
}
}
else
trgReg = doubleTrgReg;
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
if (node->getNumChildren() == 2)
cg->decReferenceCount(secondChild);
return trgReg;
}
static TR::Register *callLong2DoubleHelper(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *srcReg = cg->evaluate(child);
TR::RegisterDependencyConditions *dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(10, 10, cg->trMemory());
int i;
TR::Register *highReg = cg->allocateRegister();
TR::Register *lowReg = cg->allocateRegister();
#if defined(__ARM_PCS_VFP)
TR::Register *trgReg = cg->allocateRegister(TR_FPR);
#else
TR::Register *trgReg = cg->allocateRegisterPair(lowReg, highReg);
#endif
TR::Register *doubleTrgReg = NULL;
if (cg->comp()->target().cpu.isLittleEndian())
{
/* Little Endian */
dependencies->addPreCondition(srcReg->getHighOrder(), TR::RealRegister::gr1);
dependencies->addPreCondition(srcReg->getLowOrder(), TR::RealRegister::gr0);
#if defined(__ARM_PCS_VFP)
dependencies->addPostCondition(trgReg, TR::RealRegister::fp0);
for (i = 1; i < 8; i++)
{
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)((uint32_t)TR::RealRegister::fp0 + i);
dependencies->addPostCondition(cg->allocateRegister(TR_FPR), realReg);//TODO live register
}
dependencies->addPostCondition(cg->allocateRegister(), TR::RealRegister::gr1);//TODO live register
dependencies->addPostCondition(cg->allocateRegister(), TR::RealRegister::gr0);//TODO live register
#else
dependencies->addPostCondition(trgReg->getHighOrder(), TR::RealRegister::gr1);
dependencies->addPostCondition(trgReg->getLowOrder(), TR::RealRegister::gr0);
#endif
}
else
{
/* Big Endian */
dependencies->addPreCondition(srcReg->getHighOrder(), TR::RealRegister::gr0);
dependencies->addPreCondition(srcReg->getLowOrder(), TR::RealRegister::gr1);
#if defined(__ARM_PCS_VFP)
dependencies->addPostCondition(trgReg, TR::RealRegister::fp0);
for (i = 1; i < 8; i++)
{
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)((uint32_t)TR::RealRegister::fp0 + i);
dependencies->addPostCondition(cg->allocateRegister(TR_FPR), realReg);//TODO live register
}
dependencies->addPostCondition(cg->allocateRegister(), TR::RealRegister::gr0);//TODO live register
dependencies->addPostCondition(cg->allocateRegister(), TR::RealRegister::gr1);//TODO live register
#else
dependencies->addPostCondition(trgReg->getHighOrder(), TR::RealRegister::gr0);
dependencies->addPostCondition(trgReg->getLowOrder(), TR::RealRegister::gr1);
#endif
}
dependencies->stopAddingConditions();
generateImmSymInstruction(cg, ARMOp_bl,
node, (uintptr_t)cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMlong2Double)->getMethodAddress(),
dependencies,
cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMlong2Double));
if (noFPRA)
{
#if defined(__ARM_PCS_VFP)
if (resultCanStayInFloatRegister(cg->getCurrentEvaluationTreeTop()->getNode(), node))
{
traceMsg(cg->comp(), "Result of node %p can stay in FP reg.\n", node);
doubleTrgReg = trgReg;
}
else
{
doubleTrgReg = moveFromDoubleRegister(node, trgReg, cg);
cg->stopUsingRegister(trgReg);
}
#else
doubleTrgReg = trgReg;
#endif
}
else
doubleTrgReg = trgReg;
cg->decReferenceCount(child);
cg->machine()->setLinkRegisterKilled(true);
return doubleTrgReg;
}
static TR::Register *callLong2FloatHelper(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *srcReg = cg->evaluate(child);
TR::RegisterDependencyConditions *dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(10, 10, cg->trMemory());
int i;
#if defined(__ARM_PCS_VFP)
TR::Register *trgReg = cg->allocateSinglePrecisionRegister();
#else
TR::Register *trgReg = cg->allocateRegister(); // Callout follows soft-float abi
#endif
TR::Register *floatTrgReg = NULL;
if (cg->comp()->target().cpu.isLittleEndian())
{
/* Little Endian */
dependencies->addPreCondition(srcReg->getHighOrder(), TR::RealRegister::gr1);
dependencies->addPreCondition(srcReg->getLowOrder(), TR::RealRegister::gr0);
#if defined(__ARM_PCS_VFP)
dependencies->addPostCondition(trgReg, TR::RealRegister::fp0);
for (i = 1; i < 8; i++)
{
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)((uint32_t)TR::RealRegister::fp0 + i);
dependencies->addPostCondition(cg->allocateSinglePrecisionRegister(), realReg);//TODO live register
}
dependencies->addPostCondition(cg->allocateRegister(), TR::RealRegister::gr1);//TODO live register
dependencies->addPostCondition(cg->allocateRegister(), TR::RealRegister::gr0);//TODO live register
#else
dependencies->addPostCondition(cg->allocateRegister(), TR::RealRegister::gr1);//TODO live register
dependencies->addPostCondition(trgReg, TR::RealRegister::gr0);
#endif
}
else
{
/* Big Endian */
dependencies->addPreCondition(srcReg->getHighOrder(), TR::RealRegister::gr0);
dependencies->addPreCondition(srcReg->getLowOrder(), TR::RealRegister::gr1);
#if defined(__ARM_PCS_VFP)
dependencies->addPostCondition(trgReg, TR::RealRegister::fp0);
for (i = 1; i < 8; i++)
{
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)((uint32_t)TR::RealRegister::fp0 + i);
dependencies->addPostCondition(cg->allocateSinglePrecisionRegister(), realReg);//TODO live register
}
dependencies->addPostCondition(cg->allocateRegister(), TR::RealRegister::gr0);//TODO live register
dependencies->addPostCondition(cg->allocateRegister(), TR::RealRegister::gr1);//TODO live register
#else
dependencies->addPostCondition(trgReg, TR::RealRegister::gr0);
dependencies->addPostCondition(cg->allocateRegister(), TR::RealRegister::gr1);//TODO live register
#endif
}
dependencies->stopAddingConditions();
generateImmSymInstruction(cg, ARMOp_bl,
node, (uintptr_t)cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMlong2Float)->getMethodAddress(),
dependencies,
cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMlong2Float));
if (noFPRA)
{
#if defined(__ARM_PCS_VFP)
if (resultCanStayInFloatRegister(cg->getCurrentEvaluationTreeTop()->getNode(), node))
{
traceMsg(cg->comp(), "Result of node %p can stay in FP reg.\n", node);
floatTrgReg = trgReg;
}
else
{
floatTrgReg = moveFromFloatRegister(node, trgReg, cg);
cg->stopUsingRegister(trgReg);
}
#else
floatTrgReg = trgReg;
#endif
}
else
floatTrgReg = trgReg;
cg->decReferenceCount(child);
cg->machine()->setLinkRegisterKilled(true);
return floatTrgReg;
}
static TR::Register *callDouble2LongHelper(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *doubleSrcReg = cg->evaluate(child);
TR::Register *srcReg = NULL;
TR::RegisterDependencyConditions *dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(11, 11, cg->trMemory());
int i;
TR::Register *highReg = cg->allocateRegister();
TR::Register *lowReg = cg->allocateRegister();
TR::Register *trgReg = cg->allocateRegisterPair(lowReg, highReg);
#if defined(__ARM_PCS_VFP) // hard fp
if (doubleSrcReg->getKind() == TR_GPR)
{
srcReg = moveToDoubleRegister(node, doubleSrcReg, cg);
}
else if (doubleSrcReg->getKind() == TR_FPR)
{
srcReg = doubleSrcReg;
}
else
TR_ASSERT(0, "Unknown register type\n");
#else // soft fp
if (doubleSrcReg->getKind() == TR_GPR)
{
srcReg = doubleSrcReg;
}
else if (doubleSrcReg->getKind() == TR_FPR)
{
srcReg = moveFromDoubleRegister(node, doubleSrcReg, cg);
}
else
TR_ASSERT(0, "Unknown register type\n");
#endif
if (cg->comp()->target().cpu.isLittleEndian())
{
/* Little Endian */
#if defined(__ARM_PCS_VFP)
dependencies->addPreCondition(cg->allocateRegister(), TR::RealRegister::gr0);//TODO live register
dependencies->addPreCondition(cg->allocateRegister(), TR::RealRegister::gr1);//TODO live register
dependencies->addPreCondition(srcReg, TR::RealRegister::fp0);
for (i = 0; i < 8; i++)
{
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)((uint32_t)TR::RealRegister::fp0 + i);
dependencies->addPostCondition(cg->allocateRegister(TR_FPR), realReg);//TODO live register
}
#else
dependencies->addPreCondition(srcReg->getHighOrder(), TR::RealRegister::gr1);
dependencies->addPreCondition(srcReg->getLowOrder(), TR::RealRegister::gr0);
#endif
dependencies->addPostCondition(trgReg->getLowOrder(), TR::RealRegister::gr0);
dependencies->addPostCondition(trgReg->getHighOrder(), TR::RealRegister::gr1);
}
else
{
/* Big Endian */
#if defined(__ARM_PCS_VFP)
dependencies->addPreCondition(cg->allocateRegister(), TR::RealRegister::gr0);//TODO live register
dependencies->addPreCondition(cg->allocateRegister(), TR::RealRegister::gr1);//TODO live register
dependencies->addPreCondition(srcReg, TR::RealRegister::fp0);
for (i = 0; i < 8; i++)
{
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)((uint32_t)TR::RealRegister::fp0 + i);
dependencies->addPostCondition(cg->allocateRegister(TR_FPR), realReg);//TODO live register
}
#else
dependencies->addPreCondition(srcReg->getHighOrder(), TR::RealRegister::gr0);
dependencies->addPreCondition(srcReg->getLowOrder(), TR::RealRegister::gr1);
#endif
dependencies->addPostCondition(trgReg->getHighOrder(), TR::RealRegister::gr0);
dependencies->addPostCondition(trgReg->getLowOrder(), TR::RealRegister::gr1);
}
TR::addDependency(dependencies, NULL, TR::RealRegister::gr2, TR_GPR, cg); // Block r2
dependencies->stopAddingConditions();
generateImmSymInstruction(cg, ARMOp_bl,
node, (uintptr_t)cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMdouble2Long)->getMethodAddress(),
dependencies,
cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMdouble2Long));
//dependencies->stopUsingDepRegs(cg, trgReg);
cg->decReferenceCount(child);
cg->machine()->setLinkRegisterKilled(true);
return trgReg;
}
static TR::Register *callFloat2LongHelper(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *floatSrcReg = cg->evaluate(child);
TR::Register *srcReg = NULL;
TR::RegisterDependencyConditions *dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(11, 11, cg->trMemory());
int i;
TR::Register *highReg = cg->allocateRegister();
TR::Register *lowReg = cg->allocateRegister();
TR::Register *trgReg = cg->allocateRegisterPair(lowReg, highReg);
#if defined(__ARM_PCS_VFP)
if (floatSrcReg->getKind() == TR_GPR)
{
srcReg = moveToFloatRegister(node, floatSrcReg, cg);
}
else if (floatSrcReg->getKind() == TR_FPR)
{
srcReg = floatSrcReg;
}
else
TR_ASSERT(0, "Unknown register type\n");
#else //soft fp
if (floatSrcReg->getKind() == TR_GPR)
{
srcReg = floatSrcReg;
}
else if (floatSrcReg->getKind() == TR_FPR)
{
srcReg = moveFromFloatRegister(node, floatSrcReg, cg);
}
else
TR_ASSERT(0, "Unknown register type\n");
#endif
if (cg->comp()->target().cpu.isLittleEndian())
{
/* Little Endian */
#if defined(__ARM_PCS_VFP)
dependencies->addPreCondition(cg->allocateRegister(), TR::RealRegister::gr0);//TODO live register
dependencies->addPreCondition(srcReg, TR::RealRegister::fp0);
for (i = 0; i < 8; i++)
{
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)((uint32_t)TR::RealRegister::fp0 + i);
dependencies->addPostCondition(cg->allocateSinglePrecisionRegister(), realReg);//TODO live register
}
#else
dependencies->addPreCondition(srcReg, TR::RealRegister::gr0);
#endif
dependencies->addPreCondition(cg->allocateRegister(), TR::RealRegister::gr1);//TODO live register
dependencies->addPostCondition(trgReg->getHighOrder(), TR::RealRegister::gr1);
dependencies->addPostCondition(trgReg->getLowOrder(), TR::RealRegister::gr0);
}
else
{
/* Big Endian */
#if defined(__ARM_PCS_VFP)
dependencies->addPreCondition(cg->allocateRegister(), TR::RealRegister::gr0);//TODO live register
dependencies->addPreCondition(srcReg, TR::RealRegister::fp0);
for (i = 0; i < 8; i++)
{
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)((uint32_t)TR::RealRegister::fp0 + i);
dependencies->addPostCondition(cg->allocateSinglePrecisionRegister(), realReg);//TODO live register
}
#else
dependencies->addPreCondition(srcReg, TR::RealRegister::gr0);
#endif
dependencies->addPreCondition(cg->allocateRegister(), TR::RealRegister::gr1);//TODO live register
dependencies->addPostCondition(trgReg->getHighOrder(), TR::RealRegister::gr0);
dependencies->addPostCondition(trgReg->getLowOrder(), TR::RealRegister::gr1);
}
TR::addDependency(dependencies, NULL, TR::RealRegister::gr2, TR_GPR, cg); // Block r2
dependencies->stopAddingConditions();
generateImmSymInstruction(cg, ARMOp_bl,
node, (uintptr_t)cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMfloat2Long)->getMethodAddress(),
dependencies,
cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMfloat2Long));
//dependencies->stopUsingDepRegs(cg, trgReg);
//cg->stopUsingRegister(dummyReg);
cg->decReferenceCount(child);
cg->machine()->setLinkRegisterKilled(true);
return trgReg;
}
static TR::Register *callDoubleRemainderHelper(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::RegisterDependencyConditions *dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(10, 10, cg->trMemory());
int i;
TR::Register *highReg = cg->allocateRegister();
TR::Register *lowReg = cg->allocateRegister();
#if defined(__ARM_PCS_VFP)
TR::Register *trgReg = cg->allocateRegister(TR_FPR);
#else
TR::Register *trgReg = cg->allocateRegisterPair(lowReg, highReg);
#endif
TR::Register *doubleTrgReg = NULL;
#if defined(__ARM_PCS_VFP)
if (src1Reg->getKind() == TR_GPR)
{
src1Reg = moveToDoubleRegister(node, src1Reg, cg);
}
if (src2Reg->getKind() == TR_GPR)
{
src2Reg = moveToDoubleRegister(node, src2Reg, cg);
}
#else
if (src1Reg->getKind() == TR_FPR)
{
src1Reg = moveFromDoubleRegister(node, src1Reg, cg);
}
if (src2Reg->getKind() == TR_FPR)
{
src2Reg = moveFromDoubleRegister(node, src2Reg, cg);
}
#endif
if(!noFPRA)
{
if((src1Reg->getKind() == TR_FPR) && !cg->canClobberNodesRegister(firstChild, 0))
{
TR::Register *tempReg = cg->allocateRegister(TR_FPR);
generateTrg1Src1Instruction(cg, ARMOp_fcpyd, firstChild, tempReg, src1Reg);
src1Reg = tempReg;
}
if((src2Reg->getKind() == TR_FPR) && !cg->canClobberNodesRegister(secondChild, 0))
{
TR::Register *tempReg = cg->allocateRegister(TR_FPR);
generateTrg1Src1Instruction(cg, ARMOp_fcpyd, secondChild, tempReg, src2Reg);
src2Reg = tempReg;
}
}
if (cg->comp()->target().cpu.isLittleEndian())
{
/* Little Endian */
#if defined(__ARM_PCS_VFP)
TR::addDependency(dependencies, NULL, TR::RealRegister::gr1, TR_GPR, cg);
TR::addDependency(dependencies, NULL, TR::RealRegister::gr0, TR_GPR, cg);
dependencies->addPreCondition(src1Reg, TR::RealRegister::fp0);
dependencies->addPreCondition(src2Reg, TR::RealRegister::fp1);
for (i = 2; i < 8; i++)
{
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)((uint32_t)TR::RealRegister::fp0 + i);
TR::addDependency(dependencies, NULL, realReg, TR_FPR, cg);
}
dependencies->addPostCondition(trgReg, TR::RealRegister::fp0);
dependencies->addPostCondition(cg->allocateRegister(TR_FPR), TR::RealRegister::fp1);//TODO live register
#else
dependencies->addPreCondition(src1Reg->getHighOrder(), TR::RealRegister::gr1);
dependencies->addPreCondition(src1Reg->getLowOrder(), TR::RealRegister::gr0);
TR::addDependency(dependencies, src2Reg->getLowOrder(), TR::RealRegister::gr2, TR_GPR, cg);
TR::addDependency(dependencies, src2Reg->getHighOrder(), TR::RealRegister::gr3, TR_GPR, cg);
dependencies->addPostCondition(highReg, TR::RealRegister::gr1);
dependencies->addPostCondition(lowReg, TR::RealRegister::gr0);
#endif
}
else
{
/* Big Endian */
#if defined(__ARM_PCS_VFP)
TR::addDependency(dependencies, NULL, TR::RealRegister::gr1, TR_GPR, cg);
TR::addDependency(dependencies, NULL, TR::RealRegister::gr0, TR_GPR, cg);
dependencies->addPreCondition(src1Reg, TR::RealRegister::fp0);
dependencies->addPreCondition(src2Reg, TR::RealRegister::fp1);
for (i = 2; i < 8; i++)
{
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)((uint32_t)TR::RealRegister::fp0 + i);
TR::addDependency(dependencies, NULL, realReg, TR_FPR, cg);
}
dependencies->addPostCondition(trgReg, TR::RealRegister::fp0);
dependencies->addPostCondition(cg->allocateRegister(TR_FPR), TR::RealRegister::fp1);//TODO live register
#else
dependencies->addPreCondition(src1Reg->getHighOrder(), TR::RealRegister::gr0);
dependencies->addPreCondition(src1Reg->getLowOrder(), TR::RealRegister::gr1);
TR::addDependency(dependencies, src2Reg->getHighOrder(), TR::RealRegister::gr2, TR_GPR, cg);
TR::addDependency(dependencies, src2Reg->getLowOrder(), TR::RealRegister::gr3, TR_GPR, cg);
dependencies->addPostCondition(highReg, TR::RealRegister::gr0);
dependencies->addPostCondition(lowReg, TR::RealRegister::gr1);
#endif
}
dependencies->stopAddingConditions();
generateImmSymInstruction(cg, ARMOp_bl,
node, (uintptr_t)cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMdoubleRemainder)->getMethodAddress(),
dependencies,
cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMdoubleRemainder));
if (noFPRA)
{
#if defined(__ARM_PCS_VFP)
if (resultCanStayInFloatRegister(cg->getCurrentEvaluationTreeTop()->getNode(), node))
{
traceMsg(cg->comp(), "Result of node %p can stay in FP reg.\n", node);
doubleTrgReg = trgReg;
}
else
{
doubleTrgReg = moveFromDoubleRegister(node, trgReg, cg);
cg->stopUsingRegister(trgReg);
}
#else
doubleTrgReg = trgReg;
#endif
}
else
doubleTrgReg = trgReg;
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
cg->machine()->setLinkRegisterKilled(true);
return doubleTrgReg;
}
static TR::Register *callFloatRemainderHelper(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::RegisterDependencyConditions *dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(11, 11, cg->trMemory());
int i;
#if defined(__ARM_PCS_VFP)
TR::Register *trgReg = cg->allocateSinglePrecisionRegister();
#else
TR::Register *trgReg = cg->allocateRegister(TR_GPR);
#endif
TR::Register *floatTrgReg = NULL;
#if defined(__ARM_PCS_VFP)
if (src1Reg->getKind() == TR_GPR)
{
src1Reg = moveToFloatRegister(node, src1Reg, cg);
}
if (src2Reg->getKind() == TR_GPR)
{
src2Reg = moveToFloatRegister(node, src2Reg, cg);
}
#else
if (src1Reg->getKind() == TR_FPR)
{
src1Reg = moveFromFloatRegister(node, src1Reg, cg);
}
if (src2Reg->getKind() == TR_FPR)
{
src2Reg = moveFromFloatRegister(node, src2Reg, cg);
}
#endif
#if defined(__ARM_PCS_VFP)
if(!noFPRA)
{
if((src1Reg->getKind() == TR_FPR) && !cg->canClobberNodesRegister(firstChild, 0))
{
TR::Register *tempReg = cg->allocateRegister(TR_FPR);
generateTrg1Src1Instruction(cg, ARMOp_fcpys, firstChild, tempReg, src1Reg);
src1Reg = tempReg;
}
if((src2Reg->getKind() == TR_FPR) && !cg->canClobberNodesRegister(secondChild, 0))
{
TR::Register *tempReg = cg->allocateRegister(TR_FPR);
generateTrg1Src1Instruction(cg, ARMOp_fcpys, secondChild, tempReg, src2Reg);
src2Reg = tempReg;
}
}
TR::addDependency(dependencies, NULL, TR::RealRegister::gr1, TR_GPR, cg);
TR::addDependency(dependencies, NULL, TR::RealRegister::gr0, TR_GPR, cg);
dependencies->addPreCondition(src1Reg, TR::RealRegister::fp0);
dependencies->addPreCondition(src2Reg, TR::RealRegister::fs1);
for (i = 1; i < 8; i++)
{
TR::RealRegister::RegNum realReg = (TR::RealRegister::RegNum)((uint32_t)TR::RealRegister::fp0 + i);
TR::addDependency(dependencies, NULL, realReg, TR_FPR, cg);
}
dependencies->addPostCondition(trgReg, TR::RealRegister::fp0);
#else
dependencies->addPreCondition(src1Reg, TR::RealRegister::gr0);
dependencies->addPreCondition(src2Reg, TR::RealRegister::gr1);
dependencies->addPostCondition(trgReg, TR::RealRegister::gr0);
dependencies->addPostCondition(cg->allocateRegister(), TR::RealRegister::gr1);//TODO live register
#endif
dependencies->stopAddingConditions();
generateImmSymInstruction(cg, ARMOp_bl,
node, (uintptr_t)cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMfloatRemainder)->getMethodAddress(),
dependencies,
cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARMfloatRemainder));
if (noFPRA)
{
#if defined(__ARM_PCS_VFP)
if (resultCanStayInFloatRegister(cg->getCurrentEvaluationTreeTop()->getNode(), node))
{
traceMsg(cg->comp(), "Result of node %p can stay in FP reg.\n", node);
floatTrgReg = trgReg;
}
else
{
floatTrgReg = moveFromFloatRegister(node, trgReg, cg);
cg->stopUsingRegister(trgReg);
}
#else
floatTrgReg = trgReg;
#endif
}
else
floatTrgReg = trgReg;
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
cg->machine()->setLinkRegisterKilled(true);
return floatTrgReg;
}
TR::Register *OMR::ARM::TreeEvaluator::ibits2fEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *target = NULL;
if (child->getRegister() == NULL && child->getReferenceCount() == 1 &&
child->getOpCode().isLoadVar())
{
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(child, 4, cg);
if (noFPRA)
{
if (resultCanStayInFloatRegister(cg->getCurrentEvaluationTreeTop()->getNode(), node))
traceMsg(cg->comp(), "Result of node %p can stay in FP reg (not exec.).\n", node);
target = cg->allocateRegister();
generateTrg1MemInstruction(cg, ARMOp_ldr, node, target, tempMR);
}
else
{
target = cg->allocateSinglePrecisionRegister();
if (tempMR->getIndexRegister() && tempMR->getBaseRegister())
{
TR::Register *tempReg = cg->allocateRegister();
generateTrg1Src2Instruction(cg, ARMOp_add, node, tempReg, tempMR->getBaseRegister(), tempMR->getIndexRegister());
tempMR->decNodeReferenceCounts();
tempMR = new (cg->trHeapMemory()) TR::MemoryReference(tempReg, 0, cg);
generateTrg1MemInstruction(cg, ARMOp_flds, node, target, tempMR);
cg->stopUsingRegister(tempReg);
}
else
generateTrg1MemInstruction(cg, ARMOp_flds, node, target, tempMR);
}
tempMR->decNodeReferenceCounts();
}
else
{
TR::Register *srcReg = cg->evaluate(child);
if (noFPRA)
{
target = srcReg;
}
else
{
target = moveToFloatRegister(node, srcReg, cg);
cg->stopUsingRegister(srcReg);
}
cg->decReferenceCount(child);
}
node->setRegister(target);
return target;
}
TR::Register *OMR::ARM::TreeEvaluator::fbits2iEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *target = cg->allocateRegister();
TR_ASSERT(!node->normalizeNanValues(), "Check NAN\n");
if (child->getRegister() == NULL && child->getReferenceCount() == 1 &&
child->getOpCode().isLoadVar())
{
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(child, 4, cg);
generateTrg1MemInstruction(cg, ARMOp_ldr, node, target, tempMR);
tempMR->decNodeReferenceCounts();
}
else
{
TR::Register *srcReg = cg->evaluate(child);
if (srcReg->getKind() == TR_FPR)
{
target = moveFromFloatRegister(node, srcReg, cg);
cg->stopUsingRegister(srcReg);
}
else
{
target = srcReg;
}
cg->decReferenceCount(child);
}
node->setRegister(target);
return target;
}
TR::Register *OMR::ARM::TreeEvaluator::lbits2dEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::RegisterPair *pairTarget = NULL;
TR::Register *target = NULL;
TR::Register *lowReg = NULL;
TR::Register *highReg = NULL;
TR::Compilation *comp = cg->comp();
if (child->getRegister() == NULL && child->getReferenceCount() == 1 &&
child->getOpCode().isLoadVar())
{
TR::MemoryReference *highMem, *lowMem;
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(child, 8, cg);
if (noFPRA)
{
lowReg = cg->allocateRegister();
highReg = cg->allocateRegister();
highMem = new (cg->trHeapMemory()) TR::MemoryReference(*tempMR, (cg->comp()->target().cpu.isBigEndian()) ? 0 : 4, 4, cg);
generateTrg1MemInstruction(cg, ARMOp_ldr, node, highReg, highMem);
lowMem = new (cg->trHeapMemory()) TR::MemoryReference(*tempMR, (cg->comp()->target().cpu.isBigEndian()) ? 4 : 0, 4, cg);
generateTrg1MemInstruction(cg, ARMOp_ldr, node, lowReg, lowMem);
highMem->decNodeReferenceCounts();
lowMem->decNodeReferenceCounts();
pairTarget = cg->allocateRegisterPair(lowReg, highReg);
node->setRegister(pairTarget);
return pairTarget;
}
else
{
target = cg->allocateRegister(TR_FPR);
highMem = new (cg->trHeapMemory()) TR::MemoryReference(*tempMR, 0, 8, cg);
if (highMem->getIndexRegister() && highMem->getBaseRegister())
{
TR::Register *tempReg = cg->allocateRegister();
generateTrg1Src2Instruction(cg, ARMOp_add, node, tempReg, highMem->getBaseRegister(), highMem->getIndexRegister());
highMem->decNodeReferenceCounts();
highMem = new (cg->trHeapMemory()) TR::MemoryReference(tempReg, 0, cg);
generateTrg1MemInstruction(cg, ARMOp_fldd, node, target, highMem);
cg->stopUsingRegister(tempReg);
}
else
generateTrg1MemInstruction(cg, ARMOp_fldd, node, target, highMem);
highMem->decNodeReferenceCounts();
node->setRegister(target);
return target;
}
}
else
{
TR::Register *srcReg = cg->evaluate(child);
if (noFPRA)
{
target = srcReg;
}
else
{
target = moveToDoubleRegister(node, srcReg, cg);
cg->stopUsingRegister(srcReg);
}
cg->decReferenceCount(child);
node->setRegister(target);
return target;
}
}
TR::Register *OMR::ARM::TreeEvaluator::dbits2lEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *target = NULL;
TR::Register *srcReg = NULL;
TR::Register *lowReg = NULL;
TR::Register *highReg = NULL;
TR::Compilation *comp = cg->comp();
TR_ASSERT(!node->normalizeNanValues(), "Check NAN\n");
if (child->getRegister() == NULL && child->getReferenceCount() == 1 &&
child->getOpCode().isLoadVar())
{
TR::MemoryReference *highMem, *lowMem;
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(child, 8, cg);
lowReg = cg->allocateRegister();
highReg = cg->allocateRegister();
highMem = new (cg->trHeapMemory()) TR::MemoryReference(*tempMR, (cg->comp()->target().cpu.isBigEndian()) ? 0 : 4, 4, cg);
generateTrg1MemInstruction(cg, ARMOp_ldr, node, highReg, highMem);
lowMem = new (cg->trHeapMemory()) TR::MemoryReference(*tempMR, (cg->comp()->target().cpu.isBigEndian()) ? 4 : 0, 4, cg);
generateTrg1MemInstruction(cg, ARMOp_ldr, node, lowReg, lowMem);
highMem->decNodeReferenceCounts();
lowMem->decNodeReferenceCounts();
target = cg->allocateRegisterPair(lowReg, highReg);
tempMR->decNodeReferenceCounts(); // Taken from PPC
}
else
{
srcReg = cg->evaluate(child);
if (srcReg->getKind() == TR_FPR)
{
target = moveFromDoubleRegister(node, srcReg, cg);