-
Notifications
You must be signed in to change notification settings - Fork 392
/
OMRRealRegister.hpp
169 lines (142 loc) · 5.3 KB
/
OMRRealRegister.hpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
/*******************************************************************************
* Copyright (c) 2018, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#ifndef OMR_ARM64_REAL_REGISTER_INCL
#define OMR_ARM64_REAL_REGISTER_INCL
/*
* The following #define and typedef must appear before any #includes in this file
*/
#ifndef OMR_REAL_REGISTER_CONNECTOR
#define OMR_REAL_REGISTER_CONNECTOR
namespace OMR { namespace ARM64 { class RealRegister; } }
namespace OMR { typedef OMR::ARM64::RealRegister RealRegisterConnector; }
#else
#error OMR::ARM64::RealRegister expected to be a primary connector, but an OMR connector is already defined
#endif
#include "compiler/codegen/OMRRealRegister.hpp"
#include "infra/Annotations.hpp"
namespace TR { class CodeGenerator; }
namespace OMR
{
namespace ARM64
{
class OMR_EXTENSIBLE RealRegister : public OMR::RealRegister
{
protected:
/**
* @param[in] cg : the TR::CodeGenerator object
*/
RealRegister(TR::CodeGenerator *cg) : OMR::RealRegister(cg, NoReg) {}
/**
* @param[in] rk : kind of real register from TR_RegisterKinds
* @param[in] w : register weight
* @param[in] s : register state from RegState
* @param[in] rn : register number from RegNum
* @param[in] m : register mask from RegMask
* @param[in] cg : the TR::CodeGenerator object
*/
RealRegister(TR_RegisterKinds rk, uint16_t w, RegState s, RegNum rn, RegMask m, TR::CodeGenerator *cg) :
OMR::RealRegister(rk, w, s, (uint16_t)0, rn, m, cg) {}
public:
typedef enum {
pos_RD = 0,
pos_RN = 5,
pos_RM = 16,
pos_RT = 0,
pos_RT2 = 10,
pos_RS = 16,
pos_RA = 10
} ARM64OperandPosition;
/**
* @brief Set the RealRegister in the Rd field of the specified instruction
* @param[in] instruction : target instruction
*/
void setRegisterFieldRD(uint32_t *instruction)
{
*instruction |= fullRegBinaryEncodings[_registerNumber] << pos_RD;
}
/**
* @brief Set the RealRegister in the Rn field of the specified instruction
* @param[in] instruction : target instruction
*/
void setRegisterFieldRN(uint32_t *instruction)
{
*instruction |= fullRegBinaryEncodings[_registerNumber] << pos_RN;
}
/**
* @brief Set the RealRegister in the Rm field of the specified instruction
* @param[in] instruction : target instruction
*/
void setRegisterFieldRM(uint32_t *instruction)
{
*instruction |= fullRegBinaryEncodings[_registerNumber] << pos_RM;
}
/**
* @brief Set the RealRegister in the Rt field of the specified instruction
* @param[in] instruction : target instruction
*/
void setRegisterFieldRT(uint32_t *instruction)
{
*instruction |= fullRegBinaryEncodings[_registerNumber] << pos_RT;
}
/**
* @brief Set the RealRegister in the Rt2 field of the specified instruction
* @param[in] instruction : target instruction
*/
void setRegisterFieldRT2(uint32_t *instruction)
{
*instruction |= fullRegBinaryEncodings[_registerNumber] << pos_RT2;
}
/**
* @brief Set the RealRegister in the Rs field of the specified instruction
* @param[in] instruction : target instruction
*/
void setRegisterFieldRS(uint32_t *instruction)
{
*instruction |= fullRegBinaryEncodings[_registerNumber] << pos_RS;
}
/**
* @brief Set the RealRegister in the Ra field of the specified instruction
* @param[in] instruction : target instruction
*/
void setRegisterFieldRA(uint32_t *instruction)
{
*instruction |= fullRegBinaryEncodings[_registerNumber] << pos_RA;
}
/**
* @brief Returns register mask for available registers of specified kind
* @param[in] rk : register kind
* @returns register mask
*/
static TR_RegisterMask getAvailableRegistersMask(TR_RegisterKinds rk);
/**
* @brief Returns real register for the passed register mask
* @param[in] mask : register mask
* @param[in] rk : register kind
* @param[in] cg : code generator
* @returns real register
*/
static TR::RealRegister *regMaskToRealRegister(TR_RegisterMask mask, TR_RegisterKinds rk, TR::CodeGenerator *cg);
private:
static const uint8_t fullRegBinaryEncodings[NumRegisters];
};
}
}
#endif