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OMRInstOpCodeProperties.hpp
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OMRInstOpCodeProperties.hpp
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/*******************************************************************************
* Copyright (c) 2019, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
/*
* This file will be included within a static table. Only comments and
* definitions are permitted.
*/
{
/* .mnemonic = */ OMR::InstOpCode::assocreg,
/* .name = */ "assocreg",
/* .description = "Associate real registers with Virtual registers.", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x00000000,
/* .format = */ FORMAT_NONE,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::bad,
/* .name = */ "bad",
/* .description = "Illegal Opcode", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x00000000,
/* .format = */ FORMAT_DIRECT,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_None,
},
{
/* .mnemonic = */ OMR::InstOpCode::dd,
/* .name = */ ".dd",
/* .description = "Define Doubleword", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x00000000,
/* .format = */ FORMAT_DD,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_None,
},
{
/* .mnemonic = */ OMR::InstOpCode::fence,
/* .name = */ "fence",
/* .description = "Fence", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x00000000,
/* .format = */ FORMAT_NONE,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::label,
/* .name = */ "label",
/* .description = "Destination of a jump", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x00000000,
/* .format = */ FORMAT_NONE,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_None,
},
{
/* .mnemonic = */ OMR::InstOpCode::proc,
/* .name = */ "proc",
/* .description = "Entry to the method", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x00000000,
/* .format = */ FORMAT_NONE,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_None,
},
{
/* .mnemonic = */ OMR::InstOpCode::retn,
/* .name = */ "retn",
/* .description = "Return", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x00000000,
/* .format = */ FORMAT_NONE,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_None,
},
{
/* .mnemonic = */ OMR::InstOpCode::add,
/* .name = */ "add",
/* .description = "Add", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000214,
/* .format = */ FORMAT_RT_RA_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::add_r,
/* .name = */ "add.",
/* .description = "Add Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::add].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::add].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::add].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::add].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::add].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::addc,
/* .name = */ "addc",
/* .description = "Add carrying", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000014,
/* .format = */ FORMAT_RT_RA_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_SetsCarryFlag |
PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::addc_r,
/* .name = */ "addc.",
/* .description = "Add carrying Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addc].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addc].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addc].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addc].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addc].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::addco,
/* .name = */ "addco",
/* .description = "Add carrying setting overflow", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000414,
/* .format = */ FORMAT_RT_RA_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_SetsCarryFlag |
PPCOpProp_SetsOverflowFlag |
PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::addco_r,
/* .name = */ "addco.",
/* .description = "Add carrying setting overflow Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addco].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addco].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addco].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addco].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addco].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::adde,
/* .name = */ "adde",
/* .description = "Add extended", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000114,
/* .format = */ FORMAT_RT_RA_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_ReadsCarryFlag |
PPCOpProp_SetsCarryFlag |
PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::adde_r,
/* .name = */ "adde.",
/* .description = "Add extended Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::adde].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::adde].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::adde].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::adde].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::adde].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::addeo,
/* .name = */ "addeo",
/* .description = "Add extended setting overflow", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000514,
/* .format = */ FORMAT_RT_RA_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_ReadsCarryFlag |
PPCOpProp_SetsCarryFlag |
PPCOpProp_SetsOverflowFlag |
PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::addeo_r,
/* .name = */ "addeo.",
/* .description = "Add extended setting overflow Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addeo].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addeo].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addeo].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addeo].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addeo].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::addi,
/* .name = */ "addi",
/* .description = "Add immediate", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x38000000,
/* .format = */ FORMAT_RT_D16_RA,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_SyncSideEffectFree |
PPCOpProp_ExcludeR0ForRA,
},
{
/* .mnemonic = */ OMR::InstOpCode::addic,
/* .name = */ "addic",
/* .description = "Add immediate carrying", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x30000000,
/* .format = */ FORMAT_RT_RA_SI16,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_SetsCarryFlag |
PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::addic_r,
/* .name = */ "addic.",
/* .description = "Add immediate carrying Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addic].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addic].opcode + 0x04000000,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addic].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addic].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addic].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::addi2,
/* .name = */ "addi",
/* .description = "Add imm (carry bit set only if record form)", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x38000000,
/* .format = */ FORMAT_RT_D16_RA,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_SetsCarryFlag |
PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree |
PPCOpProp_ExcludeR0ForRA,
},
{
/* .mnemonic = */ OMR::InstOpCode::addi2_r,
/* .name = */ "addic.",
/* .description = "Add imm (carry bit set only if record form) Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addic].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addic].opcode + 0x04000000,
// Note: Normally, addic is not meant to be used as a memory instruction, since its RA field is
// not subject to the normal rule about gr0. However, it can be used under safely under
// certain controlled conditions that ensure that no code expected the gr0 = 0 behaviour
// will be triggered.
/* .format = */ FORMAT_RT_D16_RA,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addic].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addic].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::addis,
/* .name = */ "addis",
/* .description = "Add immediate shifted", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x3C000000,
/* .format = */ FORMAT_RT_RA_SI16,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_SyncSideEffectFree |
PPCOpProp_ExcludeR0ForRA,
},
{
/* .mnemonic = */ OMR::InstOpCode::addme,
/* .name = */ "addme",
/* .description = "Add to minus one extended", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C0001D4,
/* .format = */ FORMAT_RT_RA,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_ReadsCarryFlag |
PPCOpProp_SetsCarryFlag |
PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::addme_r,
/* .name = */ "addme.",
/* .description = "Add to minus one extended Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addme].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addme].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addme].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addme].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addme].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::addmeo,
/* .name = */ "addmeo",
/* .description = "Add to minus one extended setting overflow", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C0005D4,
/* .format = */ FORMAT_RT_RA,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_ReadsCarryFlag |
PPCOpProp_SetsCarryFlag |
PPCOpProp_SetsOverflowFlag |
PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::addmeo_r,
/* .name = */ "addmeo.",
/* .description = "Add to minus one extended setting overflow Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addmeo].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addmeo].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addmeo].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addmeo].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addmeo].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::addo,
/* .name = */ "addo",
/* .description = "Add setting overflow", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000614,
/* .format = */ FORMAT_RT_RA_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_SetsOverflowFlag |
PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::addo_r,
/* .name = */ "addo.",
/* .description = "Add setting overflow Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addo].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addo].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addo].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addo].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addo].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::addpcis,
/* .name = */ "addpcis",
/* .description = "Add PC Immediate Shifted", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4C000004,
/* .format = */ FORMAT_UNKNOWN,
/* .minimumALS = */ OMR_PROCESSOR_PPC_P9,
/* .properties = */ PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::addze,
/* .name = */ "addze",
/* .description = "Add to zero extended", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000194,
/* .format = */ FORMAT_RT_RA,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_ReadsCarryFlag |
PPCOpProp_SetsCarryFlag |
PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::addze_r,
/* .name = */ "addze.",
/* .description = "Add to zero extended Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addze].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addze].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addze].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addze].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addze].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::addzeo,
/* .name = */ "addzeo",
/* .description = "Add to zero extended setting overflow", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000594,
/* .format = */ FORMAT_RT_RA,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_ReadsCarryFlag |
PPCOpProp_SetsCarryFlag |
PPCOpProp_SetsOverflowFlag |
PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::addzeo_r,
/* .name = */ "addzeo.",
/* .description = "Add to zero extended setting overflow Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addzeo].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addzeo].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addzeo].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addzeo].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addzeo].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::AND,
/* .name = */ "and",
/* .description = "AND", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000038,
/* .format = */ FORMAT_RA_RS_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::and_r,
/* .name = */ "and.",
/* .description = "AND Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::AND].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::AND].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::AND].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::AND].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::AND].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::andc,
/* .name = */ "andc",
/* .description = "AND with complement", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000078,
/* .format = */ FORMAT_RA_RS_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::andc_r,
/* .name = */ "andc.",
/* .description = "AND with complement Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::andc].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::andc].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::andc].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::andc].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::andc].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
/* { */
/* .mnemonic = OMR::InstOpCode::andcxor, */
/* .name = "andcxor", */
/* .description = "AND with Complement & XOR", */
/* .prefix = 0x00000000, */
/* .opcode = 0x10000037, */
/* .format = FORMAT_UNKNOWN, */
/* .minimumALS = OMR_PROCESSOR_PPC_UNKNOWN, */
/* .properties = PPCOpProp_SyncSideEffectFree, */
/* }, */
{
/* .mnemonic = */ OMR::InstOpCode::addex,
/* .name = */ "addex",
/* .description = "Add Extended using alternate carry bits", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000154,
/* .format = */ FORMAT_UNKNOWN,
/* .minimumALS = */ OMR_PROCESSOR_PPC_P9,
/* .properties = */ PPCOpProp_HasRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::addex_r,
/* .name = */ "addex.",
/* .description = "Add Extended using alternate carry bits Rc=1", */
/* .prefix = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addex].prefix,
/* .opcode = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addex].opcode + 1,
/* .format = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addex].format,
/* .minimumALS = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addex].minimumALS,
/* .properties = */ OMR::Power::InstOpCode::metadata[OMR::InstOpCode::addex].properties & ~PPCOpProp_HasRecordForm | PPCOpProp_IsRecordForm,
},
{
/* .mnemonic = */ OMR::InstOpCode::andi_r,
/* .name = */ "andi.",
/* .description = "AND immediate", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x70000000,
/* .format = */ FORMAT_RA_RS_UI16,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_IsRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::andis_r,
/* .name = */ "andis.",
/* .description = "AND immediate shifted", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x74000000,
/* .format = */ FORMAT_RA_RS_UI16,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_IsRecordForm |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::b,
/* .name = */ "b",
/* .description = "Unconditional branch", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x48000000,
/* .format = */ FORMAT_I_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bctr,
/* .name = */ "bctr",
/* .description = "Branch to count register", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4E800420,
/* .format = */ FORMAT_DIRECT,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp |
PPCOpProp_UsesCtr,
},
{
/* .mnemonic = */ OMR::InstOpCode::bctrl,
/* .name = */ "bctrl",
/* .description = "Branch to count register and link", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4E800421,
/* .format = */ FORMAT_DIRECT,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp |
PPCOpProp_UsesCtr,
},
{
/* .mnemonic = */ OMR::InstOpCode::bdnz,
/* .name = */ "bdnz",
/* .description = "Branch if CTR!=0 after decrementing it", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x42000000,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp |
PPCOpProp_UsesCtr |
PPCOpProp_SetsCtr,
},
{
/* .mnemonic = */ OMR::InstOpCode::bdz,
/* .name = */ "bdz",
/* .description = "Branch if CTR==0 after decrementing it", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x42400000,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp |
PPCOpProp_UsesCtr |
PPCOpProp_SetsCtr,
},
{
/* .mnemonic = */ OMR::InstOpCode::beq,
/* .name = */ "beq",
/* .description = "Branch if equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x41820000,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::beql,
/* .name = */ "beql",
/* .description = "Branch and link if equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x41820001,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bfctr,
/* .name = */ "bfctr",
/* .description = "Branch false to count register", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4C800020,
/* .format = */ FORMAT_UNKNOWN,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp |
PPCOpProp_UsesCtr,
},
{
/* .mnemonic = */ OMR::InstOpCode::bge,
/* .name = */ "bge",
/* .description = "Branch if greater than or equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x40800000,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bgel,
/* .name = */ "bgel",
/* .description = "Branch and link if greater than or equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x40800001,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bgt,
/* .name = */ "bgt",
/* .description = "Branch if greater than", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x41810000,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bgtl,
/* .name = */ "bgtl",
/* .description = "Branch and link if greater than", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x41810001,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bl,
/* .name = */ "bl",
/* .description = "Branch and link", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x48000001,
/* .format = */ FORMAT_I_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_RIOS1,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::ble,
/* .name = */ "ble",
/* .description = "Branch if less than or equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x40810000,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::blel,
/* .name = */ "blel",
/* .description = "Branch and link if less than or equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x40810001,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::blt,
/* .name = */ "blt",
/* .description = "Branch if less than", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x41800000,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bltl,
/* .name = */ "bltl",
/* .description = "Branch and link if less than", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x41800001,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::blr,
/* .name = */ "blr",
/* .description = "Branch to link register", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4E800020,
/* .format = */ FORMAT_DIRECT,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::blrl,
/* .name = */ "blrl",
/* .description = "Branch to link register and link", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4E800021,
/* .format = */ FORMAT_DIRECT,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bne,
/* .name = */ "bne",
/* .description = "Branch if not equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x40820000,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bnel,
/* .name = */ "bnel",
/* .description = "Branch and link if not equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x40820001,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bnun,
/* .name = */ "bnu",
/* .description = "Branch if not unordered", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x40830000,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::btctr,
/* .name = */ "btctr",
/* .description = "Branch true to count register", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4D800020,
/* .format = */ FORMAT_UNKNOWN,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp |
PPCOpProp_UsesCtr,
},
{
/* .mnemonic = */ OMR::InstOpCode::bun,
/* .name = */ "bun",
/* .description = "Branch if unordered", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x41830000,
/* .format = */ FORMAT_B_FORM,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::beqlr,
/* .name = */ "beqlr",
/* .description = "Branch to link register if equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4D820020,
/* .format = */ FORMAT_XL_FORM_BRANCH,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bgelr,
/* .name = */ "bgelr",
/* .description = "Branch to link register if greater than or equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4C800020,
/* .format = */ FORMAT_XL_FORM_BRANCH,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bgtlr,
/* .name = */ "bgtlr",
/* .description = "Branch to link register if greater than", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4D810020,
/* .format = */ FORMAT_XL_FORM_BRANCH,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::blelr,
/* .name = */ "blelr",
/* .description = "Branch to link register if less than or equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4C810020,
/* .format = */ FORMAT_XL_FORM_BRANCH,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bltlr,
/* .name = */ "bltlr",
/* .description = "Branch to link register if less than", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4D800020,
/* .format = */ FORMAT_XL_FORM_BRANCH,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::bnelr,
/* .name = */ "bnelr",
/* .description = "Branch to link register if not equal", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x4C820020,
/* .format = */ FORMAT_XL_FORM_BRANCH,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_BranchOp,
},
{
/* .mnemonic = */ OMR::InstOpCode::cmp4,
/* .name = */ "cmpw",
/* .description = "Compare word algebraic", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000000,
/* .format = */ FORMAT_BF_RA_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_CompareOp |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::cmp8,
/* .name = */ "cmpd",
/* .description = "Compare dword algebraic", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C200000,
/* .format = */ FORMAT_BF_RA_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_DWord |
PPCOpProp_CompareOp |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::cmpi4,
/* .name = */ "cmpwi",
/* .description = "Compare word immediate algebraic", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x2C000000,
/* .format = */ FORMAT_BF_RA_SI16,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_CompareOp |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::cmpi8,
/* .name = */ "cmpdi",
/* .description = "Compare dword immediate algebraic", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x2C200000,
/* .format = */ FORMAT_BF_RA_SI16,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_DWord |
PPCOpProp_CompareOp |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::cmpl4,
/* .name = */ "cmplw",
/* .description = "Compare word logical", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000040,
/* .format = */ FORMAT_BF_RA_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_CompareOp |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::cmpl8,
/* .name = */ "cmpld",
/* .description = "Compare dword logical", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C200040,
/* .format = */ FORMAT_BF_RA_RB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_DWord |
PPCOpProp_CompareOp |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::cmpli4,
/* .name = */ "cmplwi",
/* .description = "Compare word immediate logical", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x28000000,
/* .format = */ FORMAT_BF_RA_UI16,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_CompareOp |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::cmpli8,
/* .name = */ "cmpldi",
/* .description = "Compare dword immediate logical", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x28200000,
/* .format = */ FORMAT_BF_RA_UI16,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_DWord |
PPCOpProp_CompareOp |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::cmprb,
/* .name = */ "cmprb",
/* .description = "Compare Ranged Byte", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x7C000180,
/* .format = */ FORMAT_BF_RA_RB_L,
/* .minimumALS = */ OMR_PROCESSOR_PPC_P9,
/* .properties = */ PPCOpProp_CompareOp |
PPCOpProp_SyncSideEffectFree,
},
{
/* .mnemonic = */ OMR::InstOpCode::cmpeqb,
/* .name = */ "cmpeqb",
/* .description = "Compare Equal Byte", */
/* .prefix = */ 0x00000000,