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OMRCodeGenerator.cpp
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OMRCodeGenerator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include "codegen/CodeGenerator.hpp"
#include "codegen/CodeGenerator_inlines.hpp"
#include <limits.h>
#include <stdint.h>
#include <string.h>
#include "codegen/BackingStore.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/GCStackAtlas.hpp"
#include "codegen/GCStackMap.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LinkageConventionsEnum.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/RecognizedMethods.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterIterator.hpp"
#include "codegen/RegisterPressureSimulatorInner.hpp"
#include "codegen/RegisterRematerializationInfo.hpp"
#include "codegen/Snippet.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "codegen/X86Evaluator.hpp"
#ifdef TR_TARGET_64BIT
#include "x/amd64/codegen/AMD64SystemLinkage.hpp"
#else
#include "x/i386/codegen/IA32SystemLinkage.hpp"
#endif
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "compile/VirtualGuard.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "control/Recompilation.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "control/RecompilationInfo.hpp"
#endif
#include "env/CompilerEnv.hpp"
#include "env/IO.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ParameterSymbol.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/StaticSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "infra/BitVector.hpp"
#include "infra/Flags.hpp"
#include "infra/IGNode.hpp"
#include "infra/InterferenceGraph.hpp"
#include "infra/List.hpp"
#include "infra/Stack.hpp"
#include "optimizer/RegisterCandidate.hpp"
#include "ras/Debug.hpp"
#include "ras/DebugCounter.hpp"
#include "runtime/CodeCacheManager.hpp"
#include "x/codegen/DataSnippet.hpp"
#include "x/codegen/OutlinedInstructions.hpp"
#include "x/codegen/FPTreeEvaluator.hpp"
#include "x/codegen/X86Instruction.hpp"
#include "codegen/InstOpCode.hpp"
namespace OMR { class RegisterUsage; }
namespace TR { class RegisterDependencyConditions; }
// Hack markers
#define CANT_REMATERIALIZE_ADDRESSES(cg) (cg->comp()->target().is64Bit()) // AMD64 produces a memref with an unassigned addressRegister
TR_X86ProcessorInfo OMR::X86::CodeGenerator::_targetProcessorInfo;
void TR_X86ProcessorInfo::initialize()
{
if (_featureFlags.testAny(TR_X86ProcessorInfoInitialized))
return;
// For now, we only convert the feature bits into a flags32_t, for easier querying.
// To retrieve other information, the VM functions can be called directly.
//
_featureFlags.set(TR::Compiler->target.cpu.getX86ProcessorFeatureFlags());
_featureFlags2.set(TR::Compiler->target.cpu.getX86ProcessorFeatureFlags2());
_featureFlags8.set(TR::Compiler->target.cpu.getX86ProcessorFeatureFlags8());
// Determine the processor vendor.
//
const char *vendor = TR::Compiler->target.cpu.getX86ProcessorVendorId();
if (!strncmp(vendor, "GenuineIntel", 12))
_vendorFlags.set(TR_GenuineIntel);
else if (!strncmp(vendor, "AuthenticAMD", 12))
_vendorFlags.set(TR_AuthenticAMD);
else
_vendorFlags.set(TR_UnknownVendor);
// Finally set this bit so we don't attempt to re-initialize.
//
_featureFlags.set(TR_X86ProcessorInfoInitialized);
// initialize the processor model description
_processorDescription = 0;
// set up the processor family and cache description
uint32_t _processorSignature = TR::Compiler->target.cpu.getX86ProcessorSignature();
if (isGenuineIntel())
{
switch (getCPUFamily(_processorSignature))
{
case 0x05: _processorDescription |= TR_ProcessorIntelPentium; break;
case 0x06:
{
uint32_t extended_model = getCPUModel(_processorSignature) + (getCPUExtendedModel(_processorSignature) << 4);
switch (extended_model)
{
case 0x55:
_processorDescription |= TR_ProcessorIntelSkylake; break;
case 0x4f:
_processorDescription |= TR_ProcessorIntelBroadwell; break;
case 0x3f:
case 0x3c:
_processorDescription |= TR_ProcessorIntelHaswell; break;
case 0x3e:
case 0x3a:
_processorDescription |= TR_ProcessorIntelIvyBridge; break;
case 0x2a:
case 0x2d: // SandyBridge EP
_processorDescription |= TR_ProcessorIntelSandyBridge; break;
case 0x2c: // WestmereEP
case 0x2f: // WestmereEX
_processorDescription |= TR_ProcessorIntelWestmere; break;
case 0x1a: // Nehalem
_processorDescription |= TR_ProcessorIntelNehalem; break;
case 0x17: // Harpertown
case 0x0f: // Woodcrest/Clovertown
_processorDescription |= TR_ProcessorIntelCore2; break;
default: _processorDescription |= TR_ProcessorIntelP6; break;
}
break;
}
case 0x0f: _processorDescription |= TR_ProcessorIntelPentium4; break;
default: _processorDescription |= TR_ProcessorUnknown; break;
}
}
else if (isAuthenticAMD())
{
switch (getCPUFamily(_processorSignature))
{
case 0x05:
if (getCPUModel(_processorSignature) < 0x04)
_processorDescription |= TR_ProcessorAMDK5;
else
_processorDescription |= TR_ProcessorAMDK6;
break;
case 0x06: _processorDescription |= TR_ProcessorAMDAthlonDuron; break;
case 0x0f:
if (getCPUExtendedFamily(_processorSignature) < 6)
_processorDescription |= TR_ProcessorAMDOpteron;
else
_processorDescription |= TR_ProcessorAMDFamily15h;
break;
default: _processorDescription |= TR_ProcessorUnknown; break;
}
}
}
void
OMR::X86::CodeGenerator::initializeX86(TR::Compilation *comp)
{
bool supportsSSE2 = false;
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.isGenuineIntel() == _targetProcessorInfo.isGenuineIntel(), "isGenuineIntel() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.isAuthenticAMD() == _targetProcessorInfo.isAuthenticAMD(), "isAuthenticAMD() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.prefersMultiByteNOP() == _targetProcessorInfo.prefersMultiByteNOP(), "prefersMultiByteNOP() failed\n");
// Pick a padding table
//
if (comp->target().cpu.isGenuineIntel() && comp->target().is32Bit())
_paddingTable = &_old32BitPaddingTable;
else if (comp->target().cpu.isAuthenticAMD())
_paddingTable = &_K8PaddingTable;
else if (comp->target().cpu.prefersMultiByteNOP() && !comp->getOption(TR_DisableZealousCodegenOpts))
_paddingTable = &_intelMultiBytePaddingTable;
else if (comp->target().is32Bit())
_paddingTable = &_old32BitPaddingTable; // Unknown 32-bit target
else
_paddingTable = &_K8PaddingTable; // Unknown 64-bit target
// Determine whether or not x87 or SSE should be used for floating point.
//
#if defined(TR_TARGET_X86)
#if !defined(J9HAMMER)
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE2) == _targetProcessorInfo.supportsSSE2(), "supportsSSE2() failed\n");
if (comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE2) && comp->target().cpu.testOSForSSESupport())
supportsSSE2 = true;
#else
// 64-bit targets all support SSE2
supportsSSE2 = true;
#endif // !defined(J9HAMMER)
#endif // defined(TR_TARGET_X86)
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.supportsFeature(OMR_FEATURE_X86_RTM) == _targetProcessorInfo.supportsTM(), "supportsTM() failed\n");
if (comp->target().cpu.supportsFeature(OMR_FEATURE_X86_RTM) && !comp->getOption(TR_DisableTM))
{
/**
* Due to many verions of Haswell and a small number of Broadwell have defects for TM and then disabled by Intel,
* we will return false for any versions before Broadwell.
*
* TODO: Need to figure out from which mode of Broadwell start supporting TM
*/
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELHASWELL) == _targetProcessorInfo.isIntelHaswell(), "isIntelHaswell() failed\n");
if (!comp->target().cpu.is(OMR_PROCESSOR_X86_INTELHASWELL))
{
if (comp->target().is64Bit())
{
self()->setSupportsTM(); // disable tm on 32bits for now
}
}
}
TR_ASSERT_FATAL(supportsSSE2, "Target processor/OS must support SSE2");
self()->setUseSSEForSinglePrecision();
self()->setUseSSEForDoublePrecision();
self()->setSupportsAutoSIMD();
self()->setSupportsJavaFloatSemantics();
// Choose the best XMM double precision load instruction for the target architecture.
//
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.isAuthenticAMD() == _targetProcessorInfo.isAuthenticAMD(), "isAuthenticAMD() failed\n");
static char *forceMOVLPD = feGetEnv("TR_forceMOVLPDforDoubleLoads");
if (comp->target().cpu.isAuthenticAMD() || forceMOVLPD)
{
self()->setXMMDoubleLoadOpCode(MOVLPDRegMem);
}
else
{
self()->setXMMDoubleLoadOpCode(MOVSDRegMem);
}
self()->setTargetSupportsSoftwarePrefetches();
// Enable software prefetch of the TLH and configure the TLH prefetching
// geometry.
//
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELCORE2) == comp->cg()->getX86ProcessorInfo().isIntelCore2(), "isIntelCore2() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELNEHALEM) == comp->cg()->getX86ProcessorInfo().isIntelNehalem(), "isIntelNehalem() failed\n");
if (((!comp->getOption(TR_DisableTLHPrefetch) && (comp->target().cpu.is(OMR_PROCESSOR_X86_INTELCORE2) || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELNEHALEM))) ||
(comp->getOption(TR_TLHPrefetch) && self()->targetSupportsSoftwarePrefetches())))
{
self()->setEnableTLHPrefetching();
}
self()->setGlobalGPRPartitionLimit(self()->machine()->getGlobalGPRPartitionLimit());
self()->setGlobalFPRPartitionLimit(self()->machine()->getGlobalFPRPartitionLimit());
self()->setLastGlobalGPR(self()->machine()->getLastGlobalGPRRegisterNumber());
self()->setLast8BitGlobalGPR(self()->machine()->getLast8BitGlobalGPRRegisterNumber());
self()->setLastGlobalFPR(self()->machine()->getLastGlobalFPRRegisterNumber());
/*
* GRA does not work with vector registers on 32 bit due to a bug where xmm registers are not being assigned.
* This disables GRA for vector registers on 32 bit.
* This code will be reenabled as part of Issue 2035 which tracks the progress of fixing the GRA bug.
* GRA does not work with vector registers on 64 bit either. So GRA is now being disabled vector registers.
* This code will be reenabled as part of Issue 2280
*/
#if 0
if (comp->target().is64Bit())
{
self()->setFirstGlobalVRF(self()->getFirstGlobalFPR());
self()->setLastGlobalVRF(self()->getLastGlobalFPR());
}
#endif // closes the if 0.
// Initialize Linkage for Code Generator
self()->initializeLinkage();
_linkageProperties = &self()->getLinkage()->getProperties();
_unlatchedRegisterList = (TR::RealRegister**)self()->trMemory()->allocateHeapMemory(sizeof(TR::RealRegister*)*(TR::RealRegister::NumRegisters + 1));
_unlatchedRegisterList[0] = 0; // mark that list is empty
self()->setGlobalRegisterTable(self()->machine()->getGlobalRegisterTable(*_linkageProperties));
self()->machine()->initializeRegisterFile(*_linkageProperties);
self()->getLinkage()->copyLinkageInfoToParameterSymbols();
_switchToInterpreterLabel = NULL;
// Use a virtual frame pointer register. The real frame pointer register to be used
// will be substituted based on _vfpState during size estimation.
//
_frameRegister = self()->machine()->getRealRegister(TR::RealRegister::vfp);
TR::Register *vmThreadRegister = self()->setVMThreadRegister(self()->allocateRegister());
TR::RealRegister::RegNum vmThreadIndex = _linkageProperties->getMethodMetaDataRegister();
if (vmThreadIndex != TR::RealRegister::NoReg)
{
TR::RealRegister *vmThreadReal = self()->machine()->getRealRegister(vmThreadIndex);
vmThreadRegister->setAssignedRegister(vmThreadReal);
vmThreadRegister->setAssociation(vmThreadIndex);
vmThreadReal->setAssignedRegister(vmThreadRegister);
vmThreadReal->setState(TR::RealRegister::Assigned);
}
if (!debug("disableBetterSpillPlacements"))
self()->setEnableBetterSpillPlacements();
self()->setEnableRematerialisation();
self()->setEnableRegisterAssociations();
self()->setEnableRegisterWeights();
self()->setEnableRegisterInterferences();
self()->setEnableSinglePrecisionMethods();
if (!debug("disableRefinedAliasSets"))
self()->setEnableRefinedAliasSets();
if (!comp->getOption(TR_DisableLiveRangeSplitter))
comp->setOption(TR_EnableRangeSplittingGRA);
self()->addSupportedLiveRegisterKind(TR_GPR);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(comp), TR_GPR);
self()->addSupportedLiveRegisterKind(TR_FPR);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(comp), TR_FPR);
self()->addSupportedLiveRegisterKind(TR_VRF);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(comp), TR_VRF);
if (!TR::Compiler->om.canGenerateArraylets())
{
self()->setSupportsArrayCmp();
self()->setSupportsPrimitiveArrayCopy();
if (!comp->getOption(TR_DisableArraySetOpts))
{
self()->setSupportsArraySet();
}
static bool disableX86TRTO = (bool)feGetEnv("TR_disableX86TRTO");
if (!disableX86TRTO)
{
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE4_1) == self()->getX86ProcessorInfo().supportsSSE4_1(), "supportsSSE4_1() failed\n");
if (comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE4_1))
{
self()->setSupportsArrayTranslateTRTO();
}
}
static bool disableX86TROT = (bool)feGetEnv("TR_disableX86TROT");
if (!disableX86TROT)
{
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE4_1) == self()->getX86ProcessorInfo().supportsSSE4_1(), "supportsSSE4_1() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE2) == self()->getX86ProcessorInfo().supportsSSE2(), "supportsSSE4_1() failed\n");
if (comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE4_1))
{
self()->setSupportsArrayTranslateTROT();
}
if (comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE2))
{
self()->setSupportsArrayTranslateTROTNoBreak();
}
}
}
self()->setSupportsRecompilation();
self()->setSupportsScaledIndexAddressing();
self()->setSupportsConstantOffsetInAddressing();
self()->setSupportsCompactedLocals();
self()->setSupportsGlRegDeps();
self()->setSupportsEfficientNarrowIntComputation();
self()->setSupportsEfficientNarrowUnsignedIntComputation();
self()->setSupportsVirtualGuardNOPing();
self()->setSupportsDynamicANewArray();
self()->setSupportsSelect();
// TODO (#5642): Re-enable byteswap support on x86 and Power
// self()->setSupportsByteswap();
// allows [i/l]div to decompose to [i/l]mulh in TreeSimplifier
//
static char * enableMulHigh = feGetEnv("TR_X86MulHigh");
if (enableMulHigh)
{
self()->setSupportsLoweringConstIDiv();
if (comp->target().is64Bit())
self()->setSupportsLoweringConstLDiv();
}
self()->setSpillsFPRegistersAcrossCalls(); // TODO:AMD64: Are the preserved XMMRs relevant here?
// Make a conservative estimate of the boundary over which an executable instruction cannot
// be patched.
//
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.isGenuineIntel() == _targetProcessorInfo.isGenuineIntel(), "isGenuineIntel() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.isAuthenticAMD() == _targetProcessorInfo.isAuthenticAMD(), "isAuthenticAMD() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.is(OMR_PROCESSOR_X86_AMDFAMILY15H) == _targetProcessorInfo.isAMD15h(), "isAMD15h() failed\n");
int32_t boundary;
if (comp->target().cpu.isGenuineIntel() || (comp->target().cpu.isAuthenticAMD() && comp->target().cpu.is(OMR_PROCESSOR_X86_AMDFAMILY15H)))
boundary = 32;
else
{
// TR_AuthenticAMD
// TR_UnknownVendor
//
boundary = 8;
}
self()->setInstructionPatchAlignmentBoundary(boundary);
// Smallest code patching boundary that is known to work on all processors we support.
//
self()->setLowestCommonCodePatchingAlignmentBoundary(8);
self()->setPicSlotCount(0);
if (!comp->getOption(TR_DisableRegisterPressureSimulation))
{
for (int32_t i = 0; i < TR_numSpillKinds; i++)
_globalRegisterBitVectors[i].init(self()->getNumberOfGlobalRegisters(), comp->trMemory());
TR::RealRegister::RegNum vmThreadRealRegisterIndex = _linkageProperties->getMethodMetaDataRegister();
for (TR_GlobalRegisterNumber grn=0; grn < self()->getNumberOfGlobalRegisters(); grn++)
{
TR::RealRegister::RegNum reg = (TR::RealRegister::RegNum)self()->getGlobalRegister(grn);
if (grn < self()->getFirstGlobalFPR())
_globalRegisterBitVectors[ TR_gprSpill ].set(grn);
else
_globalRegisterBitVectors[ TR_fprSpill ].set(grn);
if (!self()->getProperties().isPreservedRegister(reg))
_globalRegisterBitVectors[ TR_volatileSpill ].set(grn);
if (self()->getProperties().isIntegerArgumentRegister(reg) || self()->getProperties().isFloatArgumentRegister(reg))
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
if (reg == vmThreadRealRegisterIndex)
_globalRegisterBitVectors[ TR_vmThreadSpill ].set(grn);
if (reg == TR::RealRegister::eax)
_globalRegisterBitVectors[ TR_eaxSpill ].set(grn);
if (reg == TR::RealRegister::ecx)
_globalRegisterBitVectors[ TR_ecxSpill ].set(grn);
if (reg == TR::RealRegister::edx)
_globalRegisterBitVectors[ TR_edxSpill ].set(grn);
}
}
if (comp->target().cpu.isI386())
self()->setGenerateMasmListingSyntax();
if (comp->getOption(TR_TraceRA))
{
self()->setGPRegisterIterator(new (self()->trHeapMemory()) TR::RegisterIterator(self()->machine(), TR::RealRegister::FirstGPR, TR::RealRegister::LastAssignableGPR));
self()->setFPRegisterIterator(new (self()->trHeapMemory()) TR::RegisterIterator(self()->machine(), TR::RealRegister::FirstXMMR, TR::RealRegister::LastXMMR));
}
self()->setSupportsProfiledInlining();
}
OMR::X86::CodeGenerator::CodeGenerator(TR::Compilation *comp) :
OMR::CodeGenerator(comp),
_nanoTimeTemp(NULL),
_assignmentDirection(Backward),
_lastCatchAppendInstruction(NULL),
_betterSpillPlacements(NULL),
_dataSnippetList(getTypedAllocator<TR::X86DataSnippet*>(comp->allocator())),
_spilledIntRegisters(getTypedAllocator<TR::Register*>(comp->allocator())),
_liveDiscardableRegisters(getTypedAllocator<TR::Register*>(comp->allocator())),
_dependentDiscardableRegisters(getTypedAllocator<TR::Register*>(comp->allocator())),
_clobberingInstructions(getTypedAllocator<TR::ClobberingInstruction*>(comp->allocator())),
_outlinedInstructionsList(getTypedAllocator<TR_OutlinedInstructions*>(comp->allocator())),
_numReservedIPICTrampolines(0),
_flags(0)
{
}
void
OMR::X86::CodeGenerator::initialize()
{
self()->OMR::CodeGenerator::initialize();
_clobIterator = _clobberingInstructions.begin();
}
TR::Linkage *
OMR::X86::CodeGenerator::createLinkage(TR_LinkageConventions lc)
{
TR::Compilation *comp = self()->comp();
TR::Linkage *linkage = NULL;
switch (lc)
{
case TR_Private:
// HACK HACK HACK "intentional" fall through to system linkage
case TR_Helper:
// Intentional fall through
case TR_System:
if (self()->comp()->target().isLinux() || self()->comp()->target().isOSX() || self()->comp()->target().isBSD())
{
#if defined(TR_TARGET_64BIT)
linkage = new (self()->trHeapMemory()) TR::AMD64ABILinkage(self());
#else
linkage = new (self()->trHeapMemory()) TR::IA32SystemLinkage(self());
#endif
}
else if (self()->comp()->target().isWindows())
{
#if defined(TR_TARGET_64BIT)
linkage = new (self()->trHeapMemory()) TR::AMD64Win64FastCallLinkage(self());
#else
linkage = new (self()->trHeapMemory()) TR::IA32SystemLinkage(self());
#endif
}
else
{
TR_ASSERT(0, "\nTestarossa error: Illegal linkage convention %d\n", lc);
}
break;
default :
TR_ASSERT(0, "\nTestarossa error: Illegal linkage convention %d\n", lc);
}
self()->setLinkage(lc, linkage);
return linkage;
}
void
OMR::X86::CodeGenerator::beginInstructionSelection()
{
TR::Compilation *comp = self()->comp();
_returnTypeInfoInstruction = NULL;
TR::ResolvedMethodSymbol * methodSymbol = comp->getJittedMethodSymbol();
TR::Recompilation * recompilation = comp->getRecompilationInfo();
TR::Node * startNode = comp->getStartTree()->getNode();
if (recompilation && recompilation->generatePrePrologue() != NULL)
{
// Return type info will have been generated by recompilation info
//
if (methodSymbol->getLinkageConvention() == TR_Private)
_returnTypeInfoInstruction = (TR::X86ImmInstruction*)(self()->getAppendInstruction());
if (methodSymbol->getLinkageConvention() == TR_System)
_returnTypeInfoInstruction = (TR::X86ImmInstruction*)(self()->getAppendInstruction());
}
if (methodSymbol->getLinkageConvention() == TR_Private && !_returnTypeInfoInstruction)
{
// linkageInfo word
if (self()->getAppendInstruction())
_returnTypeInfoInstruction = generateImmInstruction(DDImm4, startNode, 0, self());
else
_returnTypeInfoInstruction = new (self()->trHeapMemory()) TR::X86ImmInstruction((TR::Instruction *)NULL, DDImm4, 0, self());
}
if (methodSymbol->getLinkageConvention() == TR_System && !_returnTypeInfoInstruction)
{
// linkageInfo word
if (self()->getAppendInstruction())
_returnTypeInfoInstruction = generateImmInstruction(DDImm4, startNode, 0, self());
else
_returnTypeInfoInstruction = new (self()->trHeapMemory()) TR::X86ImmInstruction((TR::Instruction *)NULL, DDImm4, 0, self());
}
if (self()->getAppendInstruction())
generateInstruction(PROCENTRY, startNode, self());
else
new (self()->trHeapMemory()) TR::Instruction(PROCENTRY, (TR::Instruction *)NULL, self());
// Set the default FPCW to single precision mode if we are allowed to.
//
if (self()->enableSinglePrecisionMethods() && comp->getJittedMethodSymbol()->usesSinglePrecisionMode())
{
generateMemInstruction(LDCWMem, startNode, generateX86MemoryReference(self()->findOrCreate2ByteConstant(startNode, SINGLE_PRECISION_ROUND_TO_NEAREST), self()), self());
}
}
void
OMR::X86::CodeGenerator::endInstructionSelection()
{
TR::Compilation *comp = self()->comp();
if (_returnTypeInfoInstruction != NULL)
{
TR_ReturnInfo returnInfo = comp->getReturnInfo();
// Note: this will get clobbered again in code generation on AMD64
_returnTypeInfoInstruction->setSourceImmediate(returnInfo);
}
// Reset the FPCW in the dummy finally block.
//
if (self()->enableSinglePrecisionMethods() &&
comp->getJittedMethodSymbol()->usesSinglePrecisionMode())
{
TR_ASSERT(self()->getLastCatchAppendInstruction(),
"endInstructionSelection() ==> Could not find the dummy finally block!\n");
generateMemInstruction(self()->getLastCatchAppendInstruction(), LDCWMem, generateX86MemoryReference(self()->findOrCreate2ByteConstant(self()->getLastCatchAppendInstruction()->getNode(), DOUBLE_PRECISION_ROUND_TO_NEAREST), self()), self());
}
}
int32_t OMR::X86::CodeGenerator::getMaximumNumbersOfAssignableGPRs()
{
return TR::RealRegister::LastAssignableGPR - TR::RealRegister::FirstGPR + 1; // TODO:AMD64: This is including rsp
}
/*
* This method returns TRUE for all the cases we decide NOT to replace the call to CAS
* with inline assembly. The GRA and Evaluator should be consistent about whether to inline CAS natives.
*/
static bool willNotInlineCompareAndSwapNative(TR::Node *node,
int8_t size,
TR::Compilation *comp)
{
#ifdef J9_PROJECT_SPECIFIC
TR::SymbolReference *callSymRef = node->getSymbolReference();
TR::MethodSymbol *methodSymbol = callSymRef->getSymbol()->castToMethodSymbol();
if (TR::Compiler->om.canGenerateArraylets() && !node->isUnsafeGetPutCASCallOnNonArray())
return true;
static char *disableCASInlining = feGetEnv("TR_DisableCASInlining");
if (disableCASInlining /* || comp->useCompressedPointers() */)
return true;
// In Java9 the sun.misc.Unsafe JNI methods have been moved to jdk.internal,
// with a set of wrappers remaining in sun.misc to delegate to the new package.
// We can be called in this function for the wrappers (which we will
// not be converting to assembly), the new jdk.internal JNI methods or the
// Java8 sun.misc JNI methods (both of which we will convert). We can
// differentiate between these cases by testing with isNative() on the method.
if (!methodSymbol->isNative())
return true;
if (size == 4)
{
return false;
}
else if (size == 8 && comp->target().is64Bit())
{
return false;
}
else
{
if (!comp->cg()->getX86ProcessorInfo().supportsCMPXCHG8BInstruction())
return true;
return false;
}
#else
return true;
#endif
}
/** @brief Identify methods which are not transformed into inline assembly.
Some recognized methods are transformed into very simple hardcoded
assembly sequences which don't need register spills as real calls do.
@param node The TR::Node for the method call. NB this function assumes the Node is a call.
@return true if the method will be treated as a normal call, false if the method
will be converted to inline assembly.
*/
bool OMR::X86::CodeGenerator::willBeEvaluatedAsCallByCodeGen(TR::Node *node, TR::Compilation *comp)
{
TR::SymbolReference *callSymRef = node->getSymbolReference();
TR::MethodSymbol *methodSymbol = callSymRef->getSymbol()->castToMethodSymbol();
switch (methodSymbol->getRecognizedMethod())
{
#ifdef J9_PROJECT_SPECIFIC
case TR::sun_misc_Unsafe_compareAndSwapLong_jlObjectJJJ_Z:
return willNotInlineCompareAndSwapNative(node, 8, comp);
case TR::sun_misc_Unsafe_compareAndSwapInt_jlObjectJII_Z:
return willNotInlineCompareAndSwapNative(node, 4, comp);
case TR::sun_misc_Unsafe_compareAndSwapObject_jlObjectJjlObjectjlObject_Z:
return willNotInlineCompareAndSwapNative(node, (comp->target().is64Bit() && !comp->useCompressedPointers()) ? 8 : 4, comp);
#endif
default:
return true;
}
}
int32_t OMR::X86::CodeGenerator::getMaximumNumbersOfAssignableFPRs()
{
return TR::RealRegister::LastAssignableFPR - TR::RealRegister::FirstFPR + 1;
}
// X has a different concept of VR's compared to p/z but since LocalOpts needs this to be hoisted within CG,
// this method is placed here as a dummy until platform specific code is removed from LocalOpt
int32_t OMR::X86::CodeGenerator::getMaximumNumbersOfAssignableVRs()
{
return INT_MAX;
}
void OMR::X86::CodeGenerator::addLiveDiscardableRegister(TR::Register * reg)
{
_liveDiscardableRegisters.push_front(reg);
reg->setIsDiscardable();
}
void OMR::X86::CodeGenerator::removeLiveDiscardableRegister(TR::Register * reg)
{
_liveDiscardableRegisters.remove(reg);
reg->resetIsDiscardable();
}
bool OMR::X86::CodeGenerator::canNullChkBeImplicit(TR::Node * node)
{
return self()->canNullChkBeImplicit(node, true);
}
void OMR::X86::CodeGenerator::clobberLiveDiscardableRegisters(
TR::Instruction *instr,
TR::MemoryReference *mr)
{
TR::Symbol * symbol = mr->getSymbolReference().getSymbol();
if (symbol)
{
TR::ClobberingInstruction * clob = NULL;
TR_IGNode *IGNodeSym = NULL;
if (self()->getLocalsIG())
IGNodeSym = self()->getLocalsIG()->getIGNodeForEntity(symbol);
// If this instruction clobbers the source of any memory discardable register(s),
// those registers must be deactivated (marked as non-discardable) after this point.
// We record which registers are deactivated, so that we can re-activate them when
// we have assigned registers for this instruction.
auto iterator = self()->getLiveDiscardableRegisters().begin();
while (iterator != self()->getLiveDiscardableRegisters().end())
{
TR::Register *registerCursor = *iterator;
if (registerCursor->getRematerializationInfo()->isRematerializableFromMemory())
{
TR::SymbolReference * rmSymRef = registerCursor->getRematerializationInfo()->getSymbolReference();
if ((rmSymRef->getSymbol() == symbol) ||
(rmSymRef->getOffset() == mr->getSymbolReference().getOffset()))
{
if (!clob)
{
clob = new (self()->trHeapMemory()) TR::ClobberingInstruction(instr, self()->trMemory());
self()->addClobberingInstruction(clob);
}
clob->addClobberedRegister(registerCursor);
iterator = self()->getLiveDiscardableRegisters().erase(iterator);
registerCursor->resetIsDiscardable();
if (debug("dumpRemat"))
{
diagnostic("---> Clobbering %s discardable register %s at instruction %p in %s\n",
self()->getDebug()->toString(registerCursor->getRematerializationInfo()),
self()->getDebug()->getName(registerCursor),
instr, self()->comp()->signature());
}
}
// If the symbols are different but will share the same stack slot then a clobber has occurred.
//
else if (IGNodeSym != NULL)
{
TR_IGNode *IGNodeRematSym = self()->getLocalsIG()->getIGNodeForEntity(rmSymRef->getSymbol());
if ((IGNodeRematSym != NULL) &&
(IGNodeSym->getColour() == IGNodeRematSym->getColour()))
{
if (!clob)
{
clob = new (self()->trHeapMemory()) TR::ClobberingInstruction(instr, self()->trMemory());
self()->addClobberingInstruction(clob);
}
clob->addClobberedRegister(registerCursor);
iterator = self()->getLiveDiscardableRegisters().erase(iterator);
registerCursor->resetIsDiscardable();
if (debug("dumpRemat"))
{
diagnostic("---> Clobbering %s discardable register %s at instruction %p because of shared slot in %s\n",
self()->getDebug()->toString(registerCursor->getRematerializationInfo()),
self()->getDebug()->getName(registerCursor),
instr, self()->comp()->signature());
}
}
else
++iterator;
}
else
++iterator;
}
else
++iterator;
}
// If a register-dependent discardable register depends on any of the deactivated
// registers, it (and those that depend on it if any) must also be deactivated.
//
if (clob && self()->supportsIndirectMemoryRematerialization())
{
iterator = clob->getClobberedRegisters().begin();
while (iterator != clob->getClobberedRegisters().end())
{
self()->clobberLiveDependentDiscardableRegisters(clob, *iterator);
++iterator;
}
}
}
}
// During instruction selection, if we know that an instruction clobbers a
// register, we iteratively deactivate all registers that depend on registers
// that have been clobbered/deactivated.
//
void OMR::X86::CodeGenerator::clobberLiveDependentDiscardableRegisters(TR::ClobberingInstruction * clob,
TR::Register * baseReg)
{
TR_Stack<TR::Register *> worklist(self()->trMemory());
worklist.push(baseReg);
while (!worklist.isEmpty())
{
baseReg = worklist.pop();
for (auto iterator = self()->getLiveDiscardableRegisters().begin(); iterator != self()->getLiveDiscardableRegisters().end();)
{
TR::Register * candidate = *iterator;
TR_RematerializationInfo * info = candidate->getRematerializationInfo();
if (info->isIndirect() && info->getBaseRegister() == baseReg)
{
clob->addClobberedRegister(candidate);
iterator = self()->getLiveDiscardableRegisters().erase(iterator);
candidate->resetIsDiscardable();
worklist.push(candidate);
if (debug("dumpRemat"))
{
diagnostic("---> Clobbering %s discardable register %s at instruction %p in %s\n",
self()->getDebug()->toString(info), self()->getDebug()->getName(candidate), clob->getInstruction(),
self()->comp()->signature());
}
}
else
++iterator;
}
}
}
// During register assignment, rematerialisable registers dependent on
// a base register B are re-activated when the spill state of B is
// reversed (i.e. when the register assigner inserts a spill store for it).
// A candidate is only re-activated if it is discardable at the current
// program point.
//
void OMR::X86::CodeGenerator::reactivateDependentDiscardableRegisters(TR::Register * baseReg)
{
TR_Stack<TR::Register *> worklist(self()->trMemory());
worklist.push(baseReg);
if (debug("dumpRemat"))
diagnostic("---> Re-activating rematerializable registers dependent on %s: ",
self()->getDebug()->getName(baseReg));
while (!worklist.isEmpty())
{
baseReg = worklist.pop();
for (auto iterator = self()->getDependentDiscardableRegisters().begin(); iterator != self()->getDependentDiscardableRegisters().end(); ++iterator)
{
if ((*iterator)->isDiscardable() &&
(*iterator)->getRematerializationInfo()->getBaseRegister() == baseReg)
{
if (debug("dumpRemat"))
diagnostic("%s ", self()->getDebug()->getName(*iterator));
(*iterator)->getRematerializationInfo()->setActive();
// If this candidate is currently assigned, then discardable registers
// dependent on it can also be re-activated.
//
if ((*iterator)->getAssignedRegister())
worklist.push(*iterator);
}
}
}
if (debug("dumpRemat"))
diagnostic("\n");
}
// During register assignment, rematerialisable registers dependent on
// a base register B must be deactivated when B is spilled (i.e. when
// the assigner inserts a reload instruction for it).
//
void OMR::X86::CodeGenerator::deactivateDependentDiscardableRegisters(TR::Register * baseReg)
{
TR_Stack<TR::Register *> worklist(self()->trMemory());
worklist.push(baseReg);
if (debug("dumpRemat"))
diagnostic("---> Deactivating rematerialisable registers dependent on %s: ",
self()->getDebug()->getName(baseReg));
while (!worklist.isEmpty())
{
baseReg = worklist.pop();
for (auto iterator = self()->getDependentDiscardableRegisters().begin(); iterator != self()->getDependentDiscardableRegisters().end(); ++iterator)
{
if (baseReg == (*iterator)->getRematerializationInfo()->getBaseRegister())
{
if (debug("dumpRemat"))
diagnostic("%s ", self()->getDebug()->getName(*iterator));
(*iterator)->getRematerializationInfo()->resetActive();
worklist.push(*iterator);
}
}
}
if (debug("dumpRemat"))
diagnostic("\n");
}
#define ALLOWED_TO_REMATERIALIZE(x) \
(getRematerializationOptString() && strstr(getRematerializationOptString(), (x)))
#define CAN_REMATERIALIZE(x) \
(!getRematerializationOptString() || strstr(getRematerializationOptString(), (x)))
static const char *getRematerializationOptString()
{
static char *optString = feGetEnv("TR_REMAT");
return optString;
}
bool OMR::X86::CodeGenerator::supportsConstantRematerialization() { static bool b = CAN_REMATERIALIZE("constant"); return b; }
bool OMR::X86::CodeGenerator::supportsLocalMemoryRematerialization() { static bool b = CAN_REMATERIALIZE("local"); return b; }
bool OMR::X86::CodeGenerator::supportsStaticMemoryRematerialization() { static bool b = CAN_REMATERIALIZE("static"); return !CANT_REMATERIALIZE_ADDRESSES(self()) && b; }
bool OMR::X86::CodeGenerator::supportsXMMRRematerialization() { static bool b = CAN_REMATERIALIZE("xmmr"); return b; }
bool OMR::X86::CodeGenerator::supportsIndirectMemoryRematerialization() { static bool b = ALLOWED_TO_REMATERIALIZE("indirect"); return !CANT_REMATERIALIZE_ADDRESSES(self()) && b;}
bool OMR::X86::CodeGenerator::supportsAddressRematerialization() { static bool b = ALLOWED_TO_REMATERIALIZE("address"); return !CANT_REMATERIALIZE_ADDRESSES(self()) && b; }
#undef ALLOWED_TO_REMATERIALIZE
#undef CAN_REMATERIALIZE
bool
OMR::X86::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode, TR::DataType dt)
{
/*
* Most of the vector evaluators for opcodes used in AutoSIMD have been implemented.
* The cases that return false are placeholders that should be updated as support for more vector evaluators is added.
*/
// implemented vector opcodes
switch (opcode.getOpCodeValue())
{
case TR::vadd:
case TR::vsub:
if (dt == TR::Int32 || dt == TR::Int64 || dt == TR::Float || dt == TR::Double)