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ARM64Debug.cpp
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ARM64Debug.cpp
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/*******************************************************************************
* Copyright (c) 2018, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <stdint.h>
#include <string.h>
#include "ras/Debug.hpp"
#include "codegen/ARM64ConditionCode.hpp"
#include "codegen/ARM64HelperCallSnippet.hpp"
#include "codegen/ARM64Instruction.hpp"
#include "codegen/ARM64OutOfLineCodeSection.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "codegen/GCRegisterMap.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/Relocation.hpp"
#include "codegen/Snippet.hpp"
#include "env/IO.hpp"
#include "il/Block.hpp"
#include "runtime/CodeCacheManager.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "aarch64/codegen/CallSnippet.hpp"
#include "aarch64/codegen/StackCheckFailureSnippet.hpp"
namespace TR { class ARM64ForceRecompilationSnippet; }
#endif
static const char *ARM64ConditionNames[] =
{
"eq",
"ne",
"cs",
"cc",
"mi",
"pl",
"vs",
"vc",
"hi",
"ls",
"ge",
"lt",
"gt",
"le",
"al",
"nv"
};
static const char *ARM64ShiftCodeNames[] =
{
"lsl",
"lsr",
"asr",
"???"
};
static const char *ARM64ExtendCodeNames[] =
{
"uxtb",
"uxth",
"uxtw",
"uxtx",
"sxtb",
"sxth",
"sxtw",
"sxtx"
};
static const char *opCodeToNameMap[] =
{
"bad",
"cbzw",
"cbnzw",
"cbzx",
"cbnzx",
"tbz",
"tbnz",
"b_cond",
"brkarm64",
"dsb",
"dmb",
"br",
"blr",
"ret",
"b",
"bl",
"stxrb",
"stlxrb",
"ldxrb",
"ldaxrb",
"stlrb",
"ldarb",
"stxrh",
"stlxrh",
"ldxrh",
"ldaxrh",
"stlrh",
"ldarh",
"stxrw",
"stlxrw",
"stxpw",
"stlxpw",
"ldxrw",
"ldaxrw",
"ldxpw",
"ldaxpw",
"stlrw",
"ldarw",
"stxrx",
"stlxrx",
"stxpx",
"stlxpx",
"ldxrx",
"ldaxrx",
"ldxpx",
"ldaxpx",
"stlrx",
"ldarx",
"ldrw",
"vldrs",
"ldrx",
"vldrd",
"ldrsw",
"vldrq",
"prfm",
"stnpw",
"ldnpw",
"vstnps",
"vldnps",
"vstnpd",
"vldnpd",
"stnpx",
"ldnpx",
"vstnpq",
"vldnpq",
"stppostw",
"ldppostw",
"vstpposts",
"vldpposts",
"ldpswpost",
"vstppostd",
"vldppostd",
"stppostx",
"ldppostx",
"vstppostq",
"vldppostq",
"stpoffw",
"ldpoffw",
"vstpoffs",
"vldpoffs",
"ldpswoff",
"vstpoffd",
"vldpoffd",
"stpoffx",
"ldpoffx",
"vstpoffq",
"vldpoffq",
"stpprew",
"ldpprew",
"vstppres",
"vldppres",
"ldpswpre",
"vstppred",
"vldppred",
"stpprex",
"ldpprex",
"vstppreq",
"vldppreq",
"sturb",
"ldurb",
"ldursbx",
"ldursbw",
"vsturb",
"vldurb",
"vsturq",
"vldurq",
"sturh",
"ldurh",
"ldurshx",
"ldurshw",
"vsturh",
"vldurh",
"sturw",
"ldurw",
"ldursw",
"vsturs",
"vldurs",
"sturx",
"ldurx",
"prfum",
"vsturd",
"vldurd",
"strbpost",
"ldrbpost",
"ldrsbpostx",
"ldrsbpostw",
"vstrpostb",
"vldrpostb",
"vstrpostq",
"vldrpostq",
"strhpost",
"ldrhpost",
"ldrshpostx",
"ldrshpostw",
"vstrposth",
"vldrposth",
"strpostw",
"ldrpostw",
"ldrswpost",
"vstrposts",
"vldrposts",
"strpostx",
"ldrpostx",
"vstrpostd",
"vldrpostd",
"sttrb",
"ldtrb",
"ldtrsbx",
"ldtrsbw",
"sttrh",
"ldtrh",
"ldtrshx",
"ldtrshw",
"sttrw",
"ldtrw",
"ldtrsw",
"sttrx",
"ldtrx",
"strbpre",
"ldrbpre",
"ldrsbprex",
"ldrsbprew",
"vstrpreb",
"vldrpreb",
"vstrpreq",
"vldrpreq",
"strhpre",
"ldrhpre",
"ldrshprex",
"ldrshprew",
"vstrpreh",
"vldrpreh",
"strprew",
"ldrprew",
"ldrswpre",
"vstrpres",
"vldrpres",
"strprex",
"ldrprex",
"vstrpred",
"vldrpred",
"strboff",
"ldrboff",
"ldrsboffx",
"ldrsboffw",
"vstroffb",
"vldroffb",
"vstroffq",
"vldroffq",
"strhoff",
"ldrhoff",
"ldrshoffx",
"ldrshoffw",
"vstroffh",
"vldroffh",
"stroffw",
"ldroffw",
"ldrswoff",
"vstroffs",
"vldroffs",
"stroffx",
"ldroffx",
"vstroffd",
"vldroffd",
"prfmoff",
"strbimm",
"ldrbimm",
"ldrsbimmx",
"ldrsbimmw",
"vstrimmb",
"vldrimmb",
"vstrimmq",
"vldrimmq",
"strhimm",
"ldrhimm",
"ldrshimmx",
"ldrshimmw",
"vstrimmh",
"vldrimmh",
"strimmw",
"ldrimmw",
"ldrswimm",
"vstrimms",
"vldrimms",
"strimmx",
"ldrimmx",
"vstrimmd",
"vldrimmd",
"prfmimm",
"adr",
"adrp",
"addimmw",
"addsimmw",
"subimmw",
"subsimmw",
"addimmx",
"addsimmx",
"subimmx",
"subsimmx",
"andimmw",
"orrimmw",
"eorimmw",
"andsimmw",
"andimmx",
"orrimmx",
"eorimmx",
"andsimmx",
"movnw",
"movzw",
"movkw",
"movnx",
"movzx",
"movkx",
"sbfmw",
"bfmw",
"ubfmw",
"sbfmx",
"bfmx",
"ubfmx",
"extrw",
"extrx",
"andw",
"bicw",
"orrw",
"ornw",
"eorw",
"eonw",
"andsw",
"bicsw",
"andx",
"bicx",
"orrx",
"ornx",
"eorx",
"eonx",
"andsx",
"bicsx",
"addw",
"addsw",
"subw",
"subsw",
"addx",
"addsx",
"subx",
"subsx",
"addextw",
"addsextw",
"subextw",
"subsextw",
"addextx",
"addsextx",
"subextx",
"subsextx",
"adcw",
"adcsw",
"sbcw",
"sbcsw",
"adcx",
"adcsx",
"sbcx",
"sbcsx",
"ccmnw",
"ccmnx",
"ccmpw",
"ccmpx",
"ccmnimmw",
"ccmnimmx",
"ccmpimmw",
"ccmpimmx",
"cselw",
"csincw",
"csinvw",
"csnegw",
"cselx",
"csincx",
"csinvx",
"csnegx",
"maddw",
"maddx",
"smaddl",
"umaddl",
"msubw",
"msubx",
"smsubl",
"umsubl",
"smulh",
"umulh",
"fmaddd",
"fmadds",
"crc32x",
"crc32cx",
"crc32b",
"crc32cb",
"crc32h",
"crc32ch",
"crc32w",
"crc32cw",
"udivw",
"udivx",
"sdivw",
"sdivx",
"lslvw",
"lslvx",
"lsrvw",
"lsrvx",
"asrvw",
"asrvx",
"rorvw",
"rorvx",
"rbitw",
"rbitx",
"clzw",
"clzx",
"clsw",
"clsx",
"revw",
"revx",
"rev16w",
"rev16x",
"rev32",
"fmov_stow",
"fmov_wtos",
"fmov_dtox",
"fmov_xtod",
"fcvt_stod",
"fcvt_dtos",
"fcvtzs_stow",
"fcvtzs_dtow",
"fcvtzs_stox",
"fcvtzs_dtox",
"scvtf_wtos",
"scvtf_wtod",
"scvtf_xtos",
"scvtf_xtod",
"fmovimms",
"fmovimmd",
"movi0s",
"movi0d",
"fcmps",
"fcmps_zero",
"fcmpd",
"fcmpd_zero",
"fcsels",
"fcseld",
"fmovs",
"fmovd",
"fabss",
"fabsd",
"fnegs",
"fnegd",
"fsqrts",
"fsqrtd",
"fadds",
"faddd",
"fsubs",
"fsubd",
"fmuls",
"fmuld",
"fdivs",
"fdivd",
"fmaxs",
"fmaxd",
"fmins",
"fmind",
"vorr2d",
"vadd16b",
"vadd8h",
"vfadd4s",
"vfadd2d",
"vsub16b",
"vsub8h",
"vfsub4s",
"vfsub2d",
"nop",
"proc",
"fence",
"return",
"dd",
"label",
"vgdnop",
"assocreg"
};
const char *
TR_Debug::getOpCodeName(TR::InstOpCode *opCode)
{
return opCodeToNameMap[opCode->getMnemonic()];
}
void
TR_Debug::printMemoryReferenceComment(TR::FILE *pOutFile, TR::MemoryReference *mr)
{
if (pOutFile == NULL)
return;
TR::Symbol *symbol = mr->getSymbolReference()->getSymbol();
if (symbol == NULL && mr->getSymbolReference()->getOffset() == 0)
return;
trfprintf(pOutFile, "\t\t# SymRef");
print(pOutFile, mr->getSymbolReference());
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::Instruction *instr)
{
if (pOutFile == NULL)
return;
switch (instr->getKind())
{
case OMR::Instruction::IsImm:
print(pOutFile, (TR::ARM64ImmInstruction *)instr);
break;
case OMR::Instruction::IsSynchronization:
print(pOutFile, (TR::ARM64ImmInstruction *)instr); // printing handled by superclass
break;
case OMR::Instruction::IsException:
print(pOutFile, (TR::ARM64ImmInstruction *)instr); // printing handled by superclass
break;
case OMR::Instruction::IsRelocatableImm:
print(pOutFile, (TR::ARM64RelocatableImmInstruction *)instr);
break;
case OMR::Instruction::IsImmSym:
print(pOutFile, (TR::ARM64ImmSymInstruction *)instr);
break;
case OMR::Instruction::IsLabel:
print(pOutFile, (TR::ARM64LabelInstruction *)instr);
break;
case OMR::Instruction::IsConditionalBranch:
print(pOutFile, (TR::ARM64ConditionalBranchInstruction *)instr);
break;
case OMR::Instruction::IsCompareBranch:
print(pOutFile, (TR::ARM64CompareBranchInstruction *)instr);
break;
case OMR::Instruction::IsTestBitBranch:
print(pOutFile, (TR::ARM64TestBitBranchInstruction *)instr);
break;
#ifdef J9_PROJECT_SPECIFIC
case OMR::Instruction::IsVirtualGuardNOP:
print(pOutFile, (TR::ARM64VirtualGuardNOPInstruction *)instr);
break;
#endif
case OMR::Instruction::IsRegBranch:
print(pOutFile, (TR::ARM64RegBranchInstruction *)instr);
break;
case OMR::Instruction::IsAdmin:
print(pOutFile, (TR::ARM64AdminInstruction *)instr);
break;
case OMR::Instruction::IsTrg1:
print(pOutFile, (TR::ARM64Trg1Instruction *)instr);
break;
case OMR::Instruction::IsTrg1Cond:
print(pOutFile, (TR::ARM64Trg1CondInstruction *)instr);
break;
case OMR::Instruction::IsTrg1Imm:
print(pOutFile, (TR::ARM64Trg1ImmInstruction *)instr);
break;
case OMR::Instruction::IsTrg1ImmSym:
print(pOutFile, (TR::ARM64Trg1ImmSymInstruction *)instr);
break;
case OMR::Instruction::IsTrg1ZeroSrc1:
print(pOutFile, (TR::ARM64Trg1ZeroSrc1Instruction *)instr);
break;
case OMR::Instruction::IsTrg1Src1:
print(pOutFile, (TR::ARM64Trg1Src1Instruction *)instr);
break;
case OMR::Instruction::IsTrg1Src1Imm:
print(pOutFile, (TR::ARM64Trg1Src1ImmInstruction *)instr);
break;
case OMR::Instruction::IsTrg1Src2:
print(pOutFile, (TR::ARM64Trg1Src2Instruction *)instr);
break;
case OMR::Instruction::IsCondTrg1Src2:
print(pOutFile, (TR::ARM64CondTrg1Src2Instruction *)instr);
break;
case OMR::Instruction::IsTrg1Src2Shifted:
print(pOutFile, (TR::ARM64Trg1Src2ShiftedInstruction *)instr);
break;
case OMR::Instruction::IsTrg1Src2Extended:
print(pOutFile, (TR::ARM64Trg1Src2ExtendedInstruction *)instr);
break;
case OMR::Instruction::IsTrg1Src2Zero:
print(pOutFile, (TR::ARM64Trg1Src2ZeroInstruction *)instr);
break;
case OMR::Instruction::IsTrg1Src3:
print(pOutFile, (TR::ARM64Trg1Src3Instruction *)instr);
break;
case OMR::Instruction::IsTrg1Mem:
print(pOutFile, (TR::ARM64Trg1MemInstruction *)instr);
break;
case OMR::Instruction::IsMem:
print(pOutFile, (TR::ARM64MemInstruction *)instr);
break;
case OMR::Instruction::IsMemImm:
print(pOutFile, (TR::ARM64MemImmInstruction *)instr);
break;
case OMR::Instruction::IsMemSrc1:
print(pOutFile, (TR::ARM64MemSrc1Instruction *)instr);
break;
case OMR::Instruction::IsMemSrc2:
print(pOutFile, (TR::ARM64MemSrc2Instruction *)instr);
break;
case OMR::Instruction::IsTrg1MemSrc1:
print(pOutFile, (TR::ARM64Trg1MemSrc1Instruction *)instr);
break;
case OMR::Instruction::IsSrc1:
print(pOutFile, (TR::ARM64Src1Instruction *)instr);
break;
case OMR::Instruction::IsZeroSrc1Imm:
print(pOutFile, (TR::ARM64ZeroSrc1ImmInstruction *)instr);
break;
case OMR::Instruction::IsSrc2:
print(pOutFile, (TR::ARM64Src2Instruction *)instr);
break;
case OMR::Instruction::IsZeroSrc2:
print(pOutFile, (TR::ARM64ZeroSrc2Instruction *)instr);
break;
default:
TR_ASSERT(false, "unexpected instruction kind");
// fall through
case OMR::Instruction::IsNotExtended:
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s", getOpCodeName(&instr->getOpCode()));
trfflush(_comp->getOutFile());
}
}
}
void
TR_Debug::printInstructionComment(TR::FILE *pOutFile, int32_t tabStops, TR::Instruction *instr)
{
while (tabStops-- > 0)
trfprintf(pOutFile, "\t");
dumpInstructionComments(pOutFile, instr);
}
void
TR_Debug::printPrefix(TR::FILE *pOutFile, TR::Instruction *instr)
{
if (pOutFile == NULL)
return;
printPrefix(pOutFile, instr, instr->getBinaryEncoding(), instr->getBinaryLength());
TR::Node *node = instr->getNode();
trfprintf(pOutFile, "%d \t", node ? node->getByteCodeIndex() : 0);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64ImmInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t0x%08x", getOpCodeName(&instr->getOpCode()), instr->getSourceImmediate());
trfflush(_comp->getOutFile());
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64RelocatableImmInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t" POINTER_PRINTF_FORMAT "\t; %s",
getOpCodeName(&instr->getOpCode()), instr->getSourceImmediate(),
TR::ExternalRelocation::getName(instr->getReloKind()));
TR::SymbolReference *sr = instr->getSymbolReference();
if (sr)
trfprintf(pOutFile, " \"%s\"", getName(sr));
trfflush(_comp->getOutFile());
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64ImmSymInstruction *instr)
{
printPrefix(pOutFile, instr);
TR::Symbol *target = instr->getSymbolReference()->getSymbol();
const char *name = target ? getName(instr->getSymbolReference()) : 0;
if (name)
trfprintf(pOutFile, "%s \t" POINTER_PRINTF_FORMAT "\t\t; Direct Call \"%s\"", getOpCodeName(&instr->getOpCode()), instr->getAddrImmediate(), name);
else
trfprintf(pOutFile, "%s \t" POINTER_PRINTF_FORMAT, getOpCodeName(&instr->getOpCode()), instr->getAddrImmediate());
printInstructionComment(pOutFile, 1, instr);
if (instr->getDependencyConditions())
print(pOutFile, instr->getDependencyConditions());
trfflush(_comp->getOutFile());
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64LabelInstruction *instr)
{
printPrefix(pOutFile, instr);
TR::LabelSymbol *label = instr->getLabelSymbol();
TR::Snippet *snippet = label ? label->getSnippet() : NULL;
if (instr->getOpCodeValue() == TR::InstOpCode::label)
{
print(pOutFile, label);
trfprintf(pOutFile, ":");
if (label->isStartInternalControlFlow())
trfprintf(pOutFile, "\t; (Start of internal control flow)");
else if (label->isEndInternalControlFlow())
trfprintf(pOutFile, "\t; (End of internal control flow)");
}
else
{
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, label);
if (snippet)
{
trfprintf(pOutFile, " (%s)", getName(snippet));
}
}
printInstructionComment(pOutFile, 1, instr);
if (instr->getDependencyConditions())
print(pOutFile, instr->getDependencyConditions());
trfflush(_comp->getOutFile());
}
#ifdef J9_PROJECT_SPECIFIC
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64VirtualGuardNOPInstruction * instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s Site:" POINTER_PRINTF_FORMAT ", ", getOpCodeName(&instr->getOpCode()), instr->getSite());
print(pOutFile, instr->getLabelSymbol());
printInstructionComment(pOutFile, 1, instr);
if (instr->getDependencyConditions())
print(pOutFile, instr->getDependencyConditions());
trfflush(pOutFile);
}
#endif
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64ConditionalBranchInstruction *instr)
{
printPrefix(pOutFile, instr);
TR::LabelSymbol *label = instr->getLabelSymbol();
TR::Snippet *snippet = label ? label->getSnippet() : NULL;
TR_ASSERT(instr->getOpCodeValue() == TR::InstOpCode::b_cond, "Unsupported instruction for conditional branch");
trfprintf(pOutFile, "b.%s \t", ARM64ConditionNames[instr->getConditionCode()]);
print(pOutFile, label);
if (snippet)
{
trfprintf(pOutFile, " (%s)", getName(snippet));
}
printInstructionComment(pOutFile, 1, instr);
if (instr->getDependencyConditions())
print(pOutFile, instr->getDependencyConditions());
trfflush(_comp->getOutFile());
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64CompareBranchInstruction *instr)
{
printPrefix(pOutFile, instr);
TR::LabelSymbol *label = instr->getLabelSymbol();
TR::Snippet *snippet = label ? label->getSnippet() : NULL;
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getSource1Register(), TR_WordReg); trfprintf(pOutFile, ", ");
print(pOutFile, label);
if (snippet)
{
trfprintf(pOutFile, " (%s)", getName(snippet));
}
printInstructionComment(pOutFile, 1, instr);
if (instr->getDependencyConditions())
print(pOutFile, instr->getDependencyConditions());
trfflush(_comp->getOutFile());
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64TestBitBranchInstruction *instr)
{
printPrefix(pOutFile, instr);
TR::LabelSymbol *label = instr->getLabelSymbol();
TR::Snippet *snippet = label ? label->getSnippet() : NULL;
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getSource1Register(), TR_WordReg); trfprintf(pOutFile, ", ");
trfprintf(pOutFile, "#%d, ", instr->getBitPos());
print(pOutFile, label);
if (snippet)
{
trfprintf(pOutFile, " (%s)", getName(snippet));
}
printInstructionComment(pOutFile, 1, instr);
if (instr->getDependencyConditions())
print(pOutFile, instr->getDependencyConditions());
trfflush(_comp->getOutFile());
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64RegBranchInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getTargetRegister(), TR_DoubleWordReg);
printInstructionComment(pOutFile, 1, instr);
if (instr->getDependencyConditions())
print(pOutFile, instr->getDependencyConditions());
trfflush(_comp->getOutFile());
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64AdminInstruction *instr)
{
if (instr->getOpCodeValue() == TR::InstOpCode::assocreg)
{
printAssocRegDirective(pOutFile, instr);
return;
}
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s ", getOpCodeName(&instr->getOpCode()));
TR::Node *node = instr->getNode();
if (node)
{
if (node->getOpCodeValue() == TR::BBStart)
{
trfprintf(pOutFile, " (BBStart (block_%d))", node->getBlock()->getNumber());
}
else if (node->getOpCodeValue() == TR::BBEnd)
{
trfprintf(pOutFile, " (BBEnd (block_%d))", node->getBlock()->getNumber());
}
}
if (instr->getDependencyConditions())
print(pOutFile, instr->getDependencyConditions());
trfflush(pOutFile);
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64Trg1Instruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getTargetRegister(), TR_WordReg);
trfflush(_comp->getOutFile());
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64Trg1CondInstruction *instr)
{
printPrefix(pOutFile, instr);
if (instr->getOpCodeValue() == TR::InstOpCode::csincx)
{
// cset alias
trfprintf(pOutFile, "cset \t");
print(pOutFile, instr->getTargetRegister(), TR_WordReg);
trfprintf(pOutFile, ", %s", ARM64ConditionNames[cc_invert(instr->getConditionCode())]);
}
else
{
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getTargetRegister(), TR_WordReg);
trfprintf(pOutFile, ", xzr, xzr, %s", ARM64ConditionNames[instr->getConditionCode()]);
}
trfflush(_comp->getOutFile());
}
/*
* Convert 8-bit modified immediate constant used in fmovimm instructions
* to double value
*/
static double
getDoubleFromImm8(uint32_t imm8)
{
uint32_t isNegative = imm8 & 0x80;
uint32_t lower4 = imm8 & 0xf;
uint32_t upper3 = (imm8 >> 4) & 0x7;
uint32_t shift = (upper3 <= 3) ? (upper3 + 4) : (upper3 - 4);
double x = (lower4 + 16) / 16.0;
double y = (1 << shift) / 8.0;
double r = x * y;
return isNegative ? -r : r;
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64Trg1ImmInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getTargetRegister(), TR_WordReg);
TR::InstOpCode::Mnemonic op = instr->getOpCodeValue();
if ((op == TR::InstOpCode::adr) || (op == TR::InstOpCode::adrp))
{
int64_t offset = static_cast<int64_t>(static_cast<int32_t>(instr->getSourceImmediate()));
if (instr->getOpCodeValue() == TR::InstOpCode::adrp)
{
offset *= 4096;
}
trfprintf(pOutFile, ", " POINTER_PRINTF_FORMAT, (instr->getBinaryEncoding() + offset));
}
else if ((op == TR::InstOpCode::fmovimms) || (op == TR::InstOpCode::fmovimmd))
{
uint32_t imm = instr->getSourceImmediate() & 0xFF;
trfprintf(pOutFile, ", 0x%02x (%lf)", imm, getDoubleFromImm8(imm));
}
else
{
uint32_t imm = instr->getSourceImmediate() & 0xFFFF;
uint32_t shift = (instr->getSourceImmediate() & 0x30000) >> 12;
trfprintf(pOutFile, ", 0x%04x", imm);
if (shift != 0)
{
trfprintf(pOutFile, ", LSL #%d", shift);
}
}
trfflush(_comp->getOutFile());
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64Trg1ImmSymInstruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));
print(pOutFile, instr->getTargetRegister(), TR_WordReg);
trfprintf(pOutFile, ", ");
auto sym = instr->getSymbol();
if ((sym != NULL) && sym->isLabel())
{
auto label = sym->getLabelSymbol();
print(pOutFile, label);
TR::Snippet *snippet = label->getSnippet();
if (snippet)
{
trfprintf(pOutFile, "(%s)", getName(snippet));
}
}
else
{
int64_t offset = static_cast<int64_t>(static_cast<int32_t>(instr->getSourceImmediate()));
if ((instr->getOpCodeValue() != TR::InstOpCode::adr) &&
(instr->getOpCodeValue() != TR::InstOpCode::adrp))
{
// ldr literal variants
offset *= 4;
}
if (instr->getOpCodeValue() == TR::InstOpCode::adrp)
{
offset *= 4096;
}
trfprintf(pOutFile, POINTER_PRINTF_FORMAT, (instr->getBinaryEncoding() + offset));
}
trfflush(_comp->getOutFile());
}
void
TR_Debug::print(TR::FILE *pOutFile, TR::ARM64Trg1Src1Instruction *instr)
{
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s \t", getOpCodeName(&instr->getOpCode()));