-
Notifications
You must be signed in to change notification settings - Fork 392
/
BinaryEvaluator.cpp
1130 lines (1021 loc) · 36.2 KB
/
BinaryEvaluator.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*******************************************************************************
* Copyright (c) 2018, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include "codegen/ARM64Instruction.hpp"
#include "codegen/ARM64ShiftCode.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/CodeGeneratorUtils.hpp"
#include "codegen/GenerateInstructions.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "il/AutomaticSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "infra/Bit.hpp"
/**
* Generic helper that handles a number of similar binary operations.
* @param[in] node : calling node
* @param[in] regOp : the target AArch64 instruction opcode
* @param[in] regOpImm : the matching AArch64 immediate instruction opcode
* regOpImm == regOp indicates that the passed opcode has no immediate form.
* @param[in] cg : codegenerator
* @return target register
*/
static inline TR::Register *
genericBinaryEvaluator(TR::Node *node, TR::InstOpCode::Mnemonic regOp, TR::InstOpCode::Mnemonic regOpImm, bool is64Bit, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = NULL;
TR::Register *trgReg = NULL;
int64_t value = 0;
if (node->getOpCodeValue() != TR::aladd)
{
if(1 == firstChild->getReferenceCount())
{
trgReg = src1Reg;
}
else if(1 == secondChild->getReferenceCount() && secondChild->getRegister() != NULL)
{
trgReg = secondChild->getRegister();
}
else
{
trgReg = cg->allocateRegister();
}
}
else
{
/*
* Because trgReg can contain an internal pointer, we cannot use the same virtual register
* for trgReg and sources for aladd except for the case
* where src1Reg also contains an internal pointer and has the same pinning array as the node.
*/
if ((1 == firstChild->getReferenceCount()) && node->isInternalPointer() && src1Reg->containsInternalPointer() &&
(node->getPinningArrayPointer() == src1Reg->getPinningArrayPointer()))
{
trgReg = src1Reg;
}
else
{
trgReg = cg->allocateRegister();
}
}
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
if(is64Bit)
{
value = secondChild->getLongInt();
}
else
{
value = secondChild->getInt();
}
/* When regOp == regOpImm, an immediate version of the instruction does not exist. */
if(constantIsUnsignedImm12(value) && regOp != regOpImm)
{
generateTrg1Src1ImmInstruction(cg, regOpImm, node, trgReg, src1Reg, value);
}
else if (constantIsUnsignedImm12(-value) &&
(regOpImm == TR::InstOpCode::addimmw || regOpImm == TR::InstOpCode::addimmx ||
regOpImm == TR::InstOpCode::subimmw || regOpImm == TR::InstOpCode::subimmx))
{
TR::InstOpCode::Mnemonic negatedOp;
switch (regOpImm)
{
case TR::InstOpCode::addimmw:
negatedOp = TR::InstOpCode::subimmw;
break;
case TR::InstOpCode::addimmx:
negatedOp = TR::InstOpCode::subimmx;
break;
case TR::InstOpCode::subimmw:
negatedOp = TR::InstOpCode::addimmw;
break;
case TR::InstOpCode::subimmx:
negatedOp = TR::InstOpCode::addimmx;
break;
default:
TR_ASSERT(false, "Unsupported op");
}
generateTrg1Src1ImmInstruction(cg, negatedOp, node, trgReg, src1Reg, -value);
}
else
{
src2Reg = cg->allocateRegister();
if(is64Bit)
{
loadConstant64(cg, node, value, src2Reg);
}
else
{
loadConstant32(cg, node, value, src2Reg);
}
generateTrg1Src2Instruction(cg, regOp, node, trgReg, src1Reg, src2Reg);
cg->stopUsingRegister(src2Reg);
}
}
else
{
src2Reg = cg->evaluate(secondChild);
generateTrg1Src2Instruction(cg, regOp, node, trgReg, src1Reg, src2Reg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
// multiply and add
// multiply and subtract
static TR::Register *
generateMaddOrMsub(TR::Node *node, TR::Node *mulNode, TR::Node *anotherNode, TR::InstOpCode::Mnemonic op, TR::CodeGenerator *cg)
{
if ((mulNode->getOpCodeValue() == TR::imul || mulNode->getOpCodeValue() == TR::lmul) &&
mulNode->getReferenceCount() == 1 &&
mulNode->getRegister() == NULL)
{
TR::Register *trgReg = cg->allocateRegister();
TR::Register *mulSrc1Reg = cg->evaluate(mulNode->getFirstChild());
TR::Register *mulSrc2Reg = cg->evaluate(mulNode->getSecondChild());
TR::Register *src3Reg = cg->evaluate(anotherNode);
generateTrg1Src3Instruction(cg, op, node, trgReg, mulSrc1Reg, mulSrc2Reg, src3Reg);
node->setRegister(trgReg);
cg->decReferenceCount(mulNode->getFirstChild());
cg->decReferenceCount(mulNode->getSecondChild());
cg->decReferenceCount(mulNode);
cg->decReferenceCount(anotherNode);
return trgReg;
}
else
{
return NULL; // not applicable
}
}
TR::Register *
OMR::ARM64::TreeEvaluator::iaddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *retReg;
retReg = generateMaddOrMsub(node, firstChild, secondChild, TR::InstOpCode::maddw, cg); // x*y + z
if (retReg)
{
return retReg;
}
retReg = generateMaddOrMsub(node, secondChild, firstChild, TR::InstOpCode::maddw, cg); // x + y*z
if (retReg)
{
return retReg;
}
return genericBinaryEvaluator(node, TR::InstOpCode::addw, TR::InstOpCode::addimmw, false, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::laddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *retReg;
retReg = generateMaddOrMsub(node, firstChild, secondChild, TR::InstOpCode::maddx, cg); // x*y + z
if (retReg)
{
return retReg;
}
retReg = generateMaddOrMsub(node, secondChild, firstChild, TR::InstOpCode::maddx, cg); // x + y*z
if (retReg)
{
return retReg;
}
return genericBinaryEvaluator(node, TR::InstOpCode::addx, TR::InstOpCode::addimmx, true, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::isubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *retReg;
retReg = generateMaddOrMsub(node, secondChild, firstChild, TR::InstOpCode::msubw, cg); // x - y*z
if (retReg)
{
return retReg;
}
return genericBinaryEvaluator(node, TR::InstOpCode::subw, TR::InstOpCode::subimmw, false, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::lsubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *retReg;
retReg = generateMaddOrMsub(node, secondChild, firstChild, TR::InstOpCode::msubx, cg); // x - y*z
if (retReg)
{
return retReg;
}
return genericBinaryEvaluator(node, TR::InstOpCode::subx, TR::InstOpCode::subimmx, true, cg);
}
// vector add
static TR::Register *
inlineVectorBinaryOp(TR::Node *node, TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *lhsReg = NULL, *rhsReg = NULL;
lhsReg = cg->evaluate(firstChild);
rhsReg = cg->evaluate(secondChild);
TR_ASSERT(lhsReg->getKind() == TR_VRF, "unexpected Register kind\n");
TR_ASSERT(rhsReg->getKind() == TR_VRF, "unexpected Register kind\n");
TR::Register *resReg = cg->allocateRegister(TR_VRF);
node->setRegister(resReg);
generateTrg1Src2Instruction(cg, op, node, resReg, lhsReg, rhsReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return resReg;
}
TR::Register *
OMR::ARM64::TreeEvaluator::vaddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::InstOpCode::Mnemonic addOp;
switch(node->getDataType())
{
case TR::VectorInt8:
addOp = TR::InstOpCode::vadd16b;
break;
case TR::VectorInt16:
addOp = TR::InstOpCode::vadd8h;
break;
case TR::VectorFloat:
addOp = TR::InstOpCode::vfadd4s;
break;
case TR::VectorDouble:
addOp = TR::InstOpCode::vfadd2d;
break;
default:
TR_ASSERT(false, "unrecognized vector type %s\n", node->getDataType().toString());
return NULL;
}
return inlineVectorBinaryOp(node, cg, addOp);
}
TR::Register *
OMR::ARM64::TreeEvaluator::vsubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::InstOpCode::Mnemonic subOp;
switch(node->getDataType())
{
case TR::VectorInt8:
subOp = TR::InstOpCode::vsub16b;
break;
case TR::VectorInt16:
subOp = TR::InstOpCode::vsub8h;
break;
case TR::VectorFloat:
subOp = TR::InstOpCode::vfsub4s;
break;
case TR::VectorDouble:
subOp = TR::InstOpCode::vfsub2d;
break;
default:
TR_ASSERT(false, "unrecognized vector type %s\n", node->getDataType().toString());
return NULL;
}
return inlineVectorBinaryOp(node, cg, subOp);
}
// Multiply a register by a 32-bit constant
static void mulConstant32(TR::Node *node, TR::Register *treg, TR::Register *sreg, int32_t value, TR::CodeGenerator *cg)
{
if (value == 0)
{
loadConstant32(cg, node, 0, treg);
}
else if (value == 1)
{
generateMovInstruction(cg, node, treg, sreg);
}
else if (value == -1)
{
generateNegInstruction(cg, node, treg, sreg);
}
else
{
TR::Register *tmpReg = cg->allocateRegister();
loadConstant32(cg, node, value, tmpReg);
generateMulInstruction(cg, node, treg, sreg, tmpReg);
cg->stopUsingRegister(tmpReg);
}
}
// Multiply a register by a 64-bit constant
static void mulConstant64(TR::Node *node, TR::Register *treg, TR::Register *sreg, int64_t value, TR::CodeGenerator *cg)
{
if (value == 0)
{
loadConstant64(cg, node, 0, treg);
}
else if (value == 1)
{
generateMovInstruction(cg, node, treg, sreg);
}
else if (value == -1)
{
generateNegInstruction(cg, node, treg, sreg);
}
else
{
TR::Register *tmpReg = cg->allocateRegister();
loadConstant64(cg, node, value, tmpReg);
generateMulInstruction(cg, node, treg, sreg, tmpReg);
cg->stopUsingRegister(tmpReg);
}
}
TR::Register *
OMR::ARM64::TreeEvaluator::imulEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = NULL;
TR::Register *trgReg = NULL;
int32_t value = 0;
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
value = secondChild->getInt();
if (value > 0 && cg->convertMultiplyToShift(node))
{
trgReg = cg->evaluate(node);
return trgReg;
}
}
if(1 == firstChild->getReferenceCount())
{
trgReg = src1Reg;
}
else if(1 == secondChild->getReferenceCount() && (src2Reg = secondChild->getRegister()) != NULL)
{
trgReg = src2Reg;
}
else
{
trgReg = cg->allocateRegister();
}
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
mulConstant32(node, trgReg, src1Reg, value, cg);
}
else
{
TR::Register *src2Reg = cg->evaluate(secondChild);
generateMulInstruction(cg, node, trgReg, src1Reg, src2Reg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
TR::Register *
OMR::ARM64::TreeEvaluator::imulhEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Node *secondChild = node->getSecondChild();
TR::Register *src2Reg;
TR::Register *trgReg = cg->allocateRegister();
TR::Register *tmpReg = NULL;
TR::Register *zeroReg = cg->allocateRegister();
TR::RegisterDependencyConditions *cond = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(1, 1, cg->trMemory());
TR::addDependency(cond, zeroReg, TR::RealRegister::xzr, TR_GPR, cg);
// imulh is generated for constant idiv and the second child is the magic number
// assume magic number is usually a large odd number with little optimization opportunity
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
int32_t value = secondChild->getInt();
src2Reg = tmpReg = cg->allocateRegister();
loadConstant32(cg, node, value, src2Reg);
}
else
{
src2Reg = cg->evaluate(secondChild);
}
generateTrg1Src3Instruction(cg, TR::InstOpCode::smaddl, node, trgReg, src1Reg, src2Reg, zeroReg, cond);
cg->stopUsingRegister(zeroReg);
/* logical shift right by 32 bits */
uint32_t imm = 0x183F; // N=1, immr=32, imms=63
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::ubfmx, node, trgReg, trgReg, imm);
if (tmpReg)
{
cg->stopUsingRegister(tmpReg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
TR::Register *
OMR::ARM64::TreeEvaluator::lmulEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = NULL;
TR::Register *trgReg = NULL;
int64_t value = 0;
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
value = secondChild->getLongInt();
if (value > 0 && cg->convertMultiplyToShift(node))
{
trgReg = cg->evaluate(node);
return trgReg;
}
}
if(1 == firstChild->getReferenceCount())
{
trgReg = src1Reg;
}
else if(1 == secondChild->getReferenceCount() && (src2Reg = secondChild->getRegister()) != NULL)
{
trgReg = src2Reg;
}
else
{
trgReg = cg->allocateRegister();
}
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
mulConstant64(node, trgReg, src1Reg, value, cg);
}
else
{
TR::Register *src2Reg = cg->evaluate(secondChild);
generateMulInstruction(cg, node, trgReg, src1Reg, src2Reg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
static TR::Register *idivHelper(TR::Node *node, bool is64bit, TR::CodeGenerator *cg)
{
// TODO: Add checks for special cases
TR::Node *firstChild = node->getFirstChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Node *secondChild = node->getSecondChild();
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::Register *trgReg = cg->allocateRegister();
generateTrg1Src2Instruction(cg, is64bit ? TR::InstOpCode::sdivx : TR::InstOpCode::sdivw, node, trgReg, src1Reg, src2Reg);
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
static TR::Register *iremHelper(TR::Node *node, bool is64bit, TR::CodeGenerator *cg)
{
// TODO: Add checks for special cases
TR::Node *firstChild = node->getFirstChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Node *secondChild = node->getSecondChild();
TR::Register *src2Reg = cg->evaluate(secondChild);
TR::Register *tmpReg = cg->allocateRegister();
TR::Register *trgReg = cg->allocateRegister();
generateTrg1Src2Instruction(cg, is64bit ? TR::InstOpCode::sdivx : TR::InstOpCode::sdivw, node, tmpReg, src1Reg, src2Reg);
generateTrg1Src3Instruction(cg, is64bit ? TR::InstOpCode::msubx : TR::InstOpCode::msubw, node, trgReg, tmpReg, src2Reg, src1Reg);
cg->stopUsingRegister(tmpReg);
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
TR::Register *
OMR::ARM64::TreeEvaluator::lmulhEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Node *secondChild = node->getSecondChild();
TR::Register *src2Reg;
TR::Register *trgReg = cg->allocateRegister();
TR::Register *tmpReg = NULL;
// lmulh is generated for constant ldiv and the second child is the magic number
// assume magic number is usually a large odd number with little optimization opportunity
if (secondChild->getOpCode().isLoadConst() && secondChild->getRegister() == NULL)
{
int64_t value = secondChild->getLongInt();
src2Reg = tmpReg = cg->allocateRegister();
loadConstant64(cg, node, value, src2Reg);
}
else
{
src2Reg = cg->evaluate(secondChild);
}
generateTrg1Src2Instruction(cg, TR::InstOpCode::smulh, node, trgReg, src1Reg, src2Reg);
if (tmpReg)
{
cg->stopUsingRegister(tmpReg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
TR::Register *
OMR::ARM64::TreeEvaluator::idivEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return genericBinaryEvaluator(node, TR::InstOpCode::sdivw, TR::InstOpCode::sdivw, false, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::iremEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return iremHelper(node, false, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::ldivEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return genericBinaryEvaluator(node, TR::InstOpCode::sdivx, TR::InstOpCode::sdivx, true, cg);
}
TR::Register *
OMR::ARM64::TreeEvaluator::lremEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return iremHelper(node, true, cg);
}
static TR::Register *shiftHelper(TR::Node *node, TR::ARM64ShiftCode shiftType, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::ILOpCodes secondOp = secondChild->getOpCodeValue();
TR::Register *srcReg = cg->evaluate(firstChild);
TR::Register *trgReg = cg->allocateRegister();
bool is64bit = node->getDataType().isInt64();
TR::InstOpCode::Mnemonic op;
if (secondOp == TR::iconst)
{
int32_t value = secondChild->getInt();
uint32_t shift = is64bit ? (value & 0x3F) : (value & 0x1F);
switch (shiftType)
{
case TR::SH_LSL:
generateLogicalShiftLeftImmInstruction(cg, node, trgReg, srcReg, shift, is64bit);
break;
case TR::SH_LSR:
generateLogicalShiftRightImmInstruction(cg, node, trgReg, srcReg, shift, is64bit);
break;
case TR::SH_ASR:
generateArithmeticShiftRightImmInstruction(cg, node, trgReg, srcReg, shift, is64bit);
break;
default:
TR_ASSERT(false, "Unsupported shift type.");
}
}
else
{
TR::Register *shiftAmountReg = cg->evaluate(secondChild);
switch (shiftType)
{
case TR::SH_LSL:
op = is64bit ? TR::InstOpCode::lslvx : TR::InstOpCode::lslvw;
break;
case TR::SH_LSR:
op = is64bit ? TR::InstOpCode::lsrvx : TR::InstOpCode::lsrvw;
break;
case TR::SH_ASR:
op = is64bit ? TR::InstOpCode::asrvx : TR::InstOpCode::asrvw;
break;
default:
TR_ASSERT(false, "Unsupported shift type.");
}
generateTrg1Src2Instruction(cg, op, node, trgReg, srcReg, shiftAmountReg);
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
// also handles lshl
TR::Register *
OMR::ARM64::TreeEvaluator::ishlEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
if (node->getOpCodeValue() == TR::lshl)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
if (firstChild->getOpCodeValue() == TR::i2l &&
firstChild->getRegister() == NULL &&
secondChild->getOpCodeValue() == TR::iconst)
{
// Typical IL sequence in array access (sign-extend index value and shift it to left)
TR::Node *indexChild = firstChild->getFirstChild();
TR::Register *srcReg = cg->evaluate(indexChild);
TR::Register *trgReg = (indexChild->getReferenceCount() == 1) ? srcReg : cg->allocateRegister();
int32_t bitsToShift = secondChild->getInt();
int32_t imm = ((64 - bitsToShift) << 6) | 31; // immr = 64 - bitsToShift, imms = 31
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::sbfmx, node, trgReg, srcReg, imm);
node->setRegister(trgReg);
cg->recursivelyDecReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
}
return shiftHelper(node, TR::SH_LSL, cg);
}
// also handles lshr
TR::Register *
OMR::ARM64::TreeEvaluator::ishrEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return shiftHelper(node, TR::SH_ASR, cg);
}
// also handles lushr
TR::Register *
OMR::ARM64::TreeEvaluator::iushrEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return shiftHelper(node, TR::SH_LSR, cg);
}
// also handles lrol
TR::Register *
OMR::ARM64::TreeEvaluator::irolEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *trgReg = cg->gprClobberEvaluate(firstChild);
bool is64bit = node->getDataType().isInt64();
TR::InstOpCode::Mnemonic op;
if (secondChild->getOpCode().isLoadConst())
{
int32_t value = secondChild->getInt();
uint32_t shift = is64bit ? (value & 0x3F) : (value & 0x1F);
if (shift != 0)
{
shift = is64bit ? (64 - shift) : (32 - shift); // change ROL to ROR
op = is64bit ? TR::InstOpCode::extrx : TR::InstOpCode::extrw; // ROR is an alias of EXTR
generateTrg1Src2ShiftedInstruction(cg, op, node, trgReg, trgReg, trgReg, TR::SH_LSL, shift);
}
}
else
{
TR::Register *shiftAmountSrcReg;
TR::Register *shiftAmountReg;
TR::Register *tempReg;
bool useTempReg;
if (secondChild->getOpCode().isNeg() && secondChild->getRegister() == NULL && secondChild->getReferenceCount() == 1)
{
// If the second child is `ineg` and not commoned, cancel out double negation
auto shiftAmountNode = secondChild->getFirstChild();
useTempReg = is64bit && shiftAmountNode->getReferenceCount() > 1;
tempReg = useTempReg ? cg->allocateRegister() : NULL;
shiftAmountSrcReg = cg->evaluate(shiftAmountNode);
shiftAmountReg = useTempReg ? tempReg : shiftAmountSrcReg;
if (is64bit)
{
// 32->64 bit sign extension: SXTW is alias of SBFM
uint32_t imm = 0x1F; // immr=0, imms=31, N bit is pre-encoded in `sbfmx` opcode.
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::sbfmx, node, shiftAmountReg, shiftAmountSrcReg, imm);
}
cg->decReferenceCount(shiftAmountNode);
}
else
{
useTempReg = secondChild->getReferenceCount() > 1;
tempReg = useTempReg ? cg->allocateRegister() : NULL;
shiftAmountSrcReg = cg->evaluate(secondChild);
shiftAmountReg = useTempReg ? tempReg : shiftAmountSrcReg;
generateNegInstruction(cg, node, shiftAmountReg, shiftAmountSrcReg); // change ROL to ROR
if (is64bit)
{
// 32->64 bit sign extension: SXTW is alias of SBFM
uint32_t imm = 0x1F; // immr=0, imms=31, N bit is pre-encoded in `sbfmx` opcode.
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::sbfmx, node, shiftAmountReg, shiftAmountReg, imm);
}
}
op = is64bit ? TR::InstOpCode::rorvx : TR::InstOpCode::rorvw;
generateTrg1Src2Instruction(cg, op, node, trgReg, trgReg, shiftAmountReg);
if (useTempReg)
{
cg->stopUsingRegister(tempReg);
}
}
node->setRegister(trgReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);
return trgReg;
}
/**
* Helper template function that decodes bitmask for logic op codes
* @param[in] Nbit: N bit
* @param[in] immr : immr part of immediate
* @param[in] imms : imms part of immediate
* @param[out] wmask : returned immediate
* @return true if successfully decoded
*/
template<typename U>
bool
decodeBitMasksImpl(bool Nbit, uint32_t immr, uint32_t imms, U &wmask)
{
const size_t immBitLen = sizeof(U) * 8;
if ((immBitLen == 32) && Nbit)
{
return false;
}
int len = Nbit ? 6 : (31 - leadingZeroes((~imms) & 0x3f));
if ((len <= 0) || (immBitLen < (1 << len)))
{
return false;
}
uint32_t levels = (1 << len) - 1;
uint32_t s = imms & levels;
if (s == levels)
{
return false;
}
U welem = (static_cast<U>(1) << (s + 1)) - 1;
uint32_t elemLen = 1 << len;
uint32_t r = immr & levels;
U mask = (immBitLen == elemLen) ? (~static_cast<U>(0)) : (static_cast<U>(1) << elemLen) - 1;
U elem = ((welem << (elemLen - r)) | (welem >> r)) & mask;
while (elemLen < immBitLen)
{
elem |= (elem << elemLen);
elemLen *= 2;
}
wmask = elem;
return true;
}
/**
* Decodes bitmask for 32bit variants of logic op codes
* @param[in] Nbit: N bit
* @param[in] immr : immr part of immediate
* @param[in] imms : imms part of immediate
* @param[out] wmask : returned immediate
* @return true if successfully decoded
*/
bool
decodeBitMasks(bool Nbit, uint32_t immr, uint32_t imms, uint32_t &wmask)
{
return decodeBitMasksImpl(Nbit, immr, imms, wmask);
}
/**
* Decodes bitmask for 64bit variants of logic op codes
* @param[in] Nbit: N bit
* @param[in] immr : immr part of immediate
* @param[in] imms : imms part of immediate
* @param[out] wmask : returned immediate
* @return true if successfully decoded
*/
bool
decodeBitMasks(bool Nbit, uint32_t immr, uint32_t imms, uint64_t &wmask)
{
return decodeBitMasksImpl(Nbit, immr, imms, wmask);
}
/**
* Helper template function that find rotate count and ones count for value.
* @param[in] value : immediate value element
* @param[in] elementSize : element size
* @param[out] rotateCount : right rotate count
* @param[out] onesCount : number of consective ones in value
* @return true if value has contiguous ones (as elementSize-bit integer)
*/
template<typename T, typename U> inline
bool findLogicImmediateBitPattern(T value, int elementSize, int32_t &rotateCount, int32_t &onesCount)
{
U signExtendedValue = value;
const size_t size = sizeof(U) * 8;
// if elementSize is 2 or 4, ones in value are always contiguous.
if (elementSize > 4)
{
if (elementSize < size)
{
signExtendedValue = (((U)value) << (size - elementSize)) >> (size - elementSize);
}
if (!contiguousBits(signExtendedValue))
{
return false;
}
}
int32_t tz = trailingZeroes(value);
onesCount = populationCount(value);
// if value has trailing zeroes, right rorate count is elementSize - (trailing zeroes count).
// if not, right rotate count is leading ones of value (viewed as elementSize-bit integer),
// which is obtained by subtracting trailing ones count from total ones count.
rotateCount = (tz != 0) ? (elementSize - tz) : (onesCount - trailingZeroes(~value));
return true;
}
/**
* Helper function for encoding immediate value of logic instructions.
* @param[in] value : immediate value to encode
* @param[in] is64Bit : true if 64bit instruction
* @param[out] n : N bit
* @param[out] immEncoded : immr and imms encoded in 12bit field
* @return true if value can be encoded as immediate operand
*/
bool
logicImmediateHelper(uint64_t value, bool is64Bit, bool &n, uint32_t &immEncoded)
{
uint64_t mask = ~(uint64_t)0;
int elementSize = is64Bit ? 64 : 32;
// leading ones in imms
uint32_t imms = 1 << 7;
if (!is64Bit)
{
mask >>= elementSize;
imms >>= 1;
}
// all zeroes or all ones are not allowed
if ((value == 0) || (value == mask))
{
return false;
}
do
{
uint32_t highBits = value >> (elementSize /2);
uint32_t lowBits = value & (mask >> (elementSize / 2));
if (highBits != lowBits)
{
// found element size
break;
}
imms = imms | (imms >> 1);
value = lowBits;
mask >>= elementSize / 2;
elementSize /= 2;
} while (elementSize > 2);
int32_t rotateCount;
int32_t onesCount;
if (is64Bit)
{
if (!findLogicImmediateBitPattern<uint64_t, int64_t>(value, elementSize, rotateCount, onesCount))
{
return false;
}
}
else
{
if (!findLogicImmediateBitPattern<uint32_t, int32_t>((uint32_t)value, elementSize, rotateCount, onesCount))
{
return false;
}
}
TR_ASSERT((onesCount > 0) && (onesCount < elementSize), "Failed to encode imms.");
TR_ASSERT((rotateCount >= 0) && (rotateCount < elementSize), "Failed to encode immr.");
imms |= onesCount - 1;
imms &= (1 << 6) - 1;
immEncoded = (rotateCount << 6) | imms;
n = elementSize == 64;
return true;
}
/**
* Helper function that handles logic binary operations.
* @param[in] node : calling node
* @param[in] regOp : the target AArch64 instruction opcode
* @param[in] regOpImm : the matching AArch64 immediate instruction opcode
* regOpImm == regOp indicates that the passed opcode has no immediate form.
* @param[in] is64Bit : true if regOp and regOpImm are 64bit opcode.
* @param[in] cg : codegenerator
* @return target register
*/
static inline TR::Register *
logicBinaryEvaluator(TR::Node *node, TR::InstOpCode::Mnemonic regOp, TR::InstOpCode::Mnemonic regOpImm, bool is64Bit, TR::CodeGenerator *cg)
{
TR::Node *firstChild = node->getFirstChild();
TR::Node *secondChild = node->getSecondChild();
TR::Register *src1Reg = cg->evaluate(firstChild);
TR::Register *src2Reg = NULL;
TR::Register *trgReg = NULL;
int64_t value = 0;
if (1 == firstChild->getReferenceCount())
{
trgReg = src1Reg;
}
else if (1 == secondChild->getReferenceCount() && secondChild->getRegister() != NULL)
{
trgReg = secondChild->getRegister();
}
else
{