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OMRX86Instruction.hpp
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OMRX86Instruction.hpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#ifndef OMR_X86INSTRUCTION_INCL
#define OMR_X86INSTRUCTION_INCL
#include <stddef.h>
#include <stdint.h>
#include "codegen/CodeGenerator.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterRematerializationInfo.hpp"
#include "codegen/Snippet.hpp"
#include "compile/Compilation.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/TRMemory.hpp"
#include "il/ILOpCodes.hpp"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "infra/Assert.hpp"
#include "infra/List.hpp"
#include "runtime/Runtime.hpp"
#include "codegen/InstOpCode.hpp"
#include "env/CompilerEnv.hpp"
namespace TR { class LabelRelocation; }
class TR_VirtualGuardSite;
namespace TR { class X86RegMemInstruction; }
namespace TR { class X86RegRegInstruction; }
namespace TR { class UnresolvedDataSnippet; }
namespace TR { class SymbolReference; }
enum TR_X86MemoryBarrierKinds
{
NoFence = 0x00,
kLoadFence = 0x01,
kStoreFence = 0x02,
kMemoryFence = kLoadFence | kStoreFence,
LockOR = 0x04,
NeedsExplicitBarrier = LockOR | kMemoryFence,
LockPrefix = 0x08
};
extern int32_t memoryBarrierRequired(TR_X86OpCode &op, TR::MemoryReference *mr, TR::CodeGenerator *cg, bool onlyAskingAboutFences);
extern int32_t estimateMemoryBarrierBinaryLength(int32_t barrier, TR::CodeGenerator *cg);
extern void padUnresolvedReferenceInstruction(TR::Instruction *instr, TR::MemoryReference *mr, TR::CodeGenerator *cg);
extern void insertUnresolvedReferenceInstructionMemoryBarrier(TR::CodeGenerator *cg, int32_t barrier, TR::Instruction *inst, TR::MemoryReference *mr, TR::Register *srcReg = NULL, TR::MemoryReference *anotherMr = NULL);
struct TR_AtomicRegion
{
uint8_t _start, _length;
// Note: Lists of TR_AtomicRegions are null-terminated; ie. they end with
// an entry having zero length.
uint8_t getStart() const { return _start; }
uint8_t getLength() const { return _length; }
};
namespace TR
{
class X86PaddingInstruction : public TR::Instruction
{
uint8_t _length;
TR_PaddingProperties _properties;
public:
X86PaddingInstruction(uint8_t length, TR::Node *node, TR::CodeGenerator *cg):
TR::Instruction(node, BADIA32Op, cg),
_length(length),
_properties(TR_NoOpPadding)
{}
X86PaddingInstruction(uint8_t length, TR_PaddingProperties properties, TR::Node *node, TR::CodeGenerator *cg):
TR::Instruction(node, BADIA32Op, cg),
_length(length),
_properties(properties)
{}
X86PaddingInstruction(TR::Instruction *precedingInstruction, uint8_t length, TR::CodeGenerator *cg):
TR::Instruction(BADIA32Op, precedingInstruction, cg),
_length(length),
_properties(TR_NoOpPadding)
{}
X86PaddingInstruction(TR::Instruction *precedingInstruction, uint8_t length, TR_PaddingProperties properties, TR::CodeGenerator *cg):
TR::Instruction(BADIA32Op, precedingInstruction, cg),
_length(length),
_properties(properties)
{}
uint8_t getLength() { return _length; }
TR_PaddingProperties getProperties(){ return _properties; }
virtual uint8_t *generateBinaryEncoding();
virtual int32_t estimateBinaryLength(int32_t currentEstimate);
virtual char *description() { return "X86RegMem"; }
virtual Kind getKind() { return IsPadding; }
};
class X86PaddingSnippetInstruction : public TR::X86PaddingInstruction
{
TR::UnresolvedDataSnippet *_unresolvedSnippet;
public:
X86PaddingSnippetInstruction(uint8_t length, TR::Node *node, TR::CodeGenerator *cg):
TR::X86PaddingInstruction(length, node, cg),
_unresolvedSnippet(NULL)
{}
X86PaddingSnippetInstruction(uint8_t length, TR_PaddingProperties properties, TR::Node *node, TR::CodeGenerator *cg):
TR::X86PaddingInstruction(length, properties, node, cg),
_unresolvedSnippet(NULL)
{}
X86PaddingSnippetInstruction(TR::Instruction *precedingInstruction, uint8_t length, TR::CodeGenerator *cg):
TR::X86PaddingInstruction(precedingInstruction, length, cg),
_unresolvedSnippet(NULL)
{}
X86PaddingSnippetInstruction(TR::Instruction *precedingInstruction, uint8_t length, TR_PaddingProperties properties, TR::CodeGenerator *cg):
TR::X86PaddingInstruction(precedingInstruction, length, properties, cg),
_unresolvedSnippet(NULL)
{}
virtual char *description() { return "PaddingSnippetInstruction"; }
virtual TR::Snippet *getSnippetForGC();
TR::UnresolvedDataSnippet *getUnresolvedSnippet() {return _unresolvedSnippet;}
TR::UnresolvedDataSnippet *setUnresolvedSnippet(TR::UnresolvedDataSnippet *us)
{
return (_unresolvedSnippet = us);
}
};
class X86BoundaryAvoidanceInstruction : public TR::Instruction
{
// Inserts NOPs to ensure that none of the atomicRegions in the adjacent
// targetCode cross a boundary (as specified by boundarySpacing).
public:
X86BoundaryAvoidanceInstruction(const TR_AtomicRegion *atomicRegions,
uint8_t boundarySpacing,
uint8_t maxPadding,
TR::Instruction *targetCode,
TR::CodeGenerator *cg)
: TR::Instruction(BADIA32Op, targetCode->getPrev(), cg),
_sizeOfProtectiveNop(0), _atomicRegions(atomicRegions), _boundarySpacing(boundarySpacing), _maxPadding(maxPadding), _targetCode(targetCode), _minPaddingLength(0)
{
setNode(targetCode->getNode());
}
X86BoundaryAvoidanceInstruction(int32_t sizeOfProtectiveNop,
const TR_AtomicRegion *atomicRegions,
uint8_t boundarySpacing,
uint8_t maxPadding,
TR::Instruction *targetCode,
TR::CodeGenerator *cg)
: TR::Instruction(BADIA32Op, targetCode->getPrev(), cg),
_sizeOfProtectiveNop(sizeOfProtectiveNop), _atomicRegions(atomicRegions),
_boundarySpacing(boundarySpacing), _maxPadding(maxPadding), _targetCode(targetCode),
_minPaddingLength(0)
{
setNode(targetCode->getNode());
}
X86BoundaryAvoidanceInstruction(TR::Instruction *precedingInstruction,
const TR_AtomicRegion *atomicRegions,
uint8_t boundarySpacing,
uint8_t maxPadding,
TR::CodeGenerator *cg)
: TR::Instruction(BADIA32Op, precedingInstruction, cg),
_atomicRegions(atomicRegions), _boundarySpacing(boundarySpacing), _maxPadding(maxPadding), _targetCode(NULL),
_sizeOfProtectiveNop(0), _minPaddingLength(0)
{
// Note: this constructor is usually not the right one to use, because
// when you want to make something patchable, you usually know what
// you're patching. That's why there's no generateXXX function for this.
// However, there are unusual cases where we don't care what we're
// patching, so we provide this extra constructor.
//
// Notice that the order of the arguments is crucial to avoid calling the
// wrong constructor.
}
const TR_AtomicRegion *getAtomicRegions() { return _atomicRegions; }
uint8_t getBoundarySpacing() { return _boundarySpacing; }
uint8_t getMaxPadding() { return _maxPadding; }
TR::Instruction *getTargetCode() { return _targetCode; }
int32_t getSizeOfProtectiveNop() { return _sizeOfProtectiveNop; }
virtual void assignRegisters(TR_RegisterKinds kindsToBeAssigned);
virtual int32_t estimateBinaryLength(int32_t currentEstimate);
virtual uint8_t *generateBinaryEncoding();
virtual OMR::X86::EnlargementResult enlarge(int32_t requestedEnlargementSize, int32_t maxEnlargementSize, bool allowPartialEnlargement);
virtual char *description() { return "X86BoundaryAvoidance"; }
virtual Kind getKind() { return IsBoundaryAvoidance; }
static TR_AtomicRegion unresolvedAtomicRegions[]; // For patching unresolved references
protected:
virtual int32_t betterPadLength(int32_t oldPadLength, const TR_AtomicRegion *unaccommodatedRegion, int32_t unaccommodatedRegionStart);
private:
const TR_AtomicRegion *_atomicRegions;
uint8_t _boundarySpacing;
uint8_t _maxPadding;
TR::Instruction *_targetCode; // if NULL, _next will be padded instead
int32_t _sizeOfProtectiveNop;
uint8_t _minPaddingLength;
};
class X86PatchableCodeAlignmentInstruction : public TR::X86BoundaryAvoidanceInstruction
{
public:
// Note: we use cg->getInstructionPatchAlignmentBoundary() as the max padding,
// even though that is 1 more byte than we should ever actually need. The reason is
// that we don't want the inherited logic to stop silently when it reaches this limit;
// rather, we want it to try to add more padding, and trip on an assertion inside
// the betterPadLength function so that we are alerted to the problem.
X86PatchableCodeAlignmentInstruction(const TR_AtomicRegion *atomicRegions,
TR::Instruction *patchableCode,
TR::CodeGenerator *cg)
: TR::X86BoundaryAvoidanceInstruction(atomicRegions, cg->getInstructionPatchAlignmentBoundary(), cg->getInstructionPatchAlignmentBoundary(), patchableCode, cg)
{}
X86PatchableCodeAlignmentInstruction(const TR_AtomicRegion *atomicRegions,
TR::Instruction *patchableCode,
int32_t sizeOfProtectiveNop,
TR::CodeGenerator *cg)
: TR::X86BoundaryAvoidanceInstruction(sizeOfProtectiveNop, atomicRegions, cg->getInstructionPatchAlignmentBoundary(), cg->getInstructionPatchAlignmentBoundary(), patchableCode, cg)
{}
X86PatchableCodeAlignmentInstruction(TR::Instruction *precedingInstruction,
const TR_AtomicRegion *atomicRegions,
TR::CodeGenerator *cg)
: TR::X86BoundaryAvoidanceInstruction(precedingInstruction, atomicRegions, cg->getInstructionPatchAlignmentBoundary(), cg->getInstructionPatchAlignmentBoundary(), cg)
{
// Note: this constructor is usually not the right one to use. See the
// note in the corresponding TR::X86BoundaryAvoidanceInstruction
// constructor for more information (search for "generateXXX").
}
TR::Instruction *getPatchableCode(){ return getTargetCode(); }
virtual char *description() { return "PatchableCodeAlignment"; }
virtual Kind getKind() { return IsPatchableCodeAlignment; }
virtual int32_t betterPadLength(int32_t oldPadLength, const TR_AtomicRegion *unaccommodatedRegion, int32_t unaccommodatedRegionStart);
// A few handy atomic region descriptors
static TR_AtomicRegion spinLoopAtomicRegions[]; // For any patching done using a 2-byte self-loop
static TR_AtomicRegion CALLImm4AtomicRegions[]; // For patching the displacement of a 5-byte call instruction
};
class X86LabelInstruction : public TR::Instruction
{
TR::LabelSymbol *_symbol;
TR::X86LabelInstruction *_outlinedInstructionBranch;
bool _needToClearFPStack;
uint8_t _reloType;
bool _permitShortening;
void initialize(TR::LabelSymbol *sym, bool b);
public:
X86LabelInstruction(TR_X86OpCodes op, TR::Node * node, TR::LabelSymbol *sym, TR::CodeGenerator *cg, bool b = false);
X86LabelInstruction(TR::Instruction *precedingInstruction, TR_X86OpCodes op, TR::LabelSymbol *sym, TR::CodeGenerator *cg, bool b = false);
X86LabelInstruction(TR_X86OpCodes op, TR::Node *node, TR::LabelSymbol *sym, TR::RegisterDependencyConditions *cond, TR::CodeGenerator *cg, bool b = false);
X86LabelInstruction(TR::Instruction *precedingInstruction, TR_X86OpCodes op, TR::LabelSymbol *sym, TR::RegisterDependencyConditions *cond, TR::CodeGenerator *cg, bool b = false);
void prohibitShortening() { _permitShortening = false; }
virtual char *description() { return "X86LabelInstruction"; }
virtual bool isPatchBarrier() { return getOpCodeValue() == LABEL && _symbol && _symbol->isTargeted() != TR_no; }
uint8_t getReloType() {return _reloType; };
void setReloType(uint8_t rt) { _reloType = rt;};
virtual Kind getKind() { return IsLabel; }
TR::LabelSymbol *getLabelSymbol() {return _symbol;}
TR::LabelSymbol *setLabelSymbol(TR::LabelSymbol *sym) {return (_symbol = sym);}
bool getNeedToClearFPStack() {return _needToClearFPStack;}
void setNeedToClearFPStack(bool b) {_needToClearFPStack = b;}
virtual TR::Snippet *getSnippetForGC();
virtual uint8_t *generateBinaryEncoding();
virtual int32_t estimateBinaryLength(int32_t currentEstimate);
virtual void assignRegisters(TR_RegisterKinds kindsToBeAssigned);
virtual uint8_t getBinaryLengthLowerBound();
virtual OMR::X86::EnlargementResult enlarge(int32_t requestedEnlargementSize, int32_t maxEnlargementSize, bool allowPartialEnlargement);
virtual void addMetaDataForCodeAddress(uint8_t *cursor);
virtual TR::X86LabelInstruction *getX86LabelInstruction();
void assignOutlinedInstructions(TR_RegisterKinds kindsToBeAssigned, TR::X86LabelInstruction *labelInstruction);
void addPostDepsToOutlinedInstructionsBranch();
void setOutlinedInstructionBranch(TR::X86LabelInstruction *li) {_outlinedInstructionBranch = li;}
};
class X86AlignmentInstruction : public TR::Instruction
{
uint8_t _boundary, _margin, _minPaddingLength;
public:
virtual char *description() { return "X86Alignment"; }
virtual Kind getKind() { return IsAlignment; }
uint8_t getBoundary() { return _boundary; }
uint8_t getMargin() { return _margin; }
// The 8 constructor permutations:
// - node vs. preceding instruction
// - with vs. without margin
// - with vs. without dependencies
X86AlignmentInstruction(TR::Node * node, uint8_t boundary, TR::CodeGenerator *cg)
: TR::Instruction(node, BADIA32Op, cg),
_boundary(boundary),
_margin(0),
_minPaddingLength(0)
{}
X86AlignmentInstruction(TR::Node * node, uint8_t boundary, TR::RegisterDependencyConditions *cond, TR::CodeGenerator *cg)
: TR::Instruction(cond, node, BADIA32Op, cg),
_boundary(boundary),
_margin(0),
_minPaddingLength(0)
{}
X86AlignmentInstruction(TR::Node * node, uint8_t boundary, uint8_t margin, TR::CodeGenerator *cg)
: TR::Instruction(node, BADIA32Op, cg),
_boundary(boundary),
_margin(margin),
_minPaddingLength(0)
{}
X86AlignmentInstruction(TR::Node * node, uint8_t boundary, uint8_t margin, TR::RegisterDependencyConditions *cond, TR::CodeGenerator *cg)
: TR::Instruction(cond, node, BADIA32Op, cg),
_boundary(boundary),
_margin(margin),
_minPaddingLength(0)
{}
X86AlignmentInstruction(TR::Instruction *precedingInstruction, uint8_t boundary, TR::CodeGenerator *cg)
: TR::Instruction(BADIA32Op, precedingInstruction, cg),
_boundary(boundary),
_margin(0),
_minPaddingLength(0)
{}
X86AlignmentInstruction(TR::Instruction *precedingInstruction, uint8_t boundary, TR::RegisterDependencyConditions *cond, TR::CodeGenerator *cg)
: TR::Instruction(cond, BADIA32Op, precedingInstruction, cg),
_boundary(boundary),
_margin(0),
_minPaddingLength(0)
{}
X86AlignmentInstruction(TR::Instruction *precedingInstruction, uint8_t boundary, uint8_t margin, TR::CodeGenerator *cg)
: TR::Instruction(BADIA32Op, precedingInstruction, cg),
_boundary(boundary),
_margin(margin),
_minPaddingLength(0)
{}
X86AlignmentInstruction(TR::Instruction *precedingInstruction, uint8_t boundary, uint8_t margin, TR::RegisterDependencyConditions *cond, TR::CodeGenerator *cg)
: TR::Instruction(cond, BADIA32Op, precedingInstruction, cg),
_boundary(boundary),
_margin(margin),
_minPaddingLength(0)
{}
virtual int32_t estimateBinaryLength(int32_t currentEstimate);
virtual uint8_t *generateBinaryEncoding();
virtual OMR::X86::EnlargementResult enlarge(int32_t requestedEnlargementSize, int32_t maxEnlargementSize, bool allowPartialEnlargement);
};
class X86FenceInstruction : public TR::Instruction
{
TR::Node * _fenceNode; // todo: replace uses of this with TR::Instruction::_node
public:
X86FenceInstruction(TR_X86OpCodes op,
TR::Node *,
TR::Node *n,
TR::CodeGenerator *cg);
X86FenceInstruction(TR::Instruction *precedingInstruction,
TR_X86OpCodes op,
TR::Node *n,
TR::CodeGenerator *cg);
virtual char *description() { return "X86Fence"; }
virtual Kind getKind() { return IsFence; }
TR::Node * getFenceNode() { return _fenceNode; }
virtual uint8_t *generateBinaryEncoding();
virtual void addMetaDataForCodeAddress(uint8_t *cursor);
};
#ifdef J9_PROJECT_SPECIFIC
class X86VirtualGuardNOPInstruction : public TR::X86LabelInstruction
{
private:
TR_VirtualGuardSite *_site;
// These fields are set after binary encoding
TR::RealRegister::RegNum _register;
int32_t _nopSize;
public:
X86VirtualGuardNOPInstruction(TR_X86OpCodes op,
TR::Node *node,
TR_VirtualGuardSite *site,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg,
TR::LabelSymbol *label = 0)
: TR::X86LabelInstruction(op, node, label, cond, cg), _site(site), _nopSize(0), _register(TR::RealRegister::NoReg) {}
X86VirtualGuardNOPInstruction(TR::Instruction *precedingInstruction,
TR_X86OpCodes op,
TR::Node *node,
TR_VirtualGuardSite *site,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg,
TR::LabelSymbol *label = 0)
: TR::X86LabelInstruction(precedingInstruction, op, label, cond, cg), _site(site), _nopSize(0), _register(TR::RealRegister::NoReg) { setNode(node); }
virtual char *description() { return "X86VirtualGuardNOP"; }
virtual Kind getKind() { return IsVirtualGuardNOP; }
void setSite(TR_VirtualGuardSite *site) { _site = site; }
TR_VirtualGuardSite * getSite() { return _site; }
virtual uint8_t *generateBinaryEncoding();
virtual int32_t estimateBinaryLength(int32_t currentEstimate);
virtual bool isVirtualGuardNOPInstruction() {return true;}
virtual bool defsRegister(TR::Register *reg);
virtual bool usesRegister(TR::Register *reg);
virtual bool refsRegister(TR::Register *reg);
};
#endif
class X86ImmInstruction : public TR::Instruction
{
int32_t _sourceImmediate;
int32_t _adjustsFramePointerBy; // TODO: Rename me. Calls don't adjust the VFP per se; they adjust the stack pointer
int32_t _reloKind;
public:
X86ImmInstruction(TR::Node * node, TR_X86OpCodes op, TR::CodeGenerator *cg, int32_t reloKind=TR_NoRelocation)
: TR::Instruction(node, op, cg),
_sourceImmediate(0),
_adjustsFramePointerBy(0),
_reloKind(reloKind)
{
}
X86ImmInstruction(int32_t imm, TR::Node * node, TR_X86OpCodes op, TR::CodeGenerator *cg, int32_t reloKind=TR_NoRelocation)
: TR::Instruction(node, op, cg),
_sourceImmediate(imm),
_adjustsFramePointerBy(0),
_reloKind(reloKind)
{
}
X86ImmInstruction(int32_t imm,
TR_X86OpCodes op,
TR::Instruction *precedingInstruction,
TR::CodeGenerator *cg,
int32_t reloKind=TR_NoRelocation)
: TR::Instruction(op, precedingInstruction, cg),
_sourceImmediate(imm),
_adjustsFramePointerBy(0),
_reloKind(reloKind)
{}
X86ImmInstruction(TR::RegisterDependencyConditions *cond,
int32_t imm,
TR::Node *node,
TR_X86OpCodes op,
TR::CodeGenerator *cg,
int32_t reloKind=TR_NoRelocation)
: TR::Instruction(cond, node, op, cg),
_sourceImmediate(imm),
_adjustsFramePointerBy(0),
_reloKind(reloKind)
{}
X86ImmInstruction(TR::RegisterDependencyConditions *cond,
int32_t imm,
TR_X86OpCodes op,
TR::Instruction *precedingInstruction,
TR::CodeGenerator *cg,
int32_t reloKind=TR_NoRelocation)
: TR::Instruction(cond, op, precedingInstruction, cg),
_sourceImmediate(imm),
_adjustsFramePointerBy(0),
_reloKind(reloKind)
{
if (cond && cg->enableRegisterAssociations())
cond->createRegisterAssociationDirective(this, cg);
}
X86ImmInstruction(TR_X86OpCodes op,
TR::Node *node,
int32_t imm,
TR::CodeGenerator *cg,
int32_t reloKind=TR_NoRelocation);
X86ImmInstruction(TR::Instruction *precedingInstruction,
TR_X86OpCodes op,
int32_t imm,
TR::CodeGenerator *cg,
int32_t reloKind=TR_NoRelocation);
X86ImmInstruction(TR_X86OpCodes op,
TR::Node *node,
int32_t imm,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg,
int32_t reloKind=TR_NoRelocation);
X86ImmInstruction(TR::Instruction *precedingInstruction,
TR_X86OpCodes op,
int32_t imm,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg,
int32_t reloKind=TR_NoRelocation);
virtual char *description() { return "X86Imm"; }
virtual Kind getKind() { return IsImm; }
int32_t getSourceImmediate() {return _sourceImmediate;}
uint32_t getSourceImmediateAsAddress() {return (uint32_t)_sourceImmediate;}
int32_t setSourceImmediate(int32_t si) {return (_sourceImmediate = si);}
void setAdjustsFramePointerBy(int32_t a) {_adjustsFramePointerBy = a;}
int32_t getAdjustsFramePointerBy() {return _adjustsFramePointerBy;}
int32_t getReloKind() {return _reloKind;}
void setReloKind(int32_t reloKind) {_reloKind = reloKind;}
virtual uint8_t* generateOperand(uint8_t* cursor);
virtual int32_t estimateBinaryLength(int32_t currentEstimate);
virtual uint8_t getBinaryLengthLowerBound();
virtual void addMetaDataForCodeAddress(uint8_t *cursor);
#if defined(DEBUG) || defined(PROD_WITH_ASSUMES)
// The following safe virtual downcast method is used under debug only
// for assertion checking.
//
virtual X86ImmInstruction *getX86ImmInstruction();
#endif
virtual void adjustVFPState(TR_VFPState *state, TR::CodeGenerator *cg){ adjustVFPStateForCall(state, _adjustsFramePointerBy, cg); }
};
class X86ImmSnippetInstruction : public TR::X86ImmInstruction
{
TR::UnresolvedDataSnippet *_unresolvedSnippet;
public:
X86ImmSnippetInstruction(TR_X86OpCodes op,
TR::Node *node,
int32_t imm,
TR::UnresolvedDataSnippet *us,
TR::CodeGenerator *cg);
X86ImmSnippetInstruction(TR::Instruction *precedingInstruction,
TR_X86OpCodes op,
int32_t imm,
TR::UnresolvedDataSnippet *us,
TR::CodeGenerator *cg);
virtual char *description() { return "X86ImmSnippet"; }
virtual Kind getKind() { return IsImmSnippet; }
TR::UnresolvedDataSnippet *getUnresolvedSnippet() {return _unresolvedSnippet;}
TR::UnresolvedDataSnippet *setUnresolvedSnippet(TR::UnresolvedDataSnippet *us)
{
return (_unresolvedSnippet = us);
}
virtual TR::Snippet *getSnippetForGC();
virtual uint8_t* generateOperand(uint8_t* cursor);
virtual void addMetaDataForCodeAddress(uint8_t *cursor);
};
class X86ImmSymInstruction : public TR::X86ImmInstruction
{
TR::SymbolReference *_symbolReference;
public:
X86ImmSymInstruction(TR_X86OpCodes op,
TR::Node *node,
int32_t imm,
TR::SymbolReference *sr,
TR::CodeGenerator *cg);
X86ImmSymInstruction(TR::Instruction *precedingInstruction,
TR_X86OpCodes op,
int32_t imm,
TR::SymbolReference *sr,
TR::CodeGenerator *cg);
X86ImmSymInstruction(TR_X86OpCodes op,
TR::Node *node,
int32_t imm,
TR::SymbolReference *sr,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg);
X86ImmSymInstruction(TR::Instruction *precedingInstruction,
TR_X86OpCodes op,
int32_t imm,
TR::SymbolReference *sr,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg);
virtual char *description() { return "X86ImmSym"; }
virtual Kind getKind() { return IsImmSym; }
TR::SymbolReference *getSymbolReference() {return _symbolReference;}
TR::SymbolReference *setSymbolReference(TR::SymbolReference *sr)
{
return (_symbolReference = sr);
}
void addMetaDataForCodeAddress(uint8_t *cursor);
virtual uint8_t* generateOperand(uint8_t* cursor);
virtual int32_t estimateBinaryLength(int32_t currentEstimate);
};
class X86RegInstruction : public TR::Instruction
{
TR::Register *_targetRegister;
public:
X86RegInstruction(TR::Register *reg,
TR::Node *node,
TR_X86OpCodes op,
TR::CodeGenerator *cg)
: TR::Instruction(node, op, cg), _targetRegister(reg)
{
TR::Compilation *comp = cg->comp();
useRegister(reg);
getOpCode().trackUpperBitsOnReg(reg, cg);
// Check the live discardable register list to see if this is the first
// instruction that kills the rematerializable range of a register.
//
if (cg->enableRematerialisation() &&
reg->isDiscardable() &&
getOpCode().modifiesTarget())
{
TR::ClobberingInstruction *clob = new (cg->trHeapMemory()) TR::ClobberingInstruction(this, cg->trMemory());
clob->addClobberedRegister(reg);
cg->addClobberingInstruction(clob);
cg->removeLiveDiscardableRegister(reg);
cg->clobberLiveDependentDiscardableRegisters(clob, reg);
if (debug("dumpRemat"))
{
diagnostic("---> Clobbering %s discardable register %s at instruction %p\n",
reg->getRematerializationInfo()->toString(comp), reg->getRegisterName(comp), this);
}
}
}
X86RegInstruction(TR::Register *reg,
TR_X86OpCodes op,
TR::Instruction *precedingInstruction,
TR::CodeGenerator *cg)
: TR::Instruction(op, precedingInstruction, cg), _targetRegister(reg)
{
useRegister(reg);
getOpCode().trackUpperBitsOnReg(reg, cg);
}
X86RegInstruction(TR::RegisterDependencyConditions *cond,
TR::Register *reg,
TR::Node *node,
TR_X86OpCodes op,
TR::CodeGenerator *cg)
: TR::Instruction(cond, node, op, cg), _targetRegister(reg)
{
TR::Compilation *comp = cg->comp();
useRegister(reg);
getOpCode().trackUpperBitsOnReg(reg, cg);
// Check the live discardable register list to see if this is the first
// instruction that kills the rematerializable range of a register.
//
if (cg->enableRematerialisation() &&
reg->isDiscardable() &&
getOpCode().modifiesTarget())
{
TR::ClobberingInstruction *clob = new (cg->trHeapMemory()) TR::ClobberingInstruction(this, cg->trMemory());
clob->addClobberedRegister(reg);
cg->addClobberingInstruction(clob);
cg->removeLiveDiscardableRegister(reg);
cg->clobberLiveDependentDiscardableRegisters(clob, reg);
if (debug("dumpRemat"))
{
diagnostic("---> Clobbering %s discardable register %s at instruction %p\n",
reg->getRematerializationInfo()->toString(comp), reg->getRegisterName(comp), this);
}
}
}
X86RegInstruction(TR::RegisterDependencyConditions *cond,
TR::Register *reg,
TR_X86OpCodes op,
TR::Instruction *precedingInstruction,
TR::CodeGenerator *cg)
: TR::Instruction(cond, op, precedingInstruction, cg), _targetRegister(reg)
{
useRegister(reg);
getOpCode().trackUpperBitsOnReg(reg, cg);
}
X86RegInstruction(TR_X86OpCodes op, TR::Node * node, TR::Register *reg, TR::CodeGenerator *cg);
X86RegInstruction(TR::Instruction *precedingInstruction,
TR_X86OpCodes op,
TR::Register *reg,
TR::CodeGenerator *cg);
X86RegInstruction(TR_X86OpCodes op,
TR::Node *node,
TR::Register *reg,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg);
X86RegInstruction(TR::Instruction *precedingInstruction,
TR_X86OpCodes op,
TR::Register *reg,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg);
virtual char *description() { return "X86Reg"; }
virtual Kind getKind() { return IsReg; }
virtual TR::X86RegInstruction *getX86RegInstruction();
virtual TR::X86RegRegInstruction *getIA32RegRegInstruction() {return NULL;}
virtual TR::X86RegMemInstruction *getIA32RegMemInstruction() {return NULL;}
virtual TR::Register *getTargetRegister() {return _targetRegister;}
TR::Register *setTargetRegister(TR::Register *r) {return (_targetRegister = r);}
void applyTargetRegisterToModRMByte(uint8_t *modRM)
{
TR::RealRegister *target = toRealRegister(_targetRegister);
if (getOpCode().hasTargetRegisterInModRM())
{
target->setRMRegisterFieldInModRM(modRM);
}
else if (getOpCode().hasTargetRegisterInOpcode())
{
target->setRegisterFieldInOpcode(modRM);
}
else
{
// If not in RM field and not in opcode, then must have a reg field in ModRM byte
//
target->setRegisterFieldInModRM(modRM);
}
}
#if defined(TR_TARGET_64BIT)
virtual uint8_t rexBits()
{
return operandSizeRexBits() | targetRegisterRexBits();
}
uint8_t targetRegisterRexBits()
{
// Determine where the 4th register bit (if any) should go
//
uint8_t rxbBitmask;
if (getOpCode().hasTargetRegisterInModRM())
rxbBitmask = TR::RealRegister::REX_B;
else if (getOpCode().hasTargetRegisterInOpcode())
rxbBitmask = TR::RealRegister::REX_B;
else // If not in RM field and not in opcode, then must have a reg field in ModRM byte
rxbBitmask = TR::RealRegister::REX_R;
// Add the appropriate bits to the Rex prefix byte
//
TR::RealRegister *target = toRealRegister(_targetRegister);
return target->rexBits(rxbBitmask, getOpCode().hasByteTarget() ? true : false);
}
#endif
virtual uint8_t* generateOperand(uint8_t* cursor);
virtual int32_t estimateBinaryLength(int32_t currentEstimate);
virtual uint8_t getBinaryLengthLowerBound();
virtual OMR::X86::EnlargementResult enlarge(int32_t requestedEnlargementSize, int32_t maxEnlargementSize, bool allowPartialEnlargement);
virtual void assignRegisters(TR_RegisterKinds kindsToBeAssigned);
virtual bool refsRegister(TR::Register *reg);
virtual bool defsRegister(TR::Register *reg);
virtual bool usesRegister(TR::Register *reg);
#ifdef DEBUG
virtual uint32_t getNumOperandReferencedGPRegisters() { return 1; };
#endif
};
class X86RegRegInstruction : public TR::X86RegInstruction
{
TR::Register *_sourceRegister;
public:
X86RegRegInstruction(TR::Register *sreg,
TR::Register *treg,
TR::Node *node,
TR_X86OpCodes op,
TR::CodeGenerator *cg)
: TR::X86RegInstruction(treg, node, op, cg), _sourceRegister(sreg)
{
useRegister(sreg);
}
X86RegRegInstruction(TR::Register *sreg,
TR::Register *treg,
TR_X86OpCodes op,
TR::Instruction *precedingInstruction,
TR::CodeGenerator *cg)
: TR::X86RegInstruction(treg, op, precedingInstruction, cg), _sourceRegister(sreg)
{
useRegister(sreg);
}
X86RegRegInstruction(TR::RegisterDependencyConditions *cond,
TR::Register *sreg,
TR::Register *treg,
TR::Node *node,
TR_X86OpCodes op,
TR::CodeGenerator *cg)
: TR::X86RegInstruction(cond, treg, node, op, cg), _sourceRegister(sreg)
{
useRegister(sreg);
}
X86RegRegInstruction(TR::RegisterDependencyConditions *cond,
TR::Register *sreg,
TR::Register *treg,
TR_X86OpCodes op,
TR::Instruction *precedingInstruction,
TR::CodeGenerator *cg)
: TR::X86RegInstruction(cond, treg, op, precedingInstruction, cg), _sourceRegister(sreg)
{
useRegister(sreg);
}
X86RegRegInstruction(TR_X86OpCodes op,
TR::Node *node,
TR::Register *treg,
TR::Register *sreg,
TR::CodeGenerator *cg);
X86RegRegInstruction(TR::Instruction *precedingInstruction,
TR_X86OpCodes op,
TR::Register *treg,
TR::Register *sreg,
TR::CodeGenerator *cg);
X86RegRegInstruction(TR_X86OpCodes op,
TR::Node *node,
TR::Register *treg,
TR::Register *sreg,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg);
X86RegRegInstruction(TR::Instruction *precedingInstruction,
TR_X86OpCodes op,
TR::Register *treg,
TR::Register *sreg,
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg);
virtual char *description() { return "X86RegReg"; }
virtual Kind getKind() { return IsRegReg; }
virtual TR::X86RegRegInstruction *getIA32RegRegInstruction() {return this;}
virtual TR::Register *getSourceRegister() {return _sourceRegister;}
TR::Register *setSourceRegister(TR::Register *sr) {return (_sourceRegister = sr);}
void applySourceRegisterToModRMByte(uint8_t *modRM)
{
TR::RealRegister *source = toRealRegister(_sourceRegister);
if (getOpCode().hasSourceRegisterInModRM())
{
source->setRMRegisterFieldInModRM(modRM);
}
else
{
// If not in RM field, then must be register field in ModRM byte
//
source->setRegisterFieldInModRM(modRM);
}
}
#if defined(TR_TARGET_64BIT)
virtual uint8_t rexBits()
{
return operandSizeRexBits() | targetRegisterRexBits() | sourceRegisterRexBits();
}
uint8_t sourceRegisterRexBits()
{
// Determine where the 4th register bit (if any) should go
//
uint8_t rxbBitmask;
if (getOpCode().hasSourceRegisterInModRM())