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OMRInstruction.cpp
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OMRInstruction.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
//On zOS XLC linker can't handle files with same name at link time
//This workaround with pragma is needed. What this does is essentially
//give a different name to the codesection (csect) for this file. So it
//doesn't conflict with another file with same name.
#pragma csect(CODE,"OMRZInstBase#C")
#pragma csect(STATIC,"OMRZInstBase#S")
#pragma csect(TEST,"OMRZInstBase#T")
#include "codegen/Instruction.hpp"
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "codegen/CodeGenPhase.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterPair.hpp"
#include "compile/Compilation.hpp"
#include "compile/Method.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "cs2/arrayof.h"
#include "cs2/hashtab.h"
#include "env/CompilerEnv.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/StaticSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/deque.hpp"
#include "ras/Debug.hpp"
#include "z/codegen/S390Instruction.hpp"
#include "z/codegen/S390OutOfLineCodeSection.hpp"
#include "env/TRMemory.hpp"
#define CTOR_INITIALIZER_LIST _conditions(NULL), _operands(NULL), _useRegs(NULL), _defRegs(NULL), \
_sourceUsedInMemoryReference(NULL), _flags(0), _longDispSpillReg1(NULL), _longDispSpillReg2(NULL), _binFreeRegs(0), \
_targetRegSize(0), _sourceRegSize(0), _sourceMemSize(0), _targetMemSize(0), _sourceStart(-1), _targetStart(-1)
OMR::Z::Instruction::Instruction(TR::CodeGenerator* cg, TR::InstOpCode::Mnemonic op, TR::Node* node)
:
OMR::Instruction(cg, op, node),
CTOR_INITIALIZER_LIST
{
TR_ASSERT_FATAL(cg->comp()->target().cpu.isAtLeast(_opcode.getMinimumALS()), "Processor detected (%s) does not support instruction %s\n", cg->comp()->target().cpu.getProcessorName(), _opcode.getMnemonicName());
self()->initialize();
}
OMR::Z::Instruction::Instruction(TR::CodeGenerator*cg, TR::Instruction* precedingInstruction, TR::InstOpCode::Mnemonic op, TR::Node* node)
:
OMR::Instruction(cg, precedingInstruction, op, node),
CTOR_INITIALIZER_LIST
{
TR_ASSERT_FATAL(cg->comp()->target().cpu.isAtLeast(_opcode.getMinimumALS()), "Processor detected (%s) does not support instruction %s\n", cg->comp()->target().cpu.getProcessorName(), _opcode.getMnemonicName());
self()->initialize(precedingInstruction, true);
}
TR::RegisterDependencyConditions *
OMR::Z::Instruction::setDependencyConditionsNoBookKeeping(TR::RegisterDependencyConditions *cond)
{
// If register dependency conditions exist, merge with the argument conditions
if( _conditions )
{
TR::RegisterDependencyConditions * n = new (self()->cg()->trHeapMemory()) TR::RegisterDependencyConditions( _conditions, cond, self()->cg() );
_conditions = 0;
cond = n;
}
return _conditions = cond;
}
TR::RegisterDependencyConditions *
OMR::Z::Instruction::setDependencyConditions(TR::RegisterDependencyConditions *cond)
{
TR_ASSERT(cond, "NULL S390 register dependency conditions");
int32_t oldPreAddCursor = 0;
int32_t oldPostAddCursor = 0;
// If register dependency conditions exist, merge with the argument conditions
if (_conditions)
{
oldPreAddCursor = _conditions->getAddCursorForPre();
oldPostAddCursor = _conditions->getAddCursorForPost();
TR::RegisterDependencyConditions * n = new (self()->cg()->trHeapMemory()) TR::RegisterDependencyConditions( _conditions, cond, self()->cg() );
_conditions = 0;
cond = n;
}
// Perform book keeping only on argument conditions
cond->bookKeepingRegisterUses(self(), self()->cg(), oldPreAddCursor, oldPostAddCursor);
cond->setIsUsed();
if(cond->getPreConditions()) cond->getPreConditions()->incNumUses();
if(cond->getPostConditions()) cond->getPostConditions()->incNumUses();
return _conditions = cond;
}
TR::RegisterDependencyConditions *
OMR::Z::Instruction::updateDependencyConditions(TR::RegisterDependencyConditions *cond)
{
int32_t currentPreCursor = 0;
int32_t currentPostCursor = 0;
if (_conditions)
{
currentPreCursor = _conditions->getAddCursorForPre();
currentPostCursor = _conditions->getAddCursorForPost();
}
cond->bookKeepingRegisterUses(self(), self()->cg(), currentPreCursor, currentPostCursor);
cond->setIsUsed();
return _conditions = cond;
}
void
OMR::Z::Instruction::initialize(TR::Instruction * precedingInstruction, bool instFlag, TR::RegisterDependencyConditions * cond, bool condFlag)
{
//call other initializer first
self()->initialize(cond);
TR::CodeGenerator * cg = OMR::Instruction::cg();
if (cond)
{
// Don't want to increment total use counts for ASSOCREGS instructions
// because their register references will confuse the code that tries
// to determine when the first use of a register takes place
if (condFlag || self()->getOpCodeValue() != TR::InstOpCode::ASSOCREGS)
{
cond->bookKeepingRegisterUses(self(), cg);
if(cond->getPreConditions()) cond->getPreConditions()->incNumUses();
if(cond->getPostConditions()) cond->getPostConditions()->incNumUses();
}
cond->setIsUsed();
}
if (cg->getCondCodeShouldBePreserved())
TR_ASSERT( (_opcode.setsOverflowFlag() || _opcode.setsZeroFlag() || _opcode.setsSignFlag() || _opcode.setsCarryFlag()) == false,
"We thought the instruction [0x%p] won't modify the CC, but it does.\n", self());
self()->readCCInfo(); // Must come before setCCInfo - Instruction reads CC before setting CC.
if (cg->comp()->getOption(TR_EnableEBBCCInfo))
{
((self()->isLabel() || self()->isCall()) || (instFlag && precedingInstruction == NULL)) ? self()->clearCCInfo() : self()->setCCInfo();
}
else
{
(!self()->isBranchOp() && (!instFlag || precedingInstruction == NULL)) ? self()->setCCInfo() : self()->clearCCInfo();
}
}
// Realistic offset estimate for the instruction.
// Applicable to frontends which does not do binary encoding (i.e., not Java or OMR).
// Therefore, we will reuse the field for the binary buffer pointer to store the binary
// offset. This way we dont use an extra 4 byte field in TR::Instruction
uint32_t
OMR::Z::Instruction::getEstimatedBinaryOffset()
{
union { uint8_t *p; uint32_t i; } _u;
_u.p = self()->getBinaryEncoding();
return _u.i;
}
void
OMR::Z::Instruction::setEstimatedBinaryOffset(uint32_t l)
{
union { uint8_t *p; uint32_t i; } _u;
_u.i = l;
self()->setBinaryEncoding(_u.p) ;
}
void
OMR::Z::Instruction::setCCInfo()
{
if (self()->getNode() == NULL)
{
// play it safe... perhaps this should be changed to an assert that the node should never be NULL?
self()->clearCCInfo();
return;
}
if (_opcode.setsCC())
{
if (self()->cg()->ccInstruction() != NULL)
{
// Check previous CC setting instruction... we can mark its usage as
// known, since the current instruction will override its CC value.
self()->cg()->ccInstruction()->setCCuseKnown();
}
if (!self()->cg()->comp()->getOption(TR_EnableEBBCCInfo))
{
if (_opcode.setsOverflowFlag() || _opcode.setsZeroFlag() || _opcode.setsSignFlag() || _opcode.setsCarryFlag())
{
// we have detailed information on the CC setting
self()->cg()->setHasCCInfo(true);
self()->cg()->setHasCCOverflow(_opcode.setsOverflowFlag() && !self()->getNode()->cannotOverflow());
self()->cg()->setHasCCZero(_opcode.setsZeroFlag());
self()->cg()->setHasCCSigned(_opcode.setsSignFlag() || _opcode.setsCompareFlag());
self()->cg()->setCCInstruction(self());
self()->cg()->setHasCCCarry(_opcode.setsCarryFlag());
}
else
{
// the CC setting is generic or
// there is no node associated with this instruction,
// play it safe and record no information
self()->cg()->setHasCCInfo(false);
}
self()->cg()->setCCInstruction(self());
}
else
{
if (_opcode.setsOverflowFlag() || _opcode.setsZeroFlag() || _opcode.setsSignFlag() || _opcode.setsCompareFlag() || _opcode.setsCarryFlag())
// track Ops that setsCompareFlag for compare ops as well, so that we may remove redudent compare ops;
// note this will not intruduce mismatching for compare immediate ops with CC from compare Ops,
// because compare immed ops looks for setsSignedFlag or setsZeroFlags - compare ops does not sets these flags
{
// we have detailed information on the CC setting
self()->cg()->setHasCCInfo(true);
self()->cg()->setHasCCOverflow(_opcode.setsOverflowFlag() && !self()->getNode()->cannotOverflow());
self()->cg()->setHasCCZero(_opcode.setsZeroFlag());
self()->cg()->setHasCCSigned(_opcode.setsSignFlag());
self()->cg()->setHasCCCompare(_opcode.setsCompareFlag());
self()->cg()->setHasCCCarry(_opcode.setsCarryFlag());
self()->cg()->setCCInstruction(self());
}
else
{
// the CC setting is generic, such as Load & Test Reg, Test Under Mask etc are not handled; or,
// there is no node associated with this instruction,
// play it safe and record no information
self()->cg()->setHasCCInfo(false);
}
self()->cg()->setCCInstruction(self());
} // if enableEBBCCInfo
}
}
void
OMR::Z::Instruction::readCCInfo()
{
if (_opcode.readsCC())
{
if (self()->cg()->ccInstruction() != NULL)
{
// Current instruction reads CC. Mark the last instruction that
// set the CC value as having its CC being used.
self()->cg()->ccInstruction()->setCCuseKnown();
self()->cg()->ccInstruction()->setCCused();
}
}
}
void
OMR::Z::Instruction::clearCCInfo()
{
self()->cg()->setHasCCInfo(false);
self()->cg()->setCCInstruction(NULL);
}
bool
OMR::Z::Instruction::matchesTargetRegister(TR::Register* reg)
{
if (reg->getRealRegister())
{
if (self()->implicitlySetsGPR0() &&
toRealRegister(reg)->getRegisterNumber() == TR::RealRegister::GPR0)
return true;
if (self()->implicitlySetsGPR1() &&
toRealRegister(reg)->getRegisterNumber() == TR::RealRegister::GPR1)
return true;
if (self()->implicitlySetsGPR2() &&
toRealRegister(reg)->getRegisterNumber() == TR::RealRegister::GPR2)
return true;
}
return false;
}
bool
OMR::Z::Instruction::matchesAnyRegister(TR::Register * reg, TR::Register * instReg)
{
if (!instReg)
return false;
TR::RegisterPair * regPair = instReg->getRegisterPair();
TR::RealRegister * realReg = NULL;
TR::RealRegister * realInstReg1 = NULL;
TR::RealRegister * realInstReg2 = NULL;
if (regPair)
{
// if we are matching virt regs
if ((reg == regPair->getHighOrder()) || reg == regPair->getLowOrder())
{
return true;
}
}
else
{
// if we are matching virt regs
if (reg == instReg)
{
return true;
}
}
return false;
}
bool
OMR::Z::Instruction::matchesAnyRegister(TR::Register * reg, TR::Register * instReg1, TR::Register * instReg2)
{
return self()->matchesAnyRegister(reg, instReg1) || self()->matchesAnyRegister(reg, instReg2);
}
TR::Register *
OMR::Z::Instruction::getRegForBinaryEncoding(TR::Register * reg)
{
return (reg->getRegisterPair()) ? reg->getRegisterPair()->getHighOrder() : reg;
}
void
OMR::Z::Instruction::useRegister(TR::Register * reg, bool isDummy)
{
TR_ASSERT( reg != NULL, "NULL Register encountered");
TR::RegisterPair * regPair = reg->getRegisterPair();
if (regPair)
{
TR::Register * firstRegister = regPair->getHighOrder();
TR::Register * lastRegister = regPair->getLowOrder();
TR_ASSERT( firstRegister != NULL, "NULL First Register encountered");
TR_ASSERT( lastRegister != NULL,"NULL Last Register encountered");
if (firstRegister->getRealRegister()==NULL)
{
TR_ASSERT(firstRegister->getSiblingRegister(),
"[%p] Register Pairs should be allocated using allocateConsecutivePair.\n", self());
}
if (lastRegister->getRealRegister()==NULL)
{
TR_ASSERT(lastRegister->getSiblingRegister(),
"[%p] Register Pairs should be allocated using allocateConsecutivePair.\n", self());
}
OMR::Instruction::useRegister(firstRegister);
OMR::Instruction::useRegister(lastRegister);
}
else
{
OMR::Instruction::useRegister(reg);
// If an instruction uses a dummy register, that register should no longer be considered dummy.
// S390RegisterDependency also calls useRegister, in this case we do not want to reset the dummy status of these regs
//
if (!isDummy && reg->isPlaceholderReg())
{
reg->resetPlaceholderReg();
}
}
return;
}
bool
OMR::Z::Instruction::refsRegister(TR::Register * reg)
{
return self()->getDependencyConditions() ? self()->getDependencyConditions()->refsRegister(reg) : false;
}
bool
OMR::Z::Instruction::defsAnyRegister(TR::Register * reg)
{
TR::Register **_targetReg = self()->targetRegBase();
if (_targetReg)
{
for (int32_t i = 0; i < _targetRegSize; ++i)
{
if (_targetReg[i]->usesAnyRegister(reg))
return true;
}
}
return false;
}
bool
OMR::Z::Instruction::defsRegister(TR::Register * reg)
{
TR::Register **_targetReg = self()->targetRegBase();
if (_targetReg)
{
for (int32_t i = 0; i < _targetRegSize; ++i)
{
if (_targetReg[i]->usesRegister(reg))
return true;
}
}
return false;
}
// this may replace defsRegister
bool
OMR::Z::Instruction::isDefRegister(TR::Register * reg)
{
// Test if this is the implicitly targeted register
if (self()->matchesTargetRegister(reg))
return true;
//Test explicitly targeted register by the instruction
if (_defRegs)
{
for (int32_t i = 0; i < _defRegs->size(); ++i)
{
if ((* _defRegs) [i]->usesRegister(reg))
return true;
}
}
return false;
}
bool OMR::Z::Instruction::usesOnlyRegister(TR::Register *reg)
{
int32_t i;
TR::Register **_sourceReg = self()->sourceRegBase();
TR::MemoryReference **_sourceMem = self()->sourceMemBase();
TR::MemoryReference **_targetMem = self()->targetMemBase();
for (i = 0; i < _sourceRegSize; ++i)
{
if (_sourceReg[i]->usesRegister(reg))
return true;
}
for (i = 0; i < _sourceMemSize; ++i)
{
if (_sourceMem[i]->usesRegister(reg))
return true;
}
for (i = 0; i < _targetMemSize; ++i)
{
if (_targetMem[i]->usesRegister(reg))
return true;
}
// We might have an out of line EX instruction. If so, we
// need to check whether either the EX instruction OR the instruction
// it refers to uses the specified register.
TR::Instruction *outOfLineEXInstr = self()->getOutOfLineEXInstr();
if (outOfLineEXInstr && outOfLineEXInstr->usesOnlyRegister(reg))
return true;
return false;
}
bool
OMR::Z::Instruction::usesRegister(TR::Register * reg)
{
int32_t i;
if(self()->usesOnlyRegister(reg) || self()->defsRegister(reg))
return true;
// The only thing that is not covered by defsRegister is target registers found in EX
// We might have an out of line EX instruction. If so, we
// need to check whether either the EX instruction OR the instruction
// it refers to uses the specified register.
TR::Instruction *outOfLineEXInstr = self()->getOutOfLineEXInstr();
if (outOfLineEXInstr)
{
TR::Register **_targetReg = outOfLineEXInstr->targetRegBase();
if (_targetReg)
{
for (i = 0; i < outOfLineEXInstr->_targetRegSize; ++i)
{
if (_targetReg[i]->usesRegister(reg))
return true;
}
}
}
return false;
}
TR::Instruction *
OMR::Z::Instruction::getOutOfLineEXInstr()
{
if (!self()->isOutOfLineEX())
return NULL;
switch(self()->getOpCodeValue())
{
case TR::InstOpCode::EX:
{
TR::MemoryReference * tempMR = ((TR::S390RXInstruction *)self())->getMemoryReference();
TR::S390ConstantInstructionSnippet * cis = (TR::S390ConstantInstructionSnippet *) tempMR->getConstantDataSnippet();
TR_ASSERT( cis != NULL, "Out of line EX instruction doesn't have a constantInstructionSnippet\n");
return cis->getInstruction();
}
case TR::InstOpCode::EXRL:
{
TR::S390ConstantInstructionSnippet * cis = (TR::S390ConstantInstructionSnippet *)
((TR::S390RILInstruction *)self())->getTargetSnippet();
TR_ASSERT( cis != NULL, "Out of line EXRL instruction doesn't have a constantInstructionSnippet\n");
return cis->getInstruction();
}
default:
return NULL;
}
}
// determine if this instruction will throw an implicit null pointer exception
// and set appropriate flags
void
OMR::Z::Instruction::setupThrowsImplicitNullPointerException(TR::Node *n, TR::MemoryReference *mr)
{
TR::Compilation *comp = self()->cg()->comp();
if(self()->cg()->getSupportsImplicitNullChecks())
{
// this instruction throws an implicit null check if:
// 1. The treetop node is a NULLCHK node
// 2. The memory reference of this instruction can cause a null pointer exception
// 3. The null check reference node must be a child of this node
// 4. This memory reference uses the same register as the null check reference
// 5. This is the first instruction in the evaluation of this null check node to have met all the conditions
// Test conditions 1, 2, and 5
if(n != NULL & mr != NULL &&
mr->getCausesImplicitNullPointerException() &&
self()->cg()->getCurrentEvaluationTreeTop()->getNode()->getOpCode().isNullCheck() &&
self()->cg()->getImplicitExceptionPoint() == NULL)
{
// determine what the NULLcheck reference node is
TR::Node * nullCheckReference;
TR::Node * firstChild = self()->cg()->getCurrentEvaluationTreeTop()->getNode()->getFirstChild();
if (comp->useCompressedPointers() &&
firstChild->getOpCodeValue() == TR::l2a)
{
TR::ILOpCodes loadOp = comp->il.opCodeForIndirectLoad(TR::Int32);
TR::ILOpCodes rdbarOp = comp->il.opCodeForIndirectReadBarrier(TR::Int32);
while (firstChild->getOpCodeValue() != loadOp && firstChild->getOpCodeValue() != rdbarOp)
firstChild = firstChild->getFirstChild();
nullCheckReference = firstChild->getFirstChild();
}
else
nullCheckReference = self()->cg()->getCurrentEvaluationTreeTop()->getNode()->getNullCheckReference();
// Test conditions 3 and 4
if ((self()->getNode()->getOpCode().hasSymbolReference() &&
self()->getNode()->getSymbolReference() == comp->getSymRefTab()->findVftSymbolRef()) ||
(n->hasChild(nullCheckReference) && mr->usesRegister(nullCheckReference->getRegister())))
{
traceMsg(comp,"Instruction %p throws an implicit NPE, node: %p NPE node: %p\n", self(), n, nullCheckReference);
self()->cg()->setImplicitExceptionPoint(self());
}
}
}
}
// The following safe virtual downcast method is only used in an assertion
// check within "toS390ImmInstruction"
#if defined(DEBUG) || defined(PROD_WITH_ASSUMES)
TR::S390ImmInstruction *
OMR::Z::Instruction::getS390ImmInstruction()
{
return NULL;
}
#endif
uint8_t *
OMR::Z::Instruction::generateBinaryEncoding()
{
uint8_t * instructionStart = self()->cg()->getBinaryBufferCursor();
uint8_t * cursor = instructionStart;
memset( (void*)cursor,0,self()->getEstimatedBinaryLength());
self()->getOpCode().copyBinaryToBuffer(instructionStart);
self()->setBinaryLength(self()->getOpCode().getInstructionLength());
self()->setBinaryEncoding(instructionStart);
self()->cg()->addAccumulatedInstructionLengthError(self()->getEstimatedBinaryLength() - self()->getBinaryLength());
return cursor;
}
int32_t
OMR::Z::Instruction::estimateBinaryLength(int32_t currentEstimate)
{
self()->setEstimatedBinaryLength(self()->getOpCode().getInstructionLength());
return currentEstimate + self()->getEstimatedBinaryLength();
}
bool
OMR::Z::Instruction::dependencyRefsRegister(TR::Register * reg)
{
return false;
}
bool isMatchingStoreRestore(TR::Instruction *cursorLoad, TR::Instruction *cursorStore, TR::CodeGenerator *cg)
{
return false;
}
uint32_t getRegMaskFromRange(TR::Instruction * inst)
{
uint32_t regs = 0;
TR::Register *lowReg = toS390RSInstruction(inst)->getFirstRegister();
TR::Register *highReg = toS390RSInstruction(inst)->getSecondRegister();
if (inst->getRegisterOperand(1)->getRegisterPair())
highReg = inst->getRegisterOperand(1)->getRegisterPair()->getHighOrder();
uint32_t lowRegNum = ANYREGINDEX(toRealRegister(lowReg)->getRegisterNumber());
uint32_t highRegNum = ANYREGINDEX(toRealRegister(highReg)->getRegisterNumber());
TR_ASSERT(lowRegNum >= 0 && lowRegNum <= 15 && highRegNum >= 0 && highRegNum <= 15, "Unexpected register number");
for (uint32_t i = lowRegNum; ; i = ((i == 15) ? 0 : i+1)) // wrap around to 0 at 15
{
regs = regs | (0x1 << i);
if (i == highRegNum)
break;
}
return regs;
}
static void handleLoadWithRegRanges(TR::Instruction *inst, TR::CodeGenerator *cg)
{
TR::Compilation * comp = cg->comp();
TR::InstOpCode::Mnemonic opCodeToUse = inst->getOpCodeValue();
if (!(opCodeToUse == TR::InstOpCode::LM || opCodeToUse == TR::InstOpCode::LMG || opCodeToUse == TR::InstOpCode::LMH ||
opCodeToUse == TR::InstOpCode::LMY || opCodeToUse == TR::InstOpCode::VLM))
return;
bool isVector = opCodeToUse == TR::InstOpCode::VLM ? true : false;
uint32_t numVRFs = TR::RealRegister::LastAssignableVRF - TR::RealRegister::FirstAssignableVRF;
TR::Register *lowReg = isVector ? toS390VRSInstruction(inst)->getFirstRegister() : toS390RSInstruction(inst)->getFirstRegister();
TR::Register *highReg = isVector ? toS390VRSInstruction(inst)->getSecondRegister() : toS390RSInstruction(inst)->getSecondRegister();
if (inst->getRegisterOperand(1)->getRegisterPair())
highReg = inst->getRegisterOperand(1)->getRegisterPair()->getHighOrder();
uint32_t lowRegNum = ANYREGINDEX(toRealRegister(lowReg)->getRegisterNumber());
uint32_t highRegNum = ANYREGINDEX(toRealRegister(highReg)->getRegisterNumber());
uint32_t regsInRange;
if (highRegNum >= lowRegNum)
regsInRange = (highRegNum - lowRegNum + 1);
else
regsInRange = ((isVector ? numVRFs : 16) - lowRegNum) + highRegNum + 1;
if (regsInRange <= 2)
return; // registers on instruction, nothing more to do.
// visit all registers in range. ignore first and last since RA will have taken care of already
lowRegNum = lowRegNum == (isVector ? numVRFs - 1 : 15) ? 0 : lowRegNum + 1;
// wrap around for loop terminal index to 0 at 15 or 31 for Vector Registers
uint32_t availForShuffle = cg->machine()->genBitMapOfAssignableGPRs() & ~(getRegMaskFromRange(inst));
for (uint32_t i = lowRegNum ;
i != highRegNum ;
i = ((i == (isVector ? numVRFs - 1 : 15)) ? 0 : i+1))
{
TR::RealRegister *reg = cg->machine()->getRealRegister(i + TR::RealRegister::GPR0);
// Registers that are assigned need to be checked whether they have a matching STM--otherwise we spill.
// Since we are called post RA for the LM, we check if assigned registers are last used on the LM so we can
// avoid needlessly spilling them. (ex. LM(GPR00F,GPR14P,PSALCCAV->LCCAEMS0); ! PSALCCAV needs a reg and only needed on LM)
TR::Register *virtualReg = reg->getAssignedRegister();
if (reg->getState() == TR::RealRegister::Assigned && inst != virtualReg->getEndOfRange())
{
TR::Instruction *cursor = inst->getPrev();
bool found = false;
while (cursor)
{
if (cursor->getOpCodeValue() == TR::InstOpCode::FENCE && cursor->getNode()->getOpCodeValue() == TR::BBStart)
{
TR::Block *block = cursor->getNode()->getBlock();
if (!block->isExtensionOfPreviousBlock())
break;
}
if (cursor->defsRegister(virtualReg))
break;
if (isMatchingStoreRestore(inst, cursor, cg))
{
cg->traceRegisterAssignment("Skip spilling %R--restored on load", virtualReg);
found = true;
break; // found matching store--do nothing since load will restore value
}
cursor = cursor->getPrev();
}
// register is defined before it was stored, spill or shuffle it to a free reg before load clobbers it
// start of range will be NULL in some cases, we are cautious and spill (def# 100246)
if (!found)
{
cg->traceRegisterAssignment("trying to free %R for killed reg %R by loadmultiple \n", virtualReg, reg);
TR::RealRegister *shuffle = cg->machine()->shuffleOrSpillRegister(inst, virtualReg, availForShuffle);
if (shuffle != NULL)
{
//if the LM instruction uses this reg we just shuffled, it will have the wrong real reg, need to fix this up
if (inst->usesRegister(reg))
{
inst->renameRegister(reg, shuffle);
}
}
}
}
}
}
void
OMR::Z::Instruction::assignRegisters(TR_RegisterKinds kindToBeAssigned)
{
TR::Compilation *comp = self()->cg()->comp();
if (self()->getOpCodeValue() != TR::InstOpCode::ASSOCREGS)
{
self()->assignRegistersAndDependencies(kindToBeAssigned);
}
else if (self()->cg()->enableRegisterAssociations())
{
//if (kindToBeAssigned == TR_GPR)
{
TR::Machine * machine = self()->cg()->machine();
int32_t first = TR::RealRegister::FirstGPR;
int32_t last = TR::RealRegister::LastAssignableVRF;
// Step 1 : First traverse the existing associations and remove them so that they don't interfere with the new ones
for (int32_t i = first; i <= last; ++i)
{
TR::Register * virtReg = machine->getVirtualAssociatedWithReal((TR::RealRegister::RegNum) (i));
if (virtReg)
{
virtReg->setAssociation(TR::RealRegister::NoReg);
}
}
// Step 2 : loop through and set up the new associations (both on the machine and by associating the virtual
// registers with their real dependencies)
TR::RegisterDependencyGroup * depGroup = self()->getDependencyConditions()->getPostConditions();
for (int32_t j = 0; j < last; ++j)
{
TR::Register * virtReg = depGroup->getRegisterDependency(j)->getRegister();
machine->setVirtualAssociatedWithReal((TR::RealRegister::RegNum) (j + 1), virtReg);
}
machine->setRegisterWeightsFromAssociations();
}
}
// If we are register assigning an EX or EXRL instruction with the isOutOfLineEX flag set
// we must register assign the instruction object hanging off of the memory reference's constantInstructionSnippet
TR::Instruction *outOfLineEXInstr = self()->getOutOfLineEXInstr();
if (outOfLineEXInstr)
{
TR::Instruction *savePrev = outOfLineEXInstr->getPrev();
outOfLineEXInstr->setPrev(self()->getPrev()); // Temporarily set Prev() instruction of snippet to Prev() of EX just in case we insert LR_move on assignRegisters()
self()->cg()->tracePreRAInstruction(outOfLineEXInstr);
outOfLineEXInstr->assignRegisters(kindToBeAssigned);
TR::RegisterDependencyConditions *deps = outOfLineEXInstr->getDependencyConditions();
if (deps) // merge the dependency into the EX deps
{
outOfLineEXInstr->resetDependencyConditions();
TR::RegisterDependencyConditions * exDeps = (self())->getDependencyConditions();
TR::RegisterDependencyConditions * newDeps = new (self()->cg()->trHeapMemory()) TR::RegisterDependencyConditions(deps, exDeps, self()->cg());
(self())->setDependencyConditionsNoBookKeeping(newDeps);
}
outOfLineEXInstr->setPrev(savePrev); // Restore Prev() of snippet
self()->cg()->tracePostRAInstruction(outOfLineEXInstr);
//Java and other languages probably need the value field to be set to the binary encoding of the instruction
//This can be done any time after register assignment
//If the value is set here, the snippet can be handled in an identical fashion to a normal constantdataSnippet
}
handleLoadWithRegRanges(self(), self()->cg());
}
uint32_t
OMR::Z::Instruction::useSourceRegister(TR::Register * reg)
{
TR::Compilation *comp = self()->cg()->comp();
if(_sourceStart < 0)
{
if(_targetStart < 0)
_sourceStart = 0;
else
_sourceStart = _targetRegSize;
}
self()->recordOperand((void*) reg, _sourceRegSize);
self()->useRegister(reg);
if (reg->getKind() == TR_GPR && _opcode.is64bit())
{
reg->setIs64BitReg(true);
if (reg->getRegisterPair())
{
reg->getLowOrder()->setIs64BitReg(true);
reg->getHighOrder()->setIs64BitReg(true);
}
}
return _sourceRegSize-1; // index into the source register array
}
const char *
OMR::Z::Instruction::getName(TR_Debug * debug)
{
if (debug)
return debug->getName(self());
else
return "<unknown instruction>";
}
void
OMR::Z::Instruction::recordOperand(void *operand, int8_t &operandCount)
{
TR::Compilation *comp = self()->cg()->comp();
uint32_t n = self()->numOperands();
void **p = (void **) comp->allocator().allocate(sizeof(void *) * (n+1));
if(_operands==NULL)
{
((uintptr_t** )p)[0]=(uintptr_t *)operand;
_operands=p;
}
else
{
for (int i=0; i < n; i++) ((uintptr_t**)p)[i] = ((uintptr_t **) _operands)[i];
((uintptr_t** )p)[n]= (uintptr_t *) operand;
comp->allocator().deallocate(_operands, sizeof(void *) * n);
_operands = p;
}
operandCount++;
}
/*
* Tests if instruction contains given register. More comprehensive containment search
* than matchAnyRegister.
*/
bool OMR::Z::Instruction::containsRegister(TR::Register *reg)
{
TR::Register **_sourceReg = self()->sourceRegBase();
TR::Register **_targetReg = self()->targetRegBase();
TR::MemoryReference **_sourceMem = self()->sourceMemBase();
TR::MemoryReference **_targetMem = self()->targetMemBase();
int i;
for (i = 0; i < _sourceRegSize; i++)
if (_sourceReg[i]->usesAnyRegister(reg))
return true;
for (i = 0; i < _targetRegSize; i++)
if (_targetReg[i]->usesAnyRegister(reg))
return true;
for (i = 0; i < _sourceMemSize; i++)
if (_sourceMem[i]->usesRegister(reg))
return true;
for (i = 0; i < _targetMemSize; i++)
if (_targetMem[i]->usesRegister(reg))
return true;
if (self()->isOutOfLineEX())
{
if (self()->getOpCodeValue() == TR::InstOpCode::EX)
{
TR::MemoryReference * tempMR = ((TR::S390RXInstruction *)self())->getMemoryReference();
TR::S390ConstantInstructionSnippet * cis = (TR::S390ConstantInstructionSnippet *) tempMR->getConstantDataSnippet();
TR_ASSERT( cis != NULL, "Out of line EX instruction doesn't have a constantInstructionSnippet\n");
if (cis->getInstruction()->containsRegister(reg))
return true;
}
else if (self()->getOpCodeValue() == TR::InstOpCode::EXRL)
{
TR::S390ConstantInstructionSnippet * cis = (TR::S390ConstantInstructionSnippet *) ((TR::S390RILInstruction *)self())->getTargetSnippet();
TR_ASSERT( cis != NULL, "Out of line EXRL instruction doesn't have a constantInstructionSnippet\n");
if (cis->getInstruction()->containsRegister(reg))
return true;
}
}
return false;
}
uint32_t
OMR::Z::Instruction::useTargetRegister(TR::Register* reg)
{
TR::Compilation *comp = self()->cg()->comp();
if(_targetStart < 0)
{
if(_sourceStart < 0)
_targetStart = 0;
else
_targetStart = _sourceRegSize;
}
self()->recordOperand((void*) reg, _targetRegSize);
// Invalidate CC if target kills any of the usesOnlyRegisters of ccInst
TR::Instruction* ccInst = self()->cg()->ccInstruction();
if (self()->cg()->hasCCInfo() &&
(self() != ccInst) &&
ccInst->containsRegister(reg))
{
ccInst->setCCuseKnown();
self()->clearCCInfo();
}
self()->useRegister(reg);
if (reg->getKind() == TR_GPR && (_opcode.is64bit() || _opcode.is32to64bit() ||
(comp->target().is64Bit() &&
(self()->getOpCodeValue() == TR::InstOpCode::LA ||
self()->getOpCodeValue() == TR::InstOpCode::LAY ||
self()->getOpCodeValue() == TR::InstOpCode::LARL ||
self()->getOpCodeValue() == TR::InstOpCode::BASR ||
self()->getOpCodeValue() == TR::InstOpCode::BRASL))))
{
reg->setIs64BitReg(true);
if (reg->getRegisterPair())
{
reg->getLowOrder()->setIs64BitReg(true);
reg->getHighOrder()->setIs64BitReg(true);
}
}
return _targetRegSize-1; // index into the target register array
}
// check if a particular instruction has a long displacment version
bool
OMR::Z::Instruction::hasLongDisplacementSupport()
{
// Includes all instructions with long displacement support - RXE, RX, RXY, RS, RSY, SI, SIY
return self()->getOpCode().hasLongDispSupport();