-
Notifications
You must be signed in to change notification settings - Fork 392
/
OMRRegisterDependency.cpp
1664 lines (1458 loc) · 61.9 KB
/
OMRRegisterDependency.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*******************************************************************************
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
//On zOS XLC linker can't handle files with same name at link time
//This workaround with pragma is needed. What this does is essentially
//give a different name to the codesection (csect) for this file. So it
//doesn't conflict with another file with same name.
#pragma csect(CODE,"OMRZRegisterDependency#C")
#pragma csect(STATIC,"OMRZRegisterDependency#S")
#pragma csect(TEST,"OMRZRegisterDependency#T")
#include <stddef.h>
#include <stdint.h>
#include "codegen/BackingStore.hpp"
#include "codegen/CodeGenerator.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/RegisterPair.hpp"
#include "compile/Compilation.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/ObjectModel.hpp"
#include "env/TRMemory.hpp"
#include "il/AutomaticSymbol.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "infra/Assert.hpp"
#include "infra/List.hpp"
#include "ras/Debug.hpp"
#include "z/codegen/S390GenerateInstructions.hpp"
#include "z/codegen/S390Instruction.hpp"
#include "env/IO.hpp"
OMR::Z::RegisterDependencyConditions::RegisterDependencyConditions(TR::CodeGenerator * cg, TR::Node * node,
uint32_t extranum, TR::Instruction ** cursorPtr)
{
TR::Compilation *comp = cg->comp();
_cg = cg;
List<TR::Register> regList(cg->trMemory());
TR::Instruction * iCursor = (cursorPtr == NULL) ? NULL : *cursorPtr;
int32_t totalNum = node->getNumChildren() + extranum;
int32_t i;
comp->incVisitCount();
int32_t numLongs = 0;
int32_t numLongDoubles = 0;
//
// Pre-compute how many longs are global register candidates
//
for (i = 0; i < node->getNumChildren(); ++i)
{
TR::Node * child = node->getChild(i);
TR::Register * reg = child->getRegister();
if (reg->getKind() == TR_GPR)
{
if (child->getHighGlobalRegisterNumber() > -1)
{
numLongs++;
}
}
}
totalNum = totalNum + numLongs + numLongDoubles;
_preConditions = new (totalNum, cg->trMemory()) TR::RegisterDependencyGroup;
_postConditions = new (totalNum, cg->trMemory()) TR::RegisterDependencyGroup;
_numPreConditions = totalNum;
_addCursorForPre = 0;
_numPostConditions = totalNum;
_addCursorForPost = 0;
_isUsed = false;
for (i = 0; i < totalNum; i++)
{
_preConditions->clearDependencyInfo(i);
_postConditions->clearDependencyInfo(i);
}
for (i = 0; i < node->getNumChildren(); i++)
{
TR::Node * child = node->getChild(i);
TR::Register * reg = child->getRegister();
TR::Register * highReg = NULL;
TR::Register * copyReg = NULL;
TR::Register * highCopyReg = NULL;
TR::RealRegister::RegNum regNum = (TR::RealRegister::RegNum)
cg->getGlobalRegister(child->getGlobalRegisterNumber());
TR::RealRegister::RegNum highRegNum;
if (child->getHighGlobalRegisterNumber() > -1)
{
highRegNum = (TR::RealRegister::RegNum) cg->getGlobalRegister(child->getHighGlobalRegisterNumber());
}
TR::RegisterPair * regPair = reg->getRegisterPair();
resolveSplitDependencies(cg, node, child, regPair, regList, reg, highReg, copyReg, highCopyReg, iCursor, regNum);
reg->setAssociation(regNum);
cg->setRealRegisterAssociation(reg, regNum);
addPreCondition(reg, regNum);
addPostCondition(reg, regNum);
if (copyReg != NULL)
{
cg->stopUsingRegister(copyReg);
}
if (highReg)
{
highReg->setAssociation(highRegNum);
cg->setRealRegisterAssociation(highReg, highRegNum);
addPreCondition(highReg, highRegNum);
addPostCondition(highReg, highRegNum);
if (highCopyReg != NULL)
{
cg->stopUsingRegister(highCopyReg);
}
}
}
if (iCursor != NULL && cursorPtr != NULL)
{
*cursorPtr = iCursor;
}
}
OMR::Z::RegisterDependencyConditions::RegisterDependencyConditions(TR::RegisterDependencyConditions* iConds, uint16_t numNewPreConds, uint16_t numNewPostConds, TR::CodeGenerator * cg)
: _preConditions(new ((iConds ? iConds->getNumPreConditions() : 0) + numNewPreConds, cg->trMemory()) TR::RegisterDependencyGroup),
_postConditions(new ((iConds ? iConds->getNumPostConditions() : 0) + numNewPostConds, cg->trMemory()) TR::RegisterDependencyGroup),
_numPreConditions((iConds?iConds->getNumPreConditions():0)+numNewPreConds),
_addCursorForPre(0),
_numPostConditions((iConds?iConds->getNumPostConditions():0)+numNewPostConds),
_addCursorForPost(0),
_isUsed(false),
_cg(cg)
{
int32_t i;
TR::RegisterDependencyGroup* depGroup;
uint16_t numPreConds = (iConds?iConds->getNumPreConditions():0)+numNewPreConds;
uint16_t numPostConds = (iConds?iConds->getNumPostConditions():0)+numNewPostConds;
uint32_t flag;
TR::RealRegister::RegNum rr;
TR::Register* vr;
for(i=0;i<numPreConds;i++)
{
_preConditions->clearDependencyInfo(i);
}
for(int32_t j=0;j<numPostConds;j++)
{
_postConditions->clearDependencyInfo(j);
}
if (iConds != NULL)
{
depGroup = iConds->getPreConditions();
// depGroup->printDeps(stdout, iConds->getNumPreConditions());
for(i=0;i<iConds->getAddCursorForPre();i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
flag = dep->getFlags();
vr = dep->getRegister();
rr = dep->getRealRegister();
_preConditions->setDependencyInfo(_addCursorForPre++, vr, rr, flag);
}
depGroup = iConds->getPostConditions();
// depGroup->printDeps(stdout, iConds->getNumPostConditions());
for(i=0;i<iConds->getAddCursorForPost();i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
flag = dep->getFlags();
vr = dep->getRegister();
rr = dep->getRealRegister();
_postConditions->setDependencyInfo(_addCursorForPost++, vr, rr, flag);
}
}
}
OMR::Z::RegisterDependencyConditions::RegisterDependencyConditions(TR::RegisterDependencyConditions * conds_1,
TR::RegisterDependencyConditions * conds_2,
TR::CodeGenerator * cg)
: _preConditions(new (conds_1->getNumPreConditions() + conds_2->getNumPreConditions(), cg->trMemory()) TR::RegisterDependencyGroup),
_postConditions(new (conds_1->getNumPostConditions()+conds_2->getNumPostConditions(), cg->trMemory()) TR::RegisterDependencyGroup),
_numPreConditions(conds_1->getNumPreConditions()+conds_2->getNumPreConditions()),
_addCursorForPre(0),
_numPostConditions(conds_1->getNumPostConditions()+conds_2->getNumPostConditions()),
_addCursorForPost(0),
_isUsed(false),
_cg(cg)
{
int32_t i;
TR::RegisterDependencyGroup* depGroup;
uint32_t flag;
TR::RealRegister::RegNum rr;
TR::Register* vr;
for( i = 0; i < _numPreConditions; i++)
{
_preConditions->clearDependencyInfo(i);
}
for( i = 0; i < _numPostConditions; i++)
{
_postConditions->clearDependencyInfo(i);
}
// Merge pre conditions
depGroup = conds_1->getPreConditions();
for( i = 0; i < conds_1->getAddCursorForPre(); i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
if( doesPreConditionExist( dep ) )
{
_numPreConditions--;
}
else if( !addPreConditionIfNotAlreadyInserted( dep ) )
{
_numPreConditions--;
}
}
depGroup = conds_2->getPreConditions();
for( i = 0; i < conds_2->getAddCursorForPre(); i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
if( doesPreConditionExist( dep ) )
{
_numPreConditions--;
}
else if( !addPreConditionIfNotAlreadyInserted( dep ) )
{
_numPreConditions--;
}
}
// Merge post conditions
depGroup = conds_1->getPostConditions();
for( i = 0; i < conds_1->getAddCursorForPost(); i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
if( doesPostConditionExist( dep ) )
{
_numPostConditions--;
}
else if( !addPostConditionIfNotAlreadyInserted( dep ) )
{
_numPostConditions--;
}
}
depGroup = conds_2->getPostConditions();
for( i = 0; i < conds_2->getAddCursorForPost(); i++)
{
TR::RegisterDependency* dep = depGroup->getRegisterDependency(i);
if( doesPostConditionExist( dep ) )
{
_numPostConditions--;
}
else if( !addPostConditionIfNotAlreadyInserted( dep ) )
{
_numPostConditions--;
}
}
}
OMR::Z::RegisterDependencyConditions::RegisterDependencyConditions(uint16_t numPreConds, uint16_t numPostConds, TR::CodeGenerator *cg)
: _preConditions(new (numPreConds, cg->trMemory()) TR::RegisterDependencyGroup),
_postConditions(new (numPostConds + NUM_VM_THREAD_REG_DEPS, cg->trMemory()) TR::RegisterDependencyGroup),
_numPreConditions(numPreConds),
_addCursorForPre(0),
_numPostConditions(numPostConds + NUM_VM_THREAD_REG_DEPS),
_addCursorForPost(0),
_isUsed(false),
_cg(cg)
{
for(int32_t i=0;i<numPreConds;i++)
{
_preConditions->clearDependencyInfo(i);
}
for(int32_t j=0;j<numPostConds + NUM_VM_THREAD_REG_DEPS;j++)
{
_postConditions->clearDependencyInfo(j);
}
}
void OMR::Z::RegisterDependencyConditions::resolveSplitDependencies(
TR::CodeGenerator* cg,
TR::Node* node, TR::Node* child,
TR::RegisterPair* regPair, List<TR::Register>& regList,
TR::Register*& reg, TR::Register*& highReg,
TR::Register*& copyReg, TR::Register*& highCopyReg,
TR::Instruction*& iCursor,
TR::RealRegister::RegNum& regNum)
{
TR::Compilation *comp = cg->comp();
TR_Debug * debugObj = cg->getDebug();
bool foundLow = false;
bool foundHigh = false;
if (regPair)
{
foundLow = regList.find(regPair->getLowOrder());
foundHigh = regList.find(regPair->getHighOrder());
}
else
{
foundLow = regList.find(reg);
}
if (foundLow || foundHigh)
{
TR::InstOpCode::Mnemonic opCode;
TR_RegisterKinds kind = reg->getKind();
bool isVector = kind == TR_VRF ? true : false;
if (kind == TR_GPR || kind == TR_FPR)
{
if (regPair)
{
highReg = regPair->getHighOrder();
reg = regPair->getLowOrder();
}
else if (child->getHighGlobalRegisterNumber() > -1)
{
TR_ASSERT( 0,"Long child does not have a register pair\n");
}
}
bool containsInternalPointer = false;
if (reg->getPinningArrayPointer())
{
containsInternalPointer = true;
}
copyReg = (reg->containsCollectedReference() && !containsInternalPointer) ?
cg->allocateCollectedReferenceRegister() :
cg->allocateRegister(kind);
if (containsInternalPointer)
{
copyReg->setContainsInternalPointer();
copyReg->setPinningArrayPointer(reg->getPinningArrayPointer());
}
switch (kind)
{
case TR_GPR:
if (reg->is64BitReg())
{
opCode = TR::InstOpCode::LGR;
}
else
{
opCode = TR::InstOpCode::LR;
}
break;
case TR_FPR:
opCode = TR::InstOpCode::LDR;
break;
case TR_VRF:
opCode = TR::InstOpCode::VLR;
break;
default:
TR_ASSERT( 0, "Invalid register kind.");
}
iCursor = isVector ? generateVRRaInstruction(cg, opCode, node, copyReg, reg, iCursor):
generateRRInstruction (cg, opCode, node, copyReg, reg, iCursor);
reg = copyReg;
if (debugObj)
{
if (isVector)
debugObj->addInstructionComment( toS390VRRaInstruction(iCursor), "VLR=Reg_deps2");
else
debugObj->addInstructionComment( toS390RRInstruction(iCursor), "LR=Reg_deps2");
}
if (highReg)
{
if(kind == TR_GPR)
{
containsInternalPointer = false;
if (highReg->getPinningArrayPointer())
{
containsInternalPointer = true;
}
highCopyReg = (highReg->containsCollectedReference() && !containsInternalPointer) ?
cg->allocateCollectedReferenceRegister() :
cg->allocateRegister(kind);
if (containsInternalPointer)
{
highCopyReg->setContainsInternalPointer();
highCopyReg->setPinningArrayPointer(highReg->getPinningArrayPointer());
}
iCursor = generateRRInstruction(cg, opCode, node, highCopyReg, highReg, iCursor);
highReg = highCopyReg;
}
else // kind == FPR
{
highCopyReg = cg->allocateRegister(kind);
iCursor = generateRRInstruction (cg, opCode, node, highCopyReg, highReg, iCursor);
debugObj->addInstructionComment( toS390RRInstruction(iCursor), "LR=Reg_deps2");
highReg = highCopyReg;
}
}
}
else
{
if (regPair)
{
regList.add(regPair->getHighOrder());
regList.add(regPair->getLowOrder());
}
else
{
regList.add(reg);
}
if (regPair)
{
highReg = regPair->getHighOrder();
reg = regPair->getLowOrder();
}
else if ((child->getHighGlobalRegisterNumber() > -1))
{
TR_ASSERT( 0, "Long child does not have a register pair\n");
}
}
}
TR::RegisterDependencyConditions *OMR::Z::RegisterDependencyConditions::clone(TR::CodeGenerator *cg, int32_t additionalRegDeps)
{
TR::RegisterDependencyConditions *other =
new (cg->trHeapMemory()) TR::RegisterDependencyConditions(_numPreConditions + additionalRegDeps,
_numPostConditions + additionalRegDeps, cg);
int32_t i = 0;
for (i = _numPreConditions-1; i >= 0; --i)
{
TR::RegisterDependency *dep = getPreConditions()->getRegisterDependency(i);
other->getPreConditions()->setDependencyInfo(i, dep->getRegister(), dep->getRealRegister(), dep->getFlags());
}
for (i = _numPostConditions-1; i >= 0; --i)
{
TR::RegisterDependency *dep = getPostConditions()->getRegisterDependency(i);
other->getPostConditions()->setDependencyInfo(i, dep->getRegister(), dep->getRealRegister(), dep->getFlags());
}
other->setAddCursorForPre(_addCursorForPre);
other->setAddCursorForPost(_addCursorForPost);
return other;
}
uint32_t
OMR::Z::RegisterDependencyConditions::setNumPreConditions(uint16_t n, TR_Memory * m)
{
if (_preConditions == NULL)
{
_preConditions = new (n,m) TR::RegisterDependencyGroup;
for (int32_t i = 0; i < n; i++)
{
_preConditions->clearDependencyInfo(i);
}
}
return _numPreConditions = n;
}
void
OMR::Z::RegisterDependencyConditions::addPreCondition(TR::Register *vr, TR::RealRegister::RegDep rr, uint8_t flag)
{
TR_ASSERT(!getIsUsed(), "ERROR: cannot add pre conditions to an used dependency, create a copy first\n");
// dont add dependencies if reg is real register
if (vr && vr->getRealRegister()!=NULL) return;
TR_ASSERT_FATAL(_addCursorForPre < _numPreConditions,"addPreCondition list overflow. addCursorForPre(%d), numPreConditions(%d), virtual register name(%s) and pointer(%p)\n",_addCursorForPre, _numPreConditions,vr->getRegisterName(_cg->comp()),vr);
_preConditions->setDependencyInfo(_addCursorForPre++, vr, rr, flag);
}
void
OMR::Z::RegisterDependencyConditions::addPostCondition(TR::Register *vr, TR::RealRegister::RegDep rr, uint8_t flag)
{
TR_ASSERT(!getIsUsed(), "ERROR: cannot add post conditions to an used dependency, create a copy first\n");
// dont add dependencies if reg is real register
if (vr && vr->getRealRegister()!=NULL) return;
TR_ASSERT_FATAL(_addCursorForPost < _numPostConditions,"addPostCondition list overflow. addCursorForPost(%d), numPostConditions(%d), virtual register name(%s) and pointer(%p)\n",_addCursorForPost, _numPostConditions,vr->getRegisterName(_cg->comp()),vr);
_postConditions->setDependencyInfo(_addCursorForPost++, vr, rr, flag);
}
void
OMR::Z::RegisterDependencyConditions::assignPreConditionRegisters(TR::Instruction *currentInstruction, TR_RegisterKinds kindToBeAssigned, TR::CodeGenerator *cg)
{
if (_preConditions != NULL)
{
cg->clearRegisterAssignmentFlags();
cg->setRegisterAssignmentFlag(TR_PreDependencyCoercion);
_preConditions->assignRegisters(currentInstruction, kindToBeAssigned, _addCursorForPre, cg);
}
}
void
OMR::Z::RegisterDependencyConditions::assignPostConditionRegisters(TR::Instruction *currentInstruction, TR_RegisterKinds kindToBeAssigned, TR::CodeGenerator *cg)
{
if (_postConditions != NULL)
{
cg->clearRegisterAssignmentFlags();
cg->setRegisterAssignmentFlag(TR_PostDependencyCoercion);
_postConditions->assignRegisters(currentInstruction, kindToBeAssigned, _addCursorForPost, cg);
}
}
TR::Register *
OMR::Z::RegisterDependencyConditions::searchPreConditionRegister(TR::RealRegister::RegNum rr, uint8_t flag)
{
return _preConditions==NULL?NULL:_preConditions->searchForRegister(rr, flag, _addCursorForPre, _cg);
}
TR::Register *
OMR::Z::RegisterDependencyConditions::searchPostConditionRegister(TR::RealRegister::RegNum rr, uint8_t flag)
{
return _postConditions==NULL?NULL:_postConditions->searchForRegister(rr, flag, _addCursorForPost, _cg);
}
TR::Register *
OMR::Z::RegisterDependencyConditions::searchPreConditionRegister(TR::Register * vr, uint8_t flag)
{
return _preConditions==NULL?NULL:_preConditions->searchForRegister(vr, flag, _addCursorForPre, _cg);
}
TR::Register *
OMR::Z::RegisterDependencyConditions::searchPostConditionRegister(TR::Register * vr, uint8_t flag)
{
return _postConditions==NULL?NULL:_postConditions->searchForRegister(vr, flag, _addCursorForPost, _cg);
}
int32_t
OMR::Z::RegisterDependencyConditions::searchPostConditionRegisterPos(TR::Register * vr, uint8_t flag)
{
return _postConditions==NULL?-1:_postConditions->searchForRegisterPos(vr, flag, _addCursorForPost, _cg);
}
void
OMR::Z::RegisterDependencyConditions::stopUsingDepRegs(TR::CodeGenerator *cg, TR::Register *ret1, TR::Register *ret2)
{
if (_preConditions != NULL)
_preConditions->stopUsingDepRegs(_addCursorForPre, ret1, ret2, cg);
if (_postConditions != NULL)
_postConditions->stopUsingDepRegs(_addCursorForPost, ret1, ret2, cg);
}
uint32_t
OMR::Z::RegisterDependencyConditions::setNumPostConditions(uint16_t n, TR_Memory * m)
{
if (_postConditions == NULL)
{
_postConditions = new (n,m) TR::RegisterDependencyGroup;
for (int32_t i = 0; i < n; i++)
{
_postConditions->clearDependencyInfo(i);
}
}
return _numPostConditions = n;
}
bool
OMR::Z::RegisterDependencyConditions::refsRegister(TR::Register * r)
{
for (int32_t i = 0; i < _numPreConditions; i++)
{
if (_preConditions->getRegisterDependency(i)->getRegister() == r &&
_preConditions->getRegisterDependency(i)->getRefsRegister())
{
return true;
}
}
for (int32_t j = 0; j < _numPostConditions; j++)
{
if (_postConditions->getRegisterDependency(j)->getRegister() == r &&
_postConditions->getRegisterDependency(j)->getRefsRegister())
{
return true;
}
}
return false;
}
bool
OMR::Z::RegisterDependencyConditions::defsRegister(TR::Register * r)
{
for (int32_t i = 0; i < _numPreConditions; i++)
{
if (_preConditions->getRegisterDependency(i)->getRegister() == r &&
_preConditions->getRegisterDependency(i)->getDefsRegister())
{
return true;
}
}
for (int32_t j = 0; j < _numPostConditions; j++)
{
if (_postConditions->getRegisterDependency(j)->getRegister() == r &&
_postConditions->getRegisterDependency(j)->getDefsRegister())
{
return true;
}
}
return false;
}
bool
OMR::Z::RegisterDependencyConditions::usesRegister(TR::Register * r)
{
for (int32_t i = 0; i < _numPreConditions; i++)
{
if (_preConditions->getRegisterDependency(i)->getRegister() == r &&
(_preConditions->getRegisterDependency(i)->getRefsRegister() || _preConditions->getRegisterDependency(i)->getDefsRegister()))
{
return true;
}
}
for (int32_t j = 0; j < _numPostConditions; j++)
{
if (_postConditions->getRegisterDependency(j)->getRegister() == r &&
(_postConditions->getRegisterDependency(j)->getRefsRegister() || _postConditions->getRegisterDependency(j)->getDefsRegister()))
{
return true;
}
}
return false;
}
/**
* Reason for oldPreCursor/oldPostCursor:
* When the dependencies have been created by merging new registers into an existing list then only call useRegister for the new registers in the list.
* Calling useRegister again on the existing registers will cause the totalUseCount to be too high and the virtual register will remain set to the real register
* for the entire duration of register assignment.
*/
void
OMR::Z::RegisterDependencyConditions::bookKeepingRegisterUses(TR::Instruction * instr, TR::CodeGenerator * cg, int32_t oldPreCursor, int32_t oldPostCursor)
{
if (instr->getOpCodeValue() != TR::InstOpCode::ASSOCREGS)
{
// We create a register association directive for each dependency
if (cg->enableRegisterAssociations() && !cg->isOutOfLineColdPath())
{
createRegisterAssociationDirective(instr, cg);
}
if (_preConditions != NULL)
{
for (int32_t i = oldPreCursor; i < _addCursorForPre; i++)
{
instr->useRegister(_preConditions->getRegisterDependency(i)->getRegister(), true);
}
}
if (_postConditions != NULL)
{
for (int32_t j = oldPostCursor; j < _addCursorForPost; j++)
{
instr->useRegister(_postConditions->getRegisterDependency(j)->getRegister(), true);
}
}
}
}
uint32_t
OMR::Z::RegisterDependencyGroup::genBitMapOfAssignableGPRs(TR::CodeGenerator * cg,
uint32_t numberOfRegisters)
{
TR::Machine* machine = cg->machine();
// TODO: This looks like it can be cached as it should be the same value every time in a single compilation. Should
// also investigate whether we even need this? Don't we already block registers which are part of a dependency? I
// suppose with a mask we can avoid shuffling things into GPRs which are part of the dependency and may need to get
// other virtual registers shuffled into such GPRs. Need to think about this. Are other codegens doing this?
uint32_t availRegMap = machine->genBitMapOfAssignableGPRs();
for (uint32_t i = 0; i < numberOfRegisters; i++)
{
TR::RealRegister::RegNum realReg = _dependencies[i].getRealRegister();
if (TR::RealRegister::isGPR(realReg))
{
availRegMap &= ~machine->getRealRegister(realReg)->getRealRegisterMask();
}
}
return availRegMap;
}
void
OMR::Z::RegisterDependencyGroup::assignRegisters(TR::Instruction *currentInstruction,
TR_RegisterKinds kindToBeAssigned,
uint32_t numOfDependencies,
TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR::Machine *machine = cg->machine();
TR::Register * virtReg;
TR::RealRegister::RegNum dependentRegNum;
TR::RealRegister * dependentRealReg, * assignedRegister;
int32_t i, j;
bool changed;
uint32_t availRegMask = genBitMapOfAssignableGPRs(cg, numOfDependencies);
for (i = 0; i< numOfDependencies; i++)
{
TR::RegisterDependency ®Dep = _dependencies[i];
virtReg = regDep.getRegister();
if (regDep.isSpilledReg() && !virtReg->getRealRegister())
{
TR_ASSERT_FATAL(virtReg->getBackingStorage() != NULL, "Spilled virtual register on dependency list does not have backing storage");
if (virtReg->getAssignedRealRegister())
{
// this happens when the register was first spilled in main line path then was reverse spilled
// and assigned to a real register in OOL path. We protected the backing store when doing
// the reverse spill so we could re-spill to the same slot now
TR::Node *currentNode = currentInstruction->getNode();
TR::RealRegister *assignedReg = toRealRegister(virtReg->getAssignedRegister());
cg->traceRegisterAssignment ("\nOOL: Found %R spilled in main line and reused inside OOL", virtReg);
TR::MemoryReference * tempMR = generateS390MemoryReference(currentNode, virtReg->getBackingStorage()->getSymbolReference(), cg);
TR::InstOpCode::Mnemonic opCode;
TR_RegisterKinds rk = virtReg->getKind();
switch (rk)
{
case TR_GPR:
if (virtReg->is64BitReg())
{
opCode = TR::InstOpCode::LG;
}
else
{
opCode = TR::InstOpCode::L;
}
break;
case TR_FPR:
opCode = TR::InstOpCode::LD;
break;
case TR_VRF:
opCode = TR::InstOpCode::VL;
break;
default:
TR_ASSERT( 0, "\nRegister kind not supported in OOL spill\n");
break;
}
bool isVector = (rk == TR_VRF);
TR::Instruction *inst = isVector ? generateVRXInstruction(cg, opCode, currentNode, assignedReg, tempMR, 0, currentInstruction) :
generateRXInstruction (cg, opCode, currentNode, assignedReg, tempMR, currentInstruction);
cg->traceRAInstruction(inst);
assignedReg->setAssignedRegister(NULL);
virtReg->setAssignedRegister(NULL);
assignedReg->setState(TR::RealRegister::Free);
}
// now we are leaving the OOL sequence, anything that was previously spilled in OOL hot path or main line
// should be considered as mainline spill for the next OOL sequence.
virtReg->getBackingStorage()->setMaxSpillDepth(1);
}
// we also need to free up all locked backing storage if we are exiting the OOL during backwards RA assignment
else if (currentInstruction->isLabel() && virtReg->getAssignedRealRegister())
{
TR_BackingStore * location = virtReg->getBackingStorage();
TR_RegisterKinds rk = virtReg->getKind();
int32_t dataSize;
if (toS390LabelInstruction(currentInstruction)->getLabelSymbol()->isStartOfColdInstructionStream() &&
location)
{
traceMsg (comp,"\nOOL: Releasing backing storage (%p)\n", location);
if (rk == TR_GPR)
dataSize = TR::Compiler->om.sizeofReferenceAddress();
else if (rk == TR_VRF)
dataSize = 16; // Will change to 32 in a few years..
else
dataSize = 8;
location->setMaxSpillDepth(0);
cg->freeSpill(location,dataSize,0);
virtReg->setBackingStorage(NULL);
}
}
}
uint32_t numGPRs = 0;
uint32_t numFPRs = 0;
uint32_t numVRFs = 0;
// Used to do lookups using real register numbers
OMR::RegisterDependencyMap map(_dependencies, numOfDependencies);
for (i = 0; i < numOfDependencies; i++)
{
TR::RegisterDependency ®Dep = _dependencies[i];
map.addDependency(regDep, i);
if (!regDep.isSpilledReg() &&
!regDep.isKillVolHighRegs() &&
!regDep.isNoReg())
{
virtReg = regDep.getRegister();
switch (virtReg->getKind())
{
case TR_GPR:
++numGPRs;
break;
case TR_FPR:
++numFPRs;
break;
case TR_VRF:
++numVRFs;
break;
default:
break;
}
}
}
#ifdef DEBUG
int32_t lockedGPRs = 0;
int32_t lockedFPRs = 0;
int32_t lockedVRFs = 0;
// count up how many registers are locked for each type
for (int32_t i = TR::RealRegister::FirstGPR; i <= TR::RealRegister::LastGPR; ++i)
{
TR::RealRegister* realReg = machine->getRealRegister((TR::RealRegister::RegNum)i);
if (realReg->getState() == TR::RealRegister::Locked)
++lockedGPRs;
}
for (int32_t i = TR::RealRegister::FirstFPR; i <= TR::RealRegister::LastFPR; ++i)
{
TR::RealRegister* realReg = machine->getRealRegister((TR::RealRegister::RegNum)i);
if (realReg->getState() == TR::RealRegister::Locked)
++lockedFPRs;
}
for (int32_t i = TR::RealRegister::FirstVRF; i <= TR::RealRegister::LastVRF; ++i)
{
TR::RealRegister* realReg = machine->getRealRegister((TR::RealRegister::RegNum)i);
if (realReg->getState() == TR::RealRegister::Locked)
++lockedVRFs;
}
TR_ASSERT(lockedGPRs == machine->getNumberOfLockedRegisters(TR_GPR), "Inconsistent number of locked GPRs");
TR_ASSERT(lockedFPRs == machine->getNumberOfLockedRegisters(TR_FPR), "Inconsistent number of locked FPRs");
TR_ASSERT(lockedVRFs == machine->getNumberOfLockedRegisters(TR_VRF), "Inconsistent number of locked VRFs");
#endif
// To handle circular dependencies, we block a real register if (1) it is already assigned to a correct
// virtual register and (2) if it is assigned to one register in the list but is required by another.
// However, if all available registers are requested, we do not block in case (2) to avoid all registers
// being blocked.
bool haveSpareGPRs = true;
bool haveSpareFPRs = true;
bool haveSpareVRFs = true;
TR_ASSERT(numGPRs <= (TR::RealRegister::LastGPR - TR::RealRegister::FirstGPR + 1 - machine->getNumberOfLockedRegisters(TR_GPR)), "Too many GPR dependencies, unable to assign");
TR_ASSERT(numFPRs <= (TR::RealRegister::LastFPR - TR::RealRegister::FirstFPR + 1 - machine->getNumberOfLockedRegisters(TR_FPR)), "Too many FPR dependencies, unable to assign");
TR_ASSERT(numVRFs <= (TR::RealRegister::LastVRF - TR::RealRegister::FirstVRF + 1 - machine->getNumberOfLockedRegisters(TR_VRF)), "Too many VRF dependencies, unable to assign");
if (numGPRs == (TR::RealRegister::LastGPR - TR::RealRegister::FirstGPR + 1 - machine->getNumberOfLockedRegisters(TR_GPR)))
haveSpareGPRs = false;
if (numFPRs == (TR::RealRegister::LastFPR - TR::RealRegister::FirstFPR + 1 - machine->getNumberOfLockedRegisters(TR_FPR)))
haveSpareFPRs = false;
if (numVRFs == (TR::RealRegister::LastVRF - TR::RealRegister::FirstVRF + 1 - machine->getNumberOfLockedRegisters(TR_VRF)))
haveSpareVRFs = false;
for (i = 0; i < numOfDependencies; i++)
{
virtReg = _dependencies[i].getRegister();
if (virtReg->getAssignedRealRegister() != NULL)
{
if (_dependencies[i].isNoReg())
{
virtReg->block();
}
else
{
TR::RealRegister::RegNum assignedRegNum = toRealRegister(virtReg->getAssignedRealRegister())->getRegisterNumber();
// Always block if the required register and assigned register match or if the assigned register is
// required by another dependency but only if there are any spare registers left so as to avoid blocking
// all existing registers
if (_dependencies[i].getRealRegister() == assignedRegNum ||
(map.getDependencyWithTarget(assignedRegNum) &&
((virtReg->getKind() != TR_GPR || haveSpareGPRs) &&
(virtReg->getKind() != TR_FPR || haveSpareFPRs) &&
(virtReg->getKind() != TR_VRF || haveSpareVRFs))))
{
virtReg->block();
}
}
}
// Check for directive to spill high registers. Used on callouts
if ( _dependencies[i].isKillVolHighRegs())
{
machine->spillAllVolatileHighRegisters(currentInstruction);
_dependencies[i].setRealRegister(TR::RealRegister::NoReg); // ignore from now on
}
}
///// REGISTER PAIRS
// We handle register pairs by passing regpair dependencies stubs into the register dependency
// list. The following pieces of code are responsible for replacing these stubs with actual
// real register values, using register allocation routines in the S390Machine, and hence,
// allow the dependency routines to complete the allocation.
//
// We need to run through the list of dependencies looking for register pairs.
// We assign a register pair to any such pairs that are found and then look for the low
// and high order regs in the list of deps. We update the low and high order pair deps with
// the real reg assigned by to the pair, and then let the these deps be handled as any other
// single reg dep.
//
// If the virt registers have already been assigned, the low and high order
// regs obtained from regPair will not match the ones in the dependency list.
// Hence, will fall through the dep entries for the associated virt high
// and low regs as the real high and low will not match the dep virt reg entries.
//
for (i = 0; i < numOfDependencies; i++)
{
TR::RegisterDependency ®Dep = _dependencies[i];
// Get reg pair pointer
//
TR::RegisterPair * virtRegPair = regDep.getRegister()->getRegisterPair();
// If it is a register pair
//
if (virtRegPair == NULL)
{
continue;
}
// Is this an Even-Odd pair assignment
//
if (regDep.isEvenOddPair()