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OMRCodeGenerator.cpp
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OMRCodeGenerator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include "codegen/AheadOfTimeCompile.hpp"
#include "codegen/BackingStore.hpp"
#include "codegen/CodeGenPhase.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/CodeGenerator_inlines.hpp"
#include "codegen/CodeGeneratorUtils.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/GCStackAtlas.hpp"
#include "codegen/GCStackMap.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LinkageConventionsEnum.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/RecognizedMethods.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterIterator.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/Relocation.hpp"
#include "codegen/Snippet.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "control/Recompilation.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "codegen/PrivateLinkage.hpp"
#include "control/RecompilationInfo.hpp"
#endif
#include "env/CompilerEnv.hpp"
#include "env/CPU.hpp"
#include "env/PersistentInfo.hpp"
#include "env/Processors.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/AutomaticSymbol.hpp"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ParameterSymbol.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/StaticSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Array.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "infra/BitVector.hpp"
#include "infra/Cfg.hpp"
#include "infra/Link.hpp"
#include "infra/List.hpp"
#include "optimizer/Optimizer.hpp"
#include "optimizer/RegisterCandidate.hpp"
#include "optimizer/Structure.hpp"
#include "optimizer/DataFlowAnalysis.hpp"
#include "p/codegen/GenerateInstructions.hpp"
#include "p/codegen/PPCHelperCallSnippet.hpp"
#include "p/codegen/PPCInstruction.hpp"
#include "p/codegen/PPCOutOfLineCodeSection.hpp"
#include "p/codegen/PPCSystemLinkage.hpp"
#include "p/codegen/PPCTableOfConstants.hpp"
#include "ras/Debug.hpp"
#include "ras/DebugCounter.hpp"
#include "runtime/Runtime.hpp"
#if defined(AIXPPC)
#include <sys/debug.h>
#endif
OMR::Power::CodeGenerator::CodeGenerator(TR::Compilation *comp) :
OMR::CodeGenerator(comp),
_stackPtrRegister(NULL),
_constantData(NULL),
_blockCallInfo(NULL),
_transientLongRegisters(comp->trMemory()),
conversionBuffer(NULL),
_outOfLineCodeSectionList(getTypedAllocator<TR_PPCOutOfLineCodeSection*>(comp->allocator())),
_startPCLabel(NULL)
{
}
void
OMR::Power::CodeGenerator::initialize()
{
self()->OMR::CodeGenerator::initialize();
TR::CodeGenerator *cg = self();
TR::Compilation *comp = self()->comp();
// Initialize Linkage for Code Generator
cg->initializeLinkage();
_unlatchedRegisterList =
(TR::RealRegister**)cg->trMemory()->allocateHeapMemory(sizeof(TR::RealRegister*)*(TR::RealRegister::NumRegisters + 1));
_unlatchedRegisterList[0] = 0; // mark that list is empty
_linkageProperties = &cg->getLinkage()->getProperties();
// Set up to collect items for later TOC mapping
if (comp->target().is64Bit())
{
cg->setTrackStatics(new (cg->trHeapMemory()) TR_Array<TR::SymbolReference *>(cg->trMemory()));
cg->setTrackItems(new (cg->trHeapMemory()) TR_Array<TR_PPCLoadLabelItem *>(cg->trMemory()));
}
else
{
cg->setTrackStatics(NULL);
cg->setTrackItems(NULL);
}
cg->setStackPointerRegister(cg->machine()->getRealRegister(_linkageProperties->getNormalStackPointerRegister()));
cg->setMethodMetaDataRegister(cg->machine()->getRealRegister(_linkageProperties->getMethodMetaDataRegister()));
cg->setTOCBaseRegister(cg->machine()->getRealRegister(_linkageProperties->getTOCBaseRegister()));
cg->getLinkage()->initPPCRealRegisterLinkage();
cg->getLinkage()->setParameterLinkageRegisterIndex(comp->getJittedMethodSymbol());
cg->machine()->initREGAssociations();
// Tactical GRA settings.
//
cg->setGlobalGPRPartitionLimit(TR::Machine::getGlobalGPRPartitionLimit());
cg->setGlobalFPRPartitionLimit(TR::Machine::getGlobalFPRPartitionLimit());
cg->setGlobalRegisterTable(_linkageProperties->getRegisterAllocationOrder());
_numGPR = _linkageProperties->getNumAllocatableIntegerRegisters();
_firstGPR = 0;
_lastGPR = _numGPR - 1;
_firstParmGPR = _linkageProperties->getFirstAllocatableIntegerArgumentRegister();
_lastVolatileGPR = _linkageProperties->getLastAllocatableIntegerVolatileRegister();
_numFPR = _linkageProperties->getNumAllocatableFloatRegisters();
_firstFPR = _numGPR;
_lastFPR = _firstFPR + _numFPR - 1;
_firstParmFPR = _linkageProperties->getFirstAllocatableFloatArgumentRegister();
_lastVolatileFPR = _linkageProperties->getLastAllocatableFloatVolatileRegister();
cg->setLastGlobalGPR(_lastGPR);
cg->setLast8BitGlobalGPR(_lastGPR);
cg->setLastGlobalFPR(_lastFPR);
_numVRF = _linkageProperties->getNumAllocatableVectorRegisters();
cg->setFirstGlobalVRF(_lastFPR + 1);
cg->setLastGlobalVRF(_lastFPR + _numVRF);
cg->setSupportsGlRegDeps();
cg->setSupportsGlRegDepOnFirstBlock();
cg->setSupportsRecompilation();
if (comp->target().is32Bit())
cg->setUsesRegisterPairsForLongs();
cg->setPerformsChecksExplicitly();
cg->setConsiderAllAutosAsTacticalGlobalRegisterCandidates();
cg->setEnableRefinedAliasSets();
static char * accessStaticsIndirectly = feGetEnv("TR_AccessStaticsIndirectly");
if (accessStaticsIndirectly)
cg->setAccessStaticsIndirectly(true);
if (!debug("noLiveRegisters"))
{
cg->addSupportedLiveRegisterKind(TR_GPR);
cg->addSupportedLiveRegisterKind(TR_FPR);
cg->addSupportedLiveRegisterKind(TR_CCR);
cg->addSupportedLiveRegisterKind(TR_VSX_SCALAR);
cg->addSupportedLiveRegisterKind(TR_VSX_VECTOR);
cg->addSupportedLiveRegisterKind(TR_VRF);
cg->setLiveRegisters(new (cg->trHeapMemory()) TR_LiveRegisters(comp), TR_GPR);
cg->setLiveRegisters(new (cg->trHeapMemory()) TR_LiveRegisters(comp), TR_FPR);
cg->setLiveRegisters(new (cg->trHeapMemory()) TR_LiveRegisters(comp), TR_CCR);
cg->setLiveRegisters(new (cg->trHeapMemory()) TR_LiveRegisters(comp), TR_VRF);
cg->setLiveRegisters(new (cg->trHeapMemory()) TR_LiveRegisters(comp), TR_VSX_SCALAR);
cg->setLiveRegisters(new (cg->trHeapMemory()) TR_LiveRegisters(comp), TR_VSX_VECTOR);
}
cg->setSupportsConstantOffsetInAddressing();
cg->setSupportsVirtualGuardNOPing();
cg->setSupportsPrimitiveArrayCopy();
cg->setSupportsReferenceArrayCopy();
cg->setSupportsSelect();
cg->setSupportsByteswap();
// disabled for now
//
if (comp->getOption(TR_AggressiveOpts) &&
!comp->getOption(TR_DisableArraySetOpts))
{
cg->setSupportsArraySet();
}
cg->setSupportsArrayCmp();
if (comp->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
{
static bool disablePPCTRTO = (feGetEnv("TR_disablePPCTRTO") != NULL);
static bool disablePPCTRTO255 = (feGetEnv("TR_disablePPCTRTO255") != NULL);
static bool disablePPCTROT = (feGetEnv("TR_disablePPCTROT") != NULL);
static bool disablePPCTROTNoBreak = (feGetEnv("TR_disablePPCTROTNoBreak") != NULL);
if (!disablePPCTRTO)
cg->setSupportsArrayTranslateTRTO();
#ifndef __LITTLE_ENDIAN__
else if (!disablePPCTRTO255)
setSupportsArrayTranslateTRTO255();
#endif
if (!disablePPCTROT)
cg->setSupportsArrayTranslateTROT();
if (!disablePPCTROTNoBreak)
cg->setSupportsArrayTranslateTROTNoBreak();
}
_numberBytesReadInaccessible = 0;
_numberBytesWriteInaccessible = 4096;
// Poorly named. Not necessarily Java specific.
//
cg->setSupportsJavaFloatSemantics();
cg->setSupportsDivCheck();
cg->setSupportsLoweringConstIDiv();
if (comp->target().is64Bit())
cg->setSupportsLoweringConstLDiv();
cg->setSupportsLoweringConstLDivPower2();
static bool disableDCAS = (feGetEnv("TR_DisablePPCDCAS") != NULL);
if (!disableDCAS &&
comp->target().is64Bit() &&
TR::Options::useCompressedPointers())
{
cg->setSupportsDoubleWordCAS();
cg->setSupportsDoubleWordSet();
}
if (cg->is64BitProcessor())
cg->setSupportsInlinedAtomicLongVolatiles();
// Standard allows only offset multiple of 4
// TODO: either improves the query to be size-based or gets the offset into a register
if (comp->target().is64Bit())
cg->setSupportsAlignedAccessOnly();
// TODO: distinguishing among OOO and non-OOO implementations
if (comp->target().isSMP())
cg->setEnforceStoreOrder();
if (!comp->getOption(TR_DisableTraps) && TR::Compiler->vm.hasResumableTrapHandler(comp))
cg->setHasResumableTrapHandler();
/*
* TODO: TM is currently not compatible with read barriers. If read barriers are required, TM is disabled until the issue is fixed.
* TM is now disabled by default, due to various reasons (OS, hardware, etc), unless it is explicitly enabled.
*/
if (comp->target().cpu.supportsFeature(OMR_FEATURE_PPC_HTM) && comp->getOption(TR_EnableTM) &&
!comp->getOption(TR_DisableTM) && TR::Compiler->om.readBarrierType() == gc_modron_readbar_none)
cg->setSupportsTM();
if (comp->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_ALTIVEC) && comp->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
cg->setSupportsAutoSIMD();
if (!comp->getOption(TR_DisableRegisterPressureSimulation))
{
for (int32_t i = 0; i < TR_numSpillKinds; i++)
_globalRegisterBitVectors[i].init(cg->getNumberOfGlobalRegisters(), cg->trMemory());
for (TR_GlobalRegisterNumber grn=0; grn < cg->getNumberOfGlobalRegisters(); grn++)
{
TR::RealRegister::RegNum reg = (TR::RealRegister::RegNum)cg->getGlobalRegister(grn);
if (cg->getFirstGlobalGPR() <= grn && grn <= cg->getLastGlobalGPR())
_globalRegisterBitVectors[ TR_gprSpill ].set(grn);
else if (cg->getFirstGlobalFPR() <= grn && grn <= cg->getLastGlobalFPR())
_globalRegisterBitVectors[ TR_fprSpill ].set(grn);
if (!cg->getProperties().getPreserved(reg))
_globalRegisterBitVectors[ TR_volatileSpill ].set(grn);
if (cg->getProperties().getIntegerArgument(reg) || cg->getProperties().getFloatArgument(reg))
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
}
}
// Calculate inverse of getGlobalRegister function
//
TR_GlobalRegisterNumber grn;
int i;
TR_GlobalRegisterNumber globalRegNumbers[TR::RealRegister::NumRegisters];
for (i=0; i < cg->getNumberOfGlobalGPRs(); i++)
{
grn = cg->getFirstGlobalGPR() + i;
globalRegNumbers[cg->getGlobalRegister(grn)] = grn;
}
for (i=0; i < cg->getNumberOfGlobalFPRs(); i++)
{
grn = cg->getFirstGlobalFPR() + i;
globalRegNumbers[cg->getGlobalRegister(grn)] = grn;
}
// Initialize linkage reg arrays
TR::PPCLinkageProperties linkageProperties = cg->getProperties();
for (i=0; i < linkageProperties.getNumIntArgRegs(); i++)
_gprLinkageGlobalRegisterNumbers[i] = globalRegNumbers[linkageProperties.getIntegerArgumentRegister(i)];
for (i=0; i < linkageProperties.getNumFloatArgRegs(); i++)
_fprLinkageGlobalRegisterNumbers[i] = globalRegNumbers[linkageProperties.getFloatArgumentRegister(i)];
if (comp->getOption(TR_TraceRA))
{
cg->setGPRegisterIterator(new (cg->trHeapMemory()) TR::RegisterIterator(cg->machine(), TR::RealRegister::FirstGPR, TR::RealRegister::LastGPR));
cg->setFPRegisterIterator(new (cg->trHeapMemory()) TR::RegisterIterator(cg->machine(), TR::RealRegister::FirstFPR, TR::RealRegister::LastFPR));
}
cg->setSupportsProfiledInlining();
TR_ResolvedMethod *method = comp->getJittedMethodSymbol()->getResolvedMethod();
TR_ReturnInfo returnInfo = cg->getLinkage()->getReturnInfoFromReturnType(method->returnType());
comp->setReturnInfo(returnInfo);
}
OMR::Power::CodeGenerator::CodeGenerator() :
OMR::CodeGenerator(),
_stackPtrRegister(NULL),
_constantData(NULL),
_blockCallInfo(NULL),
_transientLongRegisters(self()->trMemory()),
conversionBuffer(NULL),
_outOfLineCodeSectionList(getTypedAllocator<TR_PPCOutOfLineCodeSection*>(self()->comp()->allocator())),
_startPCLabel(NULL)
{
// Initialize Linkage for Code Generator
self()->initializeLinkage();
_unlatchedRegisterList =
(TR::RealRegister**)self()->trMemory()->allocateHeapMemory(sizeof(TR::RealRegister*)*(TR::RealRegister::NumRegisters + 1));
_unlatchedRegisterList[0] = 0; // mark that list is empty
_linkageProperties = &self()->getLinkage()->getProperties();
// Set up to collect items for later TOC mapping
if (self()->comp()->target().is64Bit())
{
self()->setTrackStatics(new (self()->trHeapMemory()) TR_Array<TR::SymbolReference *>(self()->trMemory()));
self()->setTrackItems(new (self()->trHeapMemory()) TR_Array<TR_PPCLoadLabelItem *>(self()->trMemory()));
}
else
{
self()->setTrackStatics(NULL);
self()->setTrackItems(NULL);
}
self()->setStackPointerRegister(self()->machine()->getRealRegister(_linkageProperties->getNormalStackPointerRegister()));
self()->setMethodMetaDataRegister(self()->machine()->getRealRegister(_linkageProperties->getMethodMetaDataRegister()));
self()->setTOCBaseRegister(self()->machine()->getRealRegister(_linkageProperties->getTOCBaseRegister()));
self()->getLinkage()->initPPCRealRegisterLinkage();
self()->getLinkage()->setParameterLinkageRegisterIndex(self()->comp()->getJittedMethodSymbol());
self()->machine()->initREGAssociations();
// Tactical GRA settings.
//
self()->setGlobalGPRPartitionLimit(TR::Machine::getGlobalGPRPartitionLimit());
self()->setGlobalFPRPartitionLimit(TR::Machine::getGlobalFPRPartitionLimit());
self()->setGlobalRegisterTable(_linkageProperties->getRegisterAllocationOrder());
_numGPR = _linkageProperties->getNumAllocatableIntegerRegisters();
_firstGPR = 0;
_lastGPR = _numGPR - 1;
_firstParmGPR = _linkageProperties->getFirstAllocatableIntegerArgumentRegister();
_lastVolatileGPR = _linkageProperties->getLastAllocatableIntegerVolatileRegister();
_numFPR = _linkageProperties->getNumAllocatableFloatRegisters();
_firstFPR = _numGPR;
_lastFPR = _firstFPR + _numFPR - 1;
_firstParmFPR = _linkageProperties->getFirstAllocatableFloatArgumentRegister();
_lastVolatileFPR = _linkageProperties->getLastAllocatableFloatVolatileRegister();
self()->setLastGlobalGPR(_lastGPR);
self()->setLast8BitGlobalGPR(_lastGPR);
self()->setLastGlobalFPR(_lastFPR);
_numVRF = _linkageProperties->getNumAllocatableVectorRegisters();
self()->setFirstGlobalVRF(_lastFPR + 1);
self()->setLastGlobalVRF(_lastFPR + _numVRF);
self()->setSupportsGlRegDeps();
self()->setSupportsGlRegDepOnFirstBlock();
self()->setSupportsRecompilation();
if (self()->comp()->target().is32Bit())
self()->setUsesRegisterPairsForLongs();
self()->setPerformsChecksExplicitly();
self()->setConsiderAllAutosAsTacticalGlobalRegisterCandidates();
self()->setEnableRefinedAliasSets();
static char * accessStaticsIndirectly = feGetEnv("TR_AccessStaticsIndirectly");
if (accessStaticsIndirectly)
self()->setAccessStaticsIndirectly(true);
if (!debug("noLiveRegisters"))
{
self()->addSupportedLiveRegisterKind(TR_GPR);
self()->addSupportedLiveRegisterKind(TR_FPR);
self()->addSupportedLiveRegisterKind(TR_CCR);
self()->addSupportedLiveRegisterKind(TR_VSX_SCALAR);
self()->addSupportedLiveRegisterKind(TR_VSX_VECTOR);
self()->addSupportedLiveRegisterKind(TR_VRF);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(self()->comp()), TR_GPR);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(self()->comp()), TR_FPR);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(self()->comp()), TR_CCR);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(self()->comp()), TR_VRF);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(self()->comp()), TR_VSX_SCALAR);
self()->setLiveRegisters(new (self()->trHeapMemory()) TR_LiveRegisters(self()->comp()), TR_VSX_VECTOR);
}
self()->setSupportsConstantOffsetInAddressing();
self()->setSupportsVirtualGuardNOPing();
self()->setSupportsPrimitiveArrayCopy();
self()->setSupportsReferenceArrayCopy();
self()->setSupportsSelect();
self()->setSupportsByteswap();
// disabled for now
//
if (self()->comp()->getOption(TR_AggressiveOpts) &&
!self()->comp()->getOption(TR_DisableArraySetOpts))
{
self()->setSupportsArraySet();
}
self()->setSupportsArrayCmp();
if (self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
{
static bool disablePPCTRTO = (feGetEnv("TR_disablePPCTRTO") != NULL);
static bool disablePPCTRTO255 = (feGetEnv("TR_disablePPCTRTO255") != NULL);
static bool disablePPCTROT = (feGetEnv("TR_disablePPCTROT") != NULL);
static bool disablePPCTROTNoBreak = (feGetEnv("TR_disablePPCTROTNoBreak") != NULL);
if (!disablePPCTRTO)
self()->setSupportsArrayTranslateTRTO();
#ifndef __LITTLE_ENDIAN__
else if (!disablePPCTRTO255)
setSupportsArrayTranslateTRTO255();
#endif
if (!disablePPCTROT)
self()->setSupportsArrayTranslateTROT();
if (!disablePPCTROTNoBreak)
self()->setSupportsArrayTranslateTROTNoBreak();
}
_numberBytesReadInaccessible = 0;
_numberBytesWriteInaccessible = 4096;
// Poorly named. Not necessarily Java specific.
//
self()->setSupportsJavaFloatSemantics();
self()->setSupportsDivCheck();
self()->setSupportsLoweringConstIDiv();
if (self()->comp()->target().is64Bit())
self()->setSupportsLoweringConstLDiv();
self()->setSupportsLoweringConstLDivPower2();
static bool disableDCAS = (feGetEnv("TR_DisablePPCDCAS") != NULL);
if (!disableDCAS &&
self()->comp()->target().is64Bit() &&
TR::Options::useCompressedPointers())
{
self()->setSupportsDoubleWordCAS();
self()->setSupportsDoubleWordSet();
}
if (self()->is64BitProcessor())
self()->setSupportsInlinedAtomicLongVolatiles();
// Standard allows only offset multiple of 4
// TODO: either improves the query to be size-based or gets the offset into a register
if (self()->comp()->target().is64Bit())
self()->setSupportsAlignedAccessOnly();
// TODO: distinguishing among OOO and non-OOO implementations
if (self()->comp()->target().isSMP())
self()->setEnforceStoreOrder();
if (!self()->comp()->getOption(TR_DisableTraps) && TR::Compiler->vm.hasResumableTrapHandler(self()->comp()))
self()->setHasResumableTrapHandler();
/*
* TODO: TM is currently not compatible with read barriers. If read barriers are required, TM is disabled until the issue is fixed.
* TM is now disabled by default, due to various reasons (OS, hardware, etc), unless it is explicitly enabled.
*/
if (self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HTM) && self()->comp()->getOption(TR_EnableTM) &&
!self()->comp()->getOption(TR_DisableTM) && TR::Compiler->om.readBarrierType() == gc_modron_readbar_none)
self()->setSupportsTM();
if (self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_ALTIVEC) && self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
self()->setSupportsAutoSIMD();
if (!self()->comp()->getOption(TR_DisableRegisterPressureSimulation))
{
for (int32_t i = 0; i < TR_numSpillKinds; i++)
_globalRegisterBitVectors[i].init(self()->getNumberOfGlobalRegisters(), self()->trMemory());
for (TR_GlobalRegisterNumber grn=0; grn < self()->getNumberOfGlobalRegisters(); grn++)
{
TR::RealRegister::RegNum reg = (TR::RealRegister::RegNum)self()->getGlobalRegister(grn);
if (self()->getFirstGlobalGPR() <= grn && grn <= self()->getLastGlobalGPR())
_globalRegisterBitVectors[ TR_gprSpill ].set(grn);
else if (self()->getFirstGlobalFPR() <= grn && grn <= self()->getLastGlobalFPR())
_globalRegisterBitVectors[ TR_fprSpill ].set(grn);
if (!self()->getProperties().getPreserved(reg))
_globalRegisterBitVectors[ TR_volatileSpill ].set(grn);
if (self()->getProperties().getIntegerArgument(reg) || self()->getProperties().getFloatArgument(reg))
_globalRegisterBitVectors[ TR_linkageSpill ].set(grn);
}
}
// Calculate inverse of getGlobalRegister function
//
TR_GlobalRegisterNumber grn;
int i;
TR_GlobalRegisterNumber globalRegNumbers[TR::RealRegister::NumRegisters];
for (i=0; i < self()->getNumberOfGlobalGPRs(); i++)
{
grn = self()->getFirstGlobalGPR() + i;
globalRegNumbers[self()->getGlobalRegister(grn)] = grn;
}
for (i=0; i < self()->getNumberOfGlobalFPRs(); i++)
{
grn = self()->getFirstGlobalFPR() + i;
globalRegNumbers[self()->getGlobalRegister(grn)] = grn;
}
// Initialize linkage reg arrays
TR::PPCLinkageProperties linkageProperties = self()->getProperties();
for (i=0; i < linkageProperties.getNumIntArgRegs(); i++)
_gprLinkageGlobalRegisterNumbers[i] = globalRegNumbers[linkageProperties.getIntegerArgumentRegister(i)];
for (i=0; i < linkageProperties.getNumFloatArgRegs(); i++)
_fprLinkageGlobalRegisterNumbers[i] = globalRegNumbers[linkageProperties.getFloatArgumentRegister(i)];
if (self()->comp()->getOption(TR_TraceRA))
{
self()->setGPRegisterIterator(new (self()->trHeapMemory()) TR::RegisterIterator(self()->machine(), TR::RealRegister::FirstGPR, TR::RealRegister::LastGPR));
self()->setFPRegisterIterator(new (self()->trHeapMemory()) TR::RegisterIterator(self()->machine(), TR::RealRegister::FirstFPR, TR::RealRegister::LastFPR));
}
self()->setSupportsProfiledInlining();
TR_ResolvedMethod *method = self()->comp()->getJittedMethodSymbol()->getResolvedMethod();
TR_ReturnInfo returnInfo = self()->getLinkage()->getReturnInfoFromReturnType(method->returnType());
self()->comp()->setReturnInfo(returnInfo);
}
TR::Linkage *
OMR::Power::CodeGenerator::deriveCallingLinkage(TR::Node *node, bool isIndirect)
{
TR::SymbolReference *symRef = node->getSymbolReference();
TR::MethodSymbol *callee = symRef->getSymbol()->castToMethodSymbol();
TR::Linkage *linkage = self()->getLinkage(callee->getLinkageConvention());
return linkage;
}
uintptr_t *
OMR::Power::CodeGenerator::getTOCBase()
{
TR_PPCTableOfConstants *pTOC = toPPCTableOfConstants(self()->comp()->getPersistentInfo()->getPersistentTOC());
return pTOC->getTOCBase();
}
TR_PPCScratchRegisterManager*
OMR::Power::CodeGenerator::generateScratchRegisterManager(int32_t capacity)
{
return new (self()->trHeapMemory()) TR_PPCScratchRegisterManager(capacity, self());
}
// PPC codeGenerator hook for class unloading events
//
void
OMR::Power::CodeGenerator::ppcCGOnClassUnloading(void *loaderPtr)
{
if (!TR::Options::getCmdLineOptions()->getOption(TR_DisableTOC))
TR_PPCTableOfConstants::onClassUnloading(loaderPtr);
}
TR_RuntimeHelper
directToInterpreterHelper(
TR::ResolvedMethodSymbol *methodSymbol,
TR::CodeGenerator *cg)
{
#ifdef J9_PROJECT_SPECIFIC
return methodSymbol->getVMCallHelper();
#else
return (TR_RuntimeHelper)0;
#endif
}
TR::Instruction *
OMR::Power::CodeGenerator::generateSwitchToInterpreterPrePrologue(
TR::Instruction *cursor,
TR::Node *node)
{
TR::Register *gr0 = self()->machine()->getRealRegister(TR::RealRegister::gr0);
TR::ResolvedMethodSymbol *methodSymbol = self()->comp()->getJittedMethodSymbol();
TR::SymbolReference *revertToInterpreterSymRef = self()->symRefTab()->findOrCreateRuntimeHelper(TR_PPCrevertToInterpreterGlue);
uintptr_t ramMethod = (uintptr_t)methodSymbol->getResolvedMethod()->resolvedMethodAddress();
TR::SymbolReference *helperSymRef = self()->symRefTab()->findOrCreateRuntimeHelper(directToInterpreterHelper(methodSymbol, self()));
uintptr_t helperAddr = (uintptr_t)helperSymRef->getMethodAddress();
// gr0 must contain the saved LR; see Recompilation.s
cursor = new (self()->trHeapMemory()) TR::PPCTrg1Instruction(TR::InstOpCode::mflr, node, gr0, cursor, self());
cursor = self()->getLinkage()->flushArguments(cursor);
cursor = generateDepImmSymInstruction(self(), TR::InstOpCode::bl, node, (uintptr_t)revertToInterpreterSymRef->getMethodAddress(), new (self()->trHeapMemory()) TR::RegisterDependencyConditions(0,0, self()->trMemory()), revertToInterpreterSymRef, NULL, cursor);
if (self()->comp()->target().is64Bit())
{
int32_t highBits = (int32_t)(ramMethod>>32), lowBits = (int32_t)ramMethod;
cursor = generateImmInstruction(self(), TR::InstOpCode::dd, node,
self()->comp()->target().cpu.isBigEndian()?highBits:lowBits, TR_RamMethod, cursor);
cursor = generateImmInstruction(self(), TR::InstOpCode::dd, node,
self()->comp()->target().cpu.isBigEndian()?lowBits:highBits, cursor);
}
else
{
cursor = generateImmInstruction(self(), TR::InstOpCode::dd, node, (int32_t)ramMethod, TR_RamMethod, cursor);
}
if (self()->comp()->getOption(TR_EnableHCR))
self()->comp()->getStaticHCRPICSites()->push_front(cursor);
if (self()->comp()->target().is64Bit())
{
int32_t highBits = (int32_t)(helperAddr>>32), lowBits = (int32_t)helperAddr;
cursor = generateImmInstruction(self(), TR::InstOpCode::dd, node,
self()->comp()->target().cpu.isBigEndian()?highBits:lowBits,
TR_AbsoluteHelperAddress, helperSymRef, cursor);
cursor = generateImmInstruction(self(), TR::InstOpCode::dd, node,
self()->comp()->target().cpu.isBigEndian()?lowBits:highBits, cursor);
}
else
{
cursor = generateImmInstruction(self(), TR::InstOpCode::dd, node, (int32_t)helperAddr, TR_AbsoluteHelperAddress, helperSymRef, cursor);
}
// Used in FSD to store an instruction
cursor = generateImmInstruction(self(), TR::InstOpCode::dd, node, 0, cursor);
return cursor;
}
void
OMR::Power::CodeGenerator::beginInstructionSelection()
{
TR::Node *firstNode = self()->comp()->getStartTree()->getNode();
_returnTypeInfoInstruction = NULL;
if ((self()->comp()->getJittedMethodSymbol()->getLinkageConvention() == TR_Private))
{
_returnTypeInfoInstruction = new (self()->trHeapMemory()) TR::PPCImmInstruction(TR::InstOpCode::dd, firstNode, 0, NULL, self());
}
generateAdminInstruction(self(), TR::InstOpCode::proc, firstNode);
}
void
OMR::Power::CodeGenerator::endInstructionSelection()
{
if (_returnTypeInfoInstruction != NULL)
{
_returnTypeInfoInstruction->setSourceImmediate(static_cast<uint32_t>(self()->comp()->getReturnInfo()));
}
}
void
OMR::Power::CodeGenerator::staticTracking(TR::SymbolReference *symRef)
{
if (self()->comp()->target().is64Bit())
{
TR_Array<TR::SymbolReference *> *symRefArray = self()->getTrackStatics();
int32_t idx;
for (idx=0; idx<symRefArray->size(); idx++)
if (symRefArray->element(idx) == symRef)
return;
symRefArray->add(symRef);
}
}
void
OMR::Power::CodeGenerator::itemTracking(
int32_t offset,
TR::LabelSymbol *label)
{
if (self()->comp()->target().is64Bit())
{
self()->getTrackItems()->add(new (self()->trHeapMemory()) TR_PPCLoadLabelItem(offset, label));
}
}
bool
OMR::Power::CodeGenerator::mulDecompositionCostIsJustified(
int numOfOperations,
char bitPosition[],
char operationType[],
int64_t value)
{
if (numOfOperations <= 0)
return false;
// Notice: the total simple operations is (2*numOfOperations-1). The following checking is a heuristic
// on processors we still care about.
switch (self()->comp()->target().cpu.getProcessorDescription().processor)
{
case OMR_PROCESSOR_PPC_PWR630: // 2S+1M FXU out-of-order
return (numOfOperations<=4);
case OMR_PROCESSOR_PPC_NSTAR:
case OMR_PROCESSOR_PPC_PULSAR: // 1S+1M FXU in-order
return (numOfOperations<=8);
case OMR_PROCESSOR_PPC_GPUL:
case OMR_PROCESSOR_PPC_GP:
case OMR_PROCESSOR_PPC_GR: // 2 FXU out-of-order back-to-back 2 cycles. Mul is only 4 to 6 cycles
return (numOfOperations<=2);
case OMR_PROCESSOR_PPC_P6: // Mul is on FPU for 17cycles blocking other operations
return (numOfOperations<=16);
case OMR_PROCESSOR_PPC_P7: // Mul blocks other operations for up to 4 cycles
return (numOfOperations<=3);
default: // assume a generic design similar to 604
return (numOfOperations<=3);
}
}
void OMR::Power::CodeGenerator::doRegisterAssignment(TR_RegisterKinds kindsToAssign)
{
TR::Instruction *prevInstruction;
// gprs, fprs, and ccrs are all assigned in backward direction
TR::Instruction *instructionCursor = self()->getAppendInstruction();
TR::Block *currBlock = NULL;
TR::Instruction * currBBEndInstr = instructionCursor;
if (!self()->comp()->getOption(TR_DisableOOL))
{
TR::list<TR::Register*> *spilledRegisterList = new (self()->trHeapMemory()) TR::list<TR::Register*>(getTypedAllocator<TR::Register*>(self()->comp()->allocator()));
self()->setSpilledRegisterList(spilledRegisterList);
}
if (self()->getDebug())
self()->getDebug()->startTracingRegisterAssignment();
while (instructionCursor)
{
prevInstruction = instructionCursor->getPrev();
self()->tracePreRAInstruction(instructionCursor);
self()->setCurrentBlockIndex(instructionCursor->getBlockIndex());
instructionCursor->assignRegisters(TR_GPR);
// Maintain Internal Control Flow Depth
// Track internal control flow on labels
if (instructionCursor->isLabel())
{
TR::PPCLabelInstruction *li = (TR::PPCLabelInstruction *)instructionCursor;
if (li->getLabelSymbol() != NULL)
{
if (li->getLabelSymbol()->isStartInternalControlFlow())
{
self()->decInternalControlFlowNestingDepth();
}
if (li->getLabelSymbol()->isEndInternalControlFlow())
{
self()->incInternalControlFlowNestingDepth();
}
}
}
self()->freeUnlatchedRegisters();
self()->buildGCMapsForInstructionAndSnippet(instructionCursor);
self()->tracePostRAInstruction(instructionCursor);
instructionCursor = prevInstruction;
}
if (self()->getDebug())
self()->getDebug()->stopTracingRegisterAssignment();
}
TR::Instruction *OMR::Power::CodeGenerator::generateNop(TR::Node *n, TR::Instruction *preced, TR_NOPKind nopKind)
{
TR::InstOpCode::Mnemonic nop;
switch (nopKind)
{
case TR_NOPEndGroup:
nop = TR::InstOpCode::genop;
break;
case TR_ProbeNOP:
nop = TR::InstOpCode::probenop;
break;
default:
nop = TR::InstOpCode::nop;
}
if (preced)
return new (self()->trHeapMemory()) TR::Instruction(nop, n, preced, self());
else
return new (self()->trHeapMemory()) TR::Instruction(nop, n, self());
}
TR::Instruction *OMR::Power::CodeGenerator::generateGroupEndingNop(TR::Node *node , TR::Instruction *preced)
{
if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6)) // handles P7, P8
{
preced = self()->generateNop(node , preced , TR_NOPEndGroup);
}
else
{
preced = self()->generateNop(node , preced);
preced = self()->generateNop(node , preced);
preced = self()->generateNop(node , preced);
}
return preced;
}
TR::Instruction *OMR::Power::CodeGenerator::generateProbeNop(TR::Node *node , TR::Instruction *preced)
{
preced = self()->generateNop(node , preced , TR_ProbeNOP);
return preced;
}
bool OMR::Power::CodeGenerator::checkAndFetchRequestor(TR::Instruction *instr, TR::Instruction **q)
{
if (_constantData)
{
return _constantData->getRequestorsFromNibble(instr, q, true);
}
return false;
}
bool OMR::Power::CodeGenerator::supportsAESInstructions()
{
if ( self()->comp()->target().cpu.getPPCSupportsAES() && !self()->comp()->getOption(TR_DisableAESInHardware))
return true;
else
return false;
}
TR::CodeGenerator::TR_RegisterPressureSummary *
OMR::Power::CodeGenerator::calculateRegisterPressure()
{
return NULL;
}
TR::Linkage *
OMR::Power::CodeGenerator::createLinkage(TR_LinkageConventions lc)
{
TR::Linkage *linkage = NULL;
switch (lc)
{
case TR_System:
linkage = new (self()->trHeapMemory()) TR::PPCSystemLinkage(self());
break;
default:
linkage = new (self()->trHeapMemory()) TR::PPCSystemLinkage(self());
}
self()->setLinkage(lc, linkage);
return linkage;
}
void
OMR::Power::CodeGenerator::expandInstructions()
{
_binaryEncodingData.estimate = 0;
self()->generateBinaryEncodingPrologue(&_binaryEncodingData);
generateLabelInstruction(
self(),
TR::InstOpCode::label,
self()->comp()->getStartTree()->getNode(),
self()->getStartPCLabel(),
_binaryEncodingData.preProcInstruction
);
for (TR::Instruction *instr = self()->getFirstInstruction(); instr; instr = instr->getNext())
{
instr = instr->expandInstruction();
}
}
void OMR::Power::CodeGenerator::generateBinaryEncodingPrologue(
TR_PPCBinaryEncodingData *data)
{
TR::Compilation *comp = self()->comp();
data->recomp = NULL;
data->cursorInstruction = self()->getFirstInstruction();
data->preProcInstruction = data->cursorInstruction;
data->jitTojitStart = data->cursorInstruction;
data->cursorInstruction = NULL;
self()->getLinkage()->loadUpArguments(data->cursorInstruction);
data->cursorInstruction = self()->getFirstInstruction();
while (data->cursorInstruction && data->cursorInstruction->getOpCodeValue() != TR::InstOpCode::proc)
{
data->estimate = data->cursorInstruction->estimateBinaryLength(data->estimate);
data->cursorInstruction = data->cursorInstruction->getNext();
}
if (self()->supportsJitMethodEntryAlignment())
{
self()->setPreJitMethodEntrySize(data->estimate);
data->estimate += (self()->getJitMethodEntryAlignmentBoundary() - 1);
}
self()->getLinkage()->createPrologue(data->cursorInstruction);
}
static void expandFarConditionalBranches(TR::CodeGenerator *cg)
{
for (TR::Instruction *instr = cg->getFirstInstruction(); instr; instr = instr->getNext())
{
TR::PPCConditionalBranchInstruction *branch = instr->getPPCConditionalBranchInstruction();
if (branch && branch->getLabelSymbol())
{
int32_t distance = branch->getLabelSymbol()->getEstimatedCodeLocation() - branch->getEstimatedBinaryLocation();
if (distance < (int32_t)TR::getMinSigned<TR::Int16>() || distance > (int32_t)TR::getMaxSigned<TR::Int16>())
branch->expandIntoFarBranch();
}
}
}